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Drivers/IPU: fix a potential panic issue and remove unsed codes.

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Signed-off-by: Siwei Xu <xusiwei1@hisilicon.com>
This commit is contained in:
Siwei Xu
2018-03-15 15:20:09 +08:00
committed by Guodong Xu
parent 1d2cd9e4bd
commit 495c89ef5b
11 changed files with 28 additions and 1495 deletions
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drivers/hisi/ics/Kconfig
-6
View File
@@ -25,12 +25,6 @@ config HISI_IPU_SET_VCODECBUS
help help
Allow IPU Driver to set VCODEC bus clock rate. Allow IPU Driver to set VCODEC bus clock rate.
config HISI_IPU_MNTN
tristate "Enable IPU Driver maintain function"
default n
help
Enable IPU Driver maintain function.
config HISI_IPU_REGULATOR config HISI_IPU_REGULATOR
tristate "Enable IPU Driver regulator control" tristate "Enable IPU Driver regulator control"
default n default n
drivers/hisi/ics/Makefile
-5
View File
@@ -5,10 +5,5 @@ endif
obj-$(CONFIG_HISI_ICS_IPU) += cambricon_ipu.o obj-$(CONFIG_HISI_ICS_IPU) += cambricon_ipu.o
obj-$(CONFIG_HISI_ICS_IPU) += ipu_smmu_drv.o obj-$(CONFIG_HISI_ICS_IPU) += ipu_smmu_drv.o
obj-$(CONFIG_HISI_ICS_IPU) += ipu_clock.o obj-$(CONFIG_HISI_ICS_IPU) += ipu_clock.o
obj-$(CONFIG_HISI_IPU_MNTN) += ipu_mntn.o
ifneq ($(TARGET_BUILD_VARIANT),user)
obj-$(CONFIG_HISI_ICS_IPU) += ics_debug_proxy.o
obj-y += ics_debug.o
endif
EXTRA_CFLAGS += -I$(srctree)/drivers/hisi/ap/platform/kirin970 EXTRA_CFLAGS += -I$(srctree)/drivers/hisi/ap/platform/kirin970
drivers/hisi/ics/cambricon_ipu.c
+20 -61
View File
@@ -56,7 +56,6 @@
#include "ipu_smmu_drv.h" #include "ipu_smmu_drv.h"
#include "ipu_clock.h" #include "ipu_clock.h"
#include "cambricon_ipu.h" #include "cambricon_ipu.h"
// #include "ipu_mntn.h"
#define COMP_CAMBRICON_IPU_DRV_NAME "hisilicon,cambricon-ipu" #define COMP_CAMBRICON_IPU_DRV_NAME "hisilicon,cambricon-ipu"
@@ -699,20 +698,7 @@ bool ipu_get_feature_tree (struct device *dev)
} }
memset(&adapter->feature_tree, 0, sizeof(adapter->feature_tree));// coverity[secure_coding] memset(&adapter->feature_tree, 0, sizeof(adapter->feature_tree));// coverity[secure_coding]
if (strncmp(str, "kirin970_es", sizeof("kirin970_es")) == 0) { if (strncmp(str, "kirin970_cs", sizeof("kirin970_cs")) == 0) {
adapter->feature_tree.finish_irq_expand_ns = false;
adapter->feature_tree.finish_irq_expand_p = false;
adapter->feature_tree.finish_irq_expand_s = false;
adapter->feature_tree.finish_irq_to_hifi = false;
adapter->feature_tree.finish_irq_to_ivp = false;
adapter->feature_tree.finish_irq_to_isp = false;
adapter->feature_tree.finish_irq_to_lpm3 = false;
adapter->feature_tree.finish_irq_to_iocmu = false;
adapter->feature_tree.smmu_port_select = false;
adapter->feature_tree.soft_watchdog_enable = false;
adapter->feature_tree.ipu_reset_when_in_error = IPU_RESET_UNSUPPORT;
adapter->feature_tree.ipu_bandwidth_lmt = IPU_BANDWIDTH_LMT_UNSUPPORT;
} else if (strncmp(str, "kirin970_cs", sizeof("kirin970_cs")) == 0) {
adapter->feature_tree.finish_irq_expand_ns = true; adapter->feature_tree.finish_irq_expand_ns = true;
adapter->feature_tree.finish_irq_expand_p = true; adapter->feature_tree.finish_irq_expand_p = true;
adapter->feature_tree.finish_irq_expand_s = true; adapter->feature_tree.finish_irq_expand_s = true;
@@ -744,14 +730,12 @@ int regulator_ip_vipu_enable(void)
ret = regulator_is_enabled(adapter->vipu_ip); ret = regulator_is_enabled(adapter->vipu_ip);
if (ret) { if (ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:regulator_is_enabled: %d\n", __func__, ret); printk(KERN_ERR"[%s]:IPU_ERROR:regulator_is_enabled: %d\n", __func__, ret);
// rdr_system_error((unsigned int)MODID_NPU_EXC_SET_POWER_UP_STATUS_FAULT, 0, 0);
return -EBUSY; return -EBUSY;
} }
ret = regulator_enable(adapter->vipu_ip); ret = regulator_enable(adapter->vipu_ip);
if (0 != ret) { if (0 != ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:Failed to enable: %d\n", __func__, ret); printk(KERN_ERR"[%s]:IPU_ERROR:Failed to enable: %d\n", __func__, ret);
// rdr_system_error((unsigned int)MODID_NPU_EXC_SET_POWER_UP_FAIL, 0, 0);
return ret; return ret;
} }
#endif #endif
@@ -766,7 +750,6 @@ int regulator_ip_vipu_disable(void)
ret = regulator_disable(adapter->vipu_ip); ret = regulator_disable(adapter->vipu_ip);
if (ret != 0) { if (ret != 0) {
printk(KERN_ERR"[%s]:IPU_ERROR:Failed to disable: %d\n", __func__, ret); printk(KERN_ERR"[%s]:IPU_ERROR:Failed to disable: %d\n", __func__, ret);
// rdr_system_error((unsigned int)MODID_NPU_EXC_SET_POWER_DOWN_FAIL, 0, 0);
return ret; return ret;
} }
#endif #endif
@@ -1379,7 +1362,6 @@ static irqreturn_t ipu_interrupt_handler(int irq, void *dev)
if (ipu_smmu_err_isr) { if (ipu_smmu_err_isr) {
if (adapter->feature_tree.ipu_reset_when_in_error && adapter->reset_va) { if (adapter->feature_tree.ipu_reset_when_in_error && adapter->reset_va) {
// rdr_system_error((unsigned int)MODID_NPU_EXC_INTERRUPT_ABNORMAL, 0, 0);
ipu_reset_proc((unsigned int)adapter->reset_va); //lint !e570 ipu_reset_proc((unsigned int)adapter->reset_va); //lint !e570
} }
} else { } else {
@@ -1414,6 +1396,7 @@ static irqreturn_t ipu_interrupt_handler(int irq, void *dev)
static int ipu_reset(void *arg) static int ipu_reset(void *arg)
{ {
static unsigned long last_computed_task = 0; static unsigned long last_computed_task = 0;
unsigned int peri_stat, ppll_select, power_stat, power_ack, reset_stat, perclken0, perstat0;
#ifdef CONFIG_HUAWEI_DSM #ifdef CONFIG_HUAWEI_DSM
char register_info_flag[] = "NULL"; char register_info_flag[] = "NULL";
@@ -1429,18 +1412,6 @@ static int ipu_reset(void *arg)
mutex_lock(&adapter->power_mutex); mutex_lock(&adapter->power_mutex);
/* WTD time out, report to DSM */
#ifdef CONFIG_HUAWEI_DSM
if (last_computed_task != adapter->computed_task_cnt){
ipu_smmu_dump_strm();
perr = register_info;
}
#endif /* CONFIG_HUAWEI_DSM */
DSM_AI_KERN_ERROR_REPORT(DSM_AI_KERN_WTD_TIMEOUT_ERR_NO,
"IPU soft watchdog timeout, ipu_status=%d, ttbr0=%x, inst_set=%d, offchip{set=%x, base=%x}, last_computed_task=%d, register_info=%s.\n",
adapter->ipu_power_up, adapter->smmu_ttbr0, adapter->boot_inst_set.boot_inst_recorded_is_config, adapter->boot_inst_set.access_ddr_addr_is_config,
adapter->boot_inst_set.ipu_access_ddr_addr, adapter->computed_task_cnt, perr);
if (false == adapter->ipu_power_up) { if (false == adapter->ipu_power_up) {
printk(KERN_ERR"[%s]: IPU_ERROR: ipu is power off, can not resume\n", __func__); printk(KERN_ERR"[%s]: IPU_ERROR: ipu is power off, can not resume\n", __func__);
mutex_unlock(&adapter->power_mutex); mutex_unlock(&adapter->power_mutex);
@@ -1453,31 +1424,30 @@ static int ipu_reset(void *arg)
__func__, adapter->ipu_power_up, adapter->smmu_ttbr0, adapter->boot_inst_set.boot_inst_recorded_is_config, __func__, adapter->ipu_power_up, adapter->smmu_ttbr0, adapter->boot_inst_set.boot_inst_recorded_is_config,
adapter->boot_inst_set.access_ddr_addr_is_config, adapter->boot_inst_set.ipu_access_ddr_addr, adapter->computed_task_cnt); adapter->boot_inst_set.access_ddr_addr_is_config, adapter->boot_inst_set.ipu_access_ddr_addr, adapter->computed_task_cnt);
#ifdef CONFIG_HISI_IPU_MNTN
/* get clock and power status in register */ /* get clock and power status in register */
ipu_reg_info.peri_reg.peri_stat = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.peristat7); peri_stat = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.peristat7);
ipu_reg_info.peri_reg.ppll_select = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.clkdiv8); ppll_select = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.clkdiv8);
ipu_reg_info.peri_reg.power_stat = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.perpwrstat); power_stat = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.perpwrstat);
ipu_reg_info.peri_reg.power_ack = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.perpwrack); power_ack = ioread32((void *)adapter->peri_io_addr + adapter->peri_reg_offset.perpwrack);
ipu_reg_info.peri_reg.reset_stat = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perrststat0); reset_stat = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perrststat0);
ipu_reg_info.peri_reg.perclken0 = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perclken0); perclken0 = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perclken0);
ipu_reg_info.peri_reg.perstat0 = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perstat0); perstat0 = ioread32((void *)adapter->media2_io_addr + adapter->media2_reg_offset.perstat0);
printk(KERN_ERR"[%s]: peri_stat=%x, ppll_select=%x, power_stat=%x, power_ack=%x, reset_stat=%x, perclken=%x, perstat=%x\n", printk(KERN_ERR"[%s]: peri_stat=%x, ppll_select=%x, power_stat=%x, power_ack=%x, reset_stat=%x, perclken=%x, perstat=%x\n",
__func__, __func__, peri_stat, ppll_select, power_stat, power_ack, reset_stat, perclken0, perstat0);
ipu_reg_info.peri_reg.peri_stat,
ipu_reg_info.peri_reg.ppll_select,
ipu_reg_info.peri_reg.power_stat,
ipu_reg_info.peri_reg.power_ack,
ipu_reg_info.peri_reg.reset_stat,
ipu_reg_info.peri_reg.perclken0,
ipu_reg_info.peri_reg.perstat0);
#endif
/* get memory info in register */ /* get memory info in register */
ipu_smmu_dump_strm(); ipu_smmu_dump_strm();
// rdr_system_error((unsigned int)MODID_NPU_EXC_DEAD, 0, 0); /* WTD time out, report to DSM */
} #ifdef CONFIG_HUAWEI_DSM
perr = register_info;
DSM_AI_KERN_ERROR_REPORT(DSM_AI_KERN_WTD_TIMEOUT_ERR_NO,
"IPU soft watchdog timeout, ipu_status=%d, ttbr0=%x, inst_set=%d, offchip{set=%x, base=%x}, last_computed_task=%d, register_info=%s.\n",
adapter->ipu_power_up, adapter->smmu_ttbr0, adapter->boot_inst_set.boot_inst_recorded_is_config, adapter->boot_inst_set.access_ddr_addr_is_config,
adapter->boot_inst_set.ipu_access_ddr_addr, adapter->computed_task_cnt, perr);
#endif /* CONFIG_HUAWEI_DSM */
}
/* reset ipu */ /* reset ipu */
ipu_reset_proc((unsigned int)adapter->reset_va); ipu_reset_proc((unsigned int)adapter->reset_va);
@@ -2648,14 +2618,6 @@ static int cambricon_ipu_probe(struct platform_device *pdev)
#endif #endif
#ifdef CONFIG_HISI_IPU_MNTN
err = ipu_mntn_rdr_init();
if (err) {
printk(KERN_ERR"[%s]: Call ipu_mntn_rdr_init is failed!ret=%d\n", __func__, err);
goto exit_error;
}
#endif
ipu_watchdog_init(&adapter->reset_wtd, adapter->feature_tree.soft_watchdog_enable, ipu_reset_irq); ipu_watchdog_init(&adapter->reset_wtd, adapter->feature_tree.soft_watchdog_enable, ipu_reset_irq);
sema_init(&(adapter->reset_wtd.sem), 0); sema_init(&(adapter->reset_wtd.sem), 0);
@@ -2828,9 +2790,6 @@ static void __exit cambricon_ipu_exit(void)
{ {
platform_device_unregister(&cambricon_ipu_device); platform_device_unregister(&cambricon_ipu_device);
platform_driver_unregister(&cambricon_ipu_driver); platform_driver_unregister(&cambricon_ipu_driver);
#ifdef CONFIG_HISI_IPU_MNTN
destroy_workqueue(ipu_mntn_rdr_wq);
#endif
} }
/*lint -e753 -e528*/ /*lint -e753 -e528*/
drivers/hisi/ics/ics_debug.c
-803
View File
@@ -1,803 +0,0 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/cdev.h>
#include <linux/device.h>
#include <linux/sysfs.h>
#include "ics_debug.h"
#define CLASS_NAME "ics_debug"
#define UNMASK_LPM3 (0)
#define UNMASK_IOMCU (1)
#define UNMASK_ISP (2)
#define UNMASK_IVP (3)
#define UNMASK_HIFI (4)
#define PERI_OFFSET_PEREN0 (0x000)
#define PERI_OFFSET_PERDIS0 (0x004)
#define PERI_OFFSET_PEREN6 (0x410)
#define PERI_OFFSET_PERDIS6 (0x414)
#define PERI_OFFSET_PERRSTEN4 (0x090)
#define PERI_OFFSET_PERRSTDIS4 (0x094)
#define PERI_OFFSET_CLKDIV18 (0x0F0)
#define PERI_OFFSET_PERPWREN (0x150)
#define PERI_OFFSET_PERPWRDIS (0x154)
#define PERI_OFFSET_ISOEN (0x144)
#define PERI_OFFSET_ISODIS (0x148)
#define PERI_OFFSET_CLKDIV5 (0x0bc)
#define PERI_OFFSET_CLKDIV8 (0x0c8)
#define PERI_OFFSET_CLKDIV15 (0x0e4)
#define PERI_ISOEN_ICS_ISO_EN (0x00000100)
#define PERI_ISODIS_ICS_ISO_UN (0x00000100)
#define PERI_CLKDIV8_SEL_ICS_PLL2 (0xf0004000)
#define PERI_CLKDIV8_SEL_ICS_PLL0 (0xf0002000)
#define PERI_PERPWREN_ICSPWREN_EN (0x00000100)
#define PERI_PERPWRDIS_ICS_PWR_DIS (0x00000100)
#define PERI_PERRSTDIS4_IP_RST_MEDIA2 (0x00000001)
#define PERI_CLKDIV15_SEL_FREQ_DIV4_ICS (0x7e000600)
#define PERI_PERRSTEN4_IP_RST_MEDIA_CRG (0x00000002)
#define PERI_CLKDIV8_SEL_VCODECBUS_PLL2 (0x000f0004)
#define PERI_CLKDIV8_SEL_VCODECBUS_PLL0 (0x000f0002)
#define PERI_CLKDIV15_SEL_FREQ_DIV3_ICS (0x7e000400)
#define PERI_CLKDIV15_SEL_FREQ_DIV2_ICS (0x7e000200)
#define PERI_CLKDIV18_SC_GT_CLK_ICS__EN (0x40000000)
#define PERI_PERRSTEN4_IP_RST_MEDIA2_EN (0x00000001)
#define PERI_CLKDIV18_SC_GT_CLK_VCODEBUS_EN (0x01000000)
#define PERI_CLKDIV5_SET_FREQ_DIV4_VCODECBUS (0x003f0003)
#define PERI_CLKDIV5_SET_FREQ_DIV5_VCODECBUS (0x003f0004)
#define PERI_CLKDIV5_SET_FREQ_DIV8_VCODECBUS (0x003f0007)
#define PERI_PEREN0_GT_CLK_VCODECBUS2DDRC_EN (0x00000020)
#define PERI_PERRSTDIS4_IP_RST_MEDIA2_CRG_EN (0x00000002)
#define PERI_PERDIS0_GT_CLK_VCODECBUS2DDRC_UN (0x00000020)
#define PERI_CLKDIV18_SC_GT_CLK_ICS_OPEN_AND_EN (0x40004000)
#define PERI_CLKDIV18_SC_GT_CLK_VCODEBUS_OPEN_AND_EN (0x01000100)
#define PERI_PEREN6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN (0x00010200)
#define PERI_PERDIS6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN (0x00010200)
#define MEDIA2_OFFSET_PEREN0 (0x000)
#define MEDIA2_OFFSET_PERDIS0 (0x004)
#define MEDIA2_OFFSET_PERRSTEN0 (0x030)
#define MEDIA2_OFFSET_PERRSTDIS0 (0x034)
#define MEDIA2_PEREN0_GT_CLK_VCODEBUS_EN (0x00000200)
#define MEDIA2_PERDIS0_GT_CLK_VCODEBUS_UN (0x00000200)
#define MEDIA2_PEREN0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN (0x00000007)
#define MEDIA2_PERDIS0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN (0x00000007)
#define MEDIA2_PERRSTEN0_IP_RST_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN (0x00000038)
#define MEDIA2_PERRSTDIS0_IP_RST_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN (0x00000038)
#define PMCTRL_OFFSET_NOC_POWER_IDLEREQ_0 (0x380)
#define PMCTRL_OFFSET_NOC_POWER_IDLEACK_0 (0x384)
#define PMCTRL_OFFSET_NOC_POWER_IDLE_0 (0x388)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE (0x200)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE_UN (0x0)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE_EN (0x200)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK (0x200)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK_UN (0x0)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK_EN (0x200)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK (0x10)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS (0x10)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK_UN (0x0)
#define PMCTRL_NOC_POWER_IDLEREQ_0_NOC_ICS_POWER_IDLEREQ_EN (0x02000000)
#define PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK_EN (0x10)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS_UN (0x0)
#define PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS_EN (0x10)
#define PMCTRL_NOC_POWER_IDLEREQ_0_NOC_ICS_POWER_IDLEREQ_REQ_AND_EN (0x02000200)
#define PMCTRL_NOC_NOC_POWER_IDLEREQ_0_NOC_VCODEC_BUS_POWER_IDLEREQ_EN (0x00100000)
#define PMCTRL_NOC_NOC_POWER_IDLEREQ_0_NOC_VCODEC_BUS_POWER_IDLEREQ_REQ_AND_EN (0x00100010)
#define CONFIG_REG_VIRT_ADDR_OFFSET_ICS_VERSION (0x40)
#define CONFIG_REG_VIRT_ADDR_OFFSET_ICS_BASE_ADDR (0x28)
#define ICS_IRQ_OFFSET_ICS_IRQ_MASK_LPMCU_FINISH (0x20)
#define ICS_IRQ_OFFSET_ICS_IRQ_MASK_IOMCU_FINISH (0x30)
#define ICS_IRQ_OFFSET_ICS_IRQ_MASK_ISPCPU_FINISH (0x40)
#define ICS_IRQ_OFFSET_ICS_IRQ_MASK_IVP_FINISH (0x50)
#define ICS_IRQ_OFFSET_ICS_IRQ_MASK_HIFI_FINISH (0x60)
static struct class *ics_class;
struct cambricon_ipu_private *ics_adapter;
static uint32_t setclkrate = 0;
static uint32_t setprofile = 0;
static uint32_t ipuopen = 0;
static uint32_t ipurelease = 0;
static uint32_t ipuversion = 0;
static uint32_t resetproc = 0;
static uint32_t ipurstcrtenv = 0;
static uint32_t ipurstdstenv = 0;
static uint32_t pusetreg = 0;
static uint32_t pdsetreg = 0;
static uint32_t rdcorereg = 0;
static uint32_t wrcorereg = 0;
static uint32_t wrregvbusclk = 0;
static uint32_t wrregcnnclk = 0;
static uint32_t wrreglmt = 0;
struct ics_test_iomap_addr {
void __iomem *pmctrl_io_addr;
void __iomem *pctrl_io_addr;
void __iomem *sctrl_io_addr;
void __iomem *media_io_addr;
void __iomem *peri_io_addr;
};
struct ics_test_iomap_addr ics_test_iomap_addr;
unsigned long smmu_ttbr0_bk = 0;
static ssize_t setclkrate_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "setclkrate:0x%x!\n", setclkrate);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo clockRate>setclkrate\n");
return ret;
}
static ssize_t setclkrate_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
if (sscanf(buf, "%d", &setclkrate) != 1)
return -EINVAL;
printk(KERN_DEBUG"[%s]: setclkrate_store begin\n", __FUNCTION__);
ics_adapter->clk.start_rate = setclkrate;
if (ret) {
printk(KERN_ERR"[%s]: call_ipu_clock_start failed\n", __FUNCTION__);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]: setclkrate_store end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t setprofile_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "setprofile:0x%x!\n", setprofile);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo profile>setprofile\n");
return ret;
}
static ssize_t setprofile_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
if (sscanf(buf, "%d", &setprofile) != 1)
return -EINVAL;
printk(KERN_DEBUG"[%s]: setclkrate_store begin\n", __FUNCTION__);
call_ipu_set_profile(setprofile);
if (ret) {
printk(KERN_ERR"[%s]: ipu_clock_set_profile failed\n", __FUNCTION__);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]: setprofile_store end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t ipuopen_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
ret = snprintf(buf, PAGE_SIZE, "ipuopen:0x%x!\n", ipuopen);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>ipuopen\n");
return ret;
}
static ssize_t ipuopen_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
printk(KERN_DEBUG"[%s]: ipuopen_store begin\n", __FUNCTION__);
ret = call_regulator_ip_vipu_enable();
if (ret) {
printk(KERN_ERR"[%s]: call_regulator_ip_vipu_enable failed\n", __FUNCTION__);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]: call_regulator_ip_vipu_enable ok\n", __FUNCTION__);
call_ipu_clock_start(&ics_adapter->clk);
if (ret) {
printk(KERN_ERR"[%s]: IPU clock start failed\n", __FUNCTION__);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]: call_ipu_clock_start ok\n", __FUNCTION__);
call_ipu_smmu_init(ics_adapter->smmu_ttbr0,
(unsigned long)ics_adapter->smmu_rw_err_phy_addr, ics_adapter->feature_tree.smmu_port_select, ics_adapter->feature_tree.smmu_mstr_hardware_start);
printk(KERN_DEBUG"[%s]: call_ipu_smmu_init ok\n", __FUNCTION__);
call_ipu_interrupt_init();
printk(KERN_DEBUG"[%s]: call_ipu_interrupt_init ok\n", __FUNCTION__);
printk(KERN_DEBUG"[%s]: ipuopen_store end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t ipurelease_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
ret = snprintf(buf, PAGE_SIZE, "ipurelease:0x%x!\n", ipurelease);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>ipurelease\n");
return ret;
}
static ssize_t ipurelease_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
printk(KERN_DEBUG"[%s]: ipurelease_store begin\n", __FUNCTION__);
call_ipu_clock_set_rate(&ics_adapter->clk, ics_adapter->clk.stop_rate);
printk(KERN_DEBUG"[%s]: call_ipu_clock_set_rate ok\n", __FUNCTION__);
call_ipu_clock_stop(&ics_adapter->clk);
printk(KERN_DEBUG"[%s]: call_ipu_clock_stop ok\n", __FUNCTION__);
ret = call_regulator_ip_vipu_disable();
if (ret) {
printk(KERN_ERR"[%s]: No IPU device!\n", __FUNCTION__);
return -EBUSY;
}
printk(KERN_DEBUG"[%s]: call_regulator_ip_vipu_disable ok\n", __FUNCTION__);
ics_adapter->ipu_device_opened = 0;
printk(KERN_DEBUG"[%s]: ipurelease_store end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t ipuversion_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
unsigned int regval;
regval = ioread32((void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_VERSION));
ret = snprintf(buf, PAGE_SIZE, "ipuversion:0x%x, register value: 0x%x!\n", ipuversion, regval);
DEBUG("read version %x, cached %d", regval, ipuversion);
return ret;
}
static ssize_t ipuversion_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
int ret = 0, ver = 0;
if (sscanf(buf, "%x", &ver) != 1) {
printk(KERN_ERR "[%s]: version error, invalid number format!\n", __FUNCTION__);
return -EINVAL;
}
ipuversion = ver;
iowrite32(ver, (void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_VERSION));
DEBUG("write version %x", ver);
return (ssize_t)size;
}
static ssize_t resetproc_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
ret = snprintf(buf, PAGE_SIZE, "resetproc:0x%x!\n", resetproc);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>resetproc\n");
return ret;
}
static ssize_t resetproc_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
printk(KERN_DEBUG"[%s]: begin\n", __FUNCTION__);
call_ipu_reset_proc((unsigned int)ics_adapter->reset_va);
printk(KERN_DEBUG"[%s]: end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t ipurstcrtenv_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
ret = snprintf(buf, PAGE_SIZE, "ipu reset create environment:0x%x!\n", ipurstcrtenv);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>ipurstcrtenv (no need to pu ipu)\n");
return ret;
}
static ssize_t ipurstcrtenv_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
printk(KERN_DEBUG"[%s]: begin\n", __FUNCTION__);
smmu_ttbr0_bk = ics_adapter->smmu_ttbr0;
ics_adapter->smmu_ttbr0 = smmu_ttbr0_bk & 0xffffffff;
printk(KERN_DEBUG"[%s]: end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t ipurstdstenv_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
ret = snprintf(buf, PAGE_SIZE, "ipu reset destroy environment:0x%x!\n", ipurstdstenv);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>ipurstcrtenv (no need to pu ipu)\n");
return ret;
}
static ssize_t ipurstdstenv_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
printk(KERN_DEBUG"[%s]: begin\n", __FUNCTION__);
ics_adapter->smmu_ttbr0 = smmu_ttbr0_bk;
printk(KERN_DEBUG"[%s]: end\n", __FUNCTION__);
return (ssize_t)size;
}
static ssize_t pusetreg_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "pusetreg:0x%x!\n", pusetreg);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>pusetreg\n");
return ret;
}
static ssize_t pusetreg_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
unsigned int read_value;
printk(KERN_DEBUG"[%s]: peri_io_addr:%p, media2_io_addr:%p, pmctrl_io_addr=%p\n", __FUNCTION__,
ics_adapter->peri_io_addr, ics_adapter->media2_io_addr, ics_adapter->pmctrl_io_addr);
//set_pu_media2_subsys
printk(KERN_DEBUG"[%s]:meidia module unrst\n",__FUNCTION__);
iowrite32(PERI_PERRSTDIS4_IP_RST_MEDIA2_CRG_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERRSTDIS4));
printk(KERN_DEBUG"[%s]:meidia module clk enable\n",__FUNCTION__);
iowrite32(PERI_PEREN6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PEREN6));
udelay(1);
printk(KERN_DEBUG"[%s]:meidia module clk disable\n",__FUNCTION__);
iowrite32(PERI_PERDIS6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERDIS6));
udelay(1);
printk(KERN_DEBUG"[%s]:meidia module unrst\n",__FUNCTION__);
iowrite32(PERI_PERRSTDIS4_IP_RST_MEDIA2, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERRSTDIS4));
printk(KERN_DEBUG"[%s]:meidia module clk enable\n",__FUNCTION__);
iowrite32(PERI_PEREN6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PEREN6));
//set_pu_vcodec
printk(KERN_DEBUG"[%s]:vcodec module clk enable\n",__FUNCTION__);
iowrite32(PERI_CLKDIV18_SC_GT_CLK_VCODEBUS_OPEN_AND_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV18));
iowrite32(MEDIA2_PEREN0_GT_CLK_VCODEBUS_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PEREN0));
iowrite32(PERI_PEREN0_GT_CLK_VCODECBUS2DDRC_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PEREN0));
udelay(1);
printk(KERN_DEBUG"[%s]:vcodec module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PERDIS0_GT_CLK_VCODEBUS_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERDIS0));
iowrite32(PERI_PERDIS0_GT_CLK_VCODECBUS2DDRC_UN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERDIS0));
udelay(1);
printk(KERN_DEBUG"[%s]:vcodec module clk enable\n",__FUNCTION__);
iowrite32(MEDIA2_PEREN0_GT_CLK_VCODEBUS_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PEREN0));
iowrite32(PERI_PEREN0_GT_CLK_VCODECBUS2DDRC_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PEREN0));
printk(KERN_DEBUG"[%s]:vcodec bus idle clear\n",__FUNCTION__);
iowrite32(PMCTRL_NOC_NOC_POWER_IDLEREQ_0_NOC_VCODEC_BUS_POWER_IDLEREQ_EN, (void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEREQ_0));
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEACK_0));
if ((PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK & PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK_UN) != 0x0) {
printk(KERN_ERR"[%s]: pu_codec:no expect power idleack value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr + PMCTRL_OFFSET_NOC_POWER_IDLE_0));
if ((read_value & PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS) != PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS_UN) {
printk(KERN_ERR"[%s]: pu_codec:no expect power idle value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
//set_pu_ics
printk(KERN_DEBUG"[%s]:ipu module mtcmos on\n",__FUNCTION__);
iowrite32(PERI_PERPWREN_ICSPWREN_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERPWREN));
udelay(100);
printk(KERN_DEBUG"[%s]:ipu module clk enable\n",__FUNCTION__);
iowrite32(PERI_CLKDIV18_SC_GT_CLK_ICS_OPEN_AND_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV18));
iowrite32(MEDIA2_PEREN0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PEREN0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PERDIS0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERDIS0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module iso disable\n",__FUNCTION__);
iowrite32(PERI_ISODIS_ICS_ISO_UN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_ISODIS));
printk(KERN_DEBUG"[%s]:ipu module unrst\n",__FUNCTION__);
iowrite32(MEDIA2_PERRSTDIS0_IP_RST_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERRSTDIS0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module clk enable\n",__FUNCTION__);
iowrite32(MEDIA2_PEREN0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PEREN0));
printk(KERN_DEBUG"[%s]:ipu bus idle clear\n",__FUNCTION__);
iowrite32(PMCTRL_NOC_POWER_IDLEREQ_0_NOC_ICS_POWER_IDLEREQ_EN, (void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEREQ_0));
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEACK_0));
if ((read_value & PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK) != PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK_UN) {
printk(KERN_ERR"[%s]: pu_ics:no expect power idleack value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLE_0));
if ((read_value & PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE) != PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE_UN) {
printk(KERN_ERR"[%s]: pu_ics:no expect power idle value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
return (ssize_t)size;
}
static ssize_t pdsetreg_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "pdsetreg:0x%x!\n", pdsetreg);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>pdsetreg\n");
return ret;
}
static ssize_t pdsetreg_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
unsigned int read_value;
//set_pd_ics
printk(KERN_DEBUG"[%s]:ipu bus idle set\n",__FUNCTION__);
iowrite32(PMCTRL_NOC_POWER_IDLEREQ_0_NOC_ICS_POWER_IDLEREQ_REQ_AND_EN, (void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEREQ_0));
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEACK_0));
if((read_value & PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK) != PMCTRL_NOC_POWER_IDLEACK_0_NOC_ICS_POWER_IDLEACK_EN) {
printk(KERN_ERR"[%s]: pd_ics:no expect power idleack value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLE_0));
if((read_value & PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE) != PMCTRL_NOC_POWER_IDLE_0_NOC_ICS_POWER_IDLE_EN) {
printk(KERN_ERR"[%s]: pd_ics:no expect power idle value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]:ipu module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PERDIS0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERDIS0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module rst\n",__FUNCTION__);
iowrite32(MEDIA2_PERRSTEN0_IP_RST_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERRSTEN0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PEREN0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_EN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PEREN0));
udelay(1);
printk(KERN_DEBUG"[%s]:ipu module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PERDIS0_GT_CLK_ICS_AND_NOC_ICS_AND_NOC_ICS_CFG_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERDIS0));
iowrite32(PERI_CLKDIV18_SC_GT_CLK_ICS__EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV18));
printk(KERN_DEBUG"[%s]:ipu module iso\n",__FUNCTION__);
iowrite32(PERI_ISOEN_ICS_ISO_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_ISOEN));
printk(KERN_DEBUG"[%s]:ipu module mtcmos off\n",__FUNCTION__);
iowrite32(PERI_PERPWRDIS_ICS_PWR_DIS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERPWRDIS));
//set_pd_vcodec
printk(KERN_DEBUG"[%s]:vcodec bus idle set\n",__FUNCTION__);
iowrite32(PMCTRL_NOC_NOC_POWER_IDLEREQ_0_NOC_VCODEC_BUS_POWER_IDLEREQ_REQ_AND_EN, (void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEREQ_0));
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLEACK_0));
if((read_value & PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK) != PMCTRL_NOC_POWER_IDLEACK_0_NOC_VCODEC_BUS_POWER_IDLEACK_EN) {
printk(KERN_ERR"[%s]: pd_codec:no expect power idleack value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->pmctrl_io_addr+ PMCTRL_OFFSET_NOC_POWER_IDLE_0));
if((read_value & PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS) != PMCTRL_NOC_POWER_IDLE_0_NOC_VCODEC_BUS_POWER_IDLE_STATUS_EN) {
printk(KERN_ERR"[%s]: pd_codec:no expect power idle value:%d!\n",
__FUNCTION__ , read_value);
return -EINVAL;
}
printk(KERN_DEBUG"[%s]:vcodec module clk disable\n",__FUNCTION__);
iowrite32(MEDIA2_PERDIS0_GT_CLK_VCODEBUS_UN, (void *)((unsigned long)ics_adapter->media2_io_addr + MEDIA2_OFFSET_PERDIS0));
iowrite32(PERI_PERDIS0_GT_CLK_VCODECBUS2DDRC_UN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERDIS0));
iowrite32(PERI_CLKDIV18_SC_GT_CLK_VCODEBUS_EN, (void *)((unsigned long)ics_adapter->peri_io_addr+ PERI_OFFSET_CLKDIV18));
//set_pu_media2_subsys
printk(KERN_DEBUG"[%s]:media module rst\n",__FUNCTION__);
iowrite32(PERI_PERRSTEN4_IP_RST_MEDIA2_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERRSTEN4));
printk(KERN_DEBUG"[%s]:media module clk disable\n",__FUNCTION__);
iowrite32(PERI_PERDIS6_GT_CLK_CFGBUS_MEDIA_AND_MEDIA2_EN, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERDIS6));
printk(KERN_DEBUG"[%s]:media module unrst\n",__FUNCTION__);
iowrite32(PERI_PERRSTEN4_IP_RST_MEDIA_CRG, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_PERRSTEN4));
return (ssize_t)size;
}
static ssize_t rdcorereg_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "rdcorereg:0x%x!\n", rdcorereg);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>rdcorereg\n");
return ret;
}
static ssize_t rdcorereg_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
unsigned int read_value;
read_value = ioread32((void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_VERSION));
if (read_value != 0x44400a7c && read_value != 0x4440031b) {
printk(KERN_ERR"[%s]: read_value error : 0x%x!\n", __FUNCTION__ , read_value);
return -EINVAL;
}
return (ssize_t)size;
}
static ssize_t wrcorereg_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret =0;
u32 value = 0;
ret = snprintf(buf, PAGE_SIZE, "wrcorereg:0x%x!\n", wrcorereg);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>wrcorereg\n");
value = ioread32((void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_BASE_ADDR));
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "register value: %u\n", value);
return ret;
}
static ssize_t wrcorereg_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
unsigned int read_value;
if (sscanf(buf, "0x%x", &wrcorereg) != 1)
return -EINVAL;
iowrite32(wrcorereg, (void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_BASE_ADDR));
udelay(1);
read_value = ioread32((void *)((unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_BASE_ADDR));
if (read_value != wrcorereg) {
printk(KERN_ERR"[%s]: read_value error : 0x%x!\n", __FUNCTION__ , read_value);
return -EINVAL;
} else {
printk(KERN_DEBUG "[%s]: write %lx success!\n", __FUNCTION__, (unsigned long)ics_adapter->config_reg_virt_addr + CONFIG_REG_VIRT_ADDR_OFFSET_ICS_BASE_ADDR);
}
return (ssize_t)size;
}
static ssize_t wrregvbusclk_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "wrregvbusclk:0x%x!\n", wrregvbusclk);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>wrregvbusclk\n");
return ret;
}
static ssize_t wrregvbusclk_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
if (sscanf(buf, "%d", &wrregvbusclk) != 1)
return -EINVAL;
if (wrregvbusclk != 480000000 && wrregvbusclk != 322000000 && wrregvbusclk != 207500000) {
return -EINVAL;
}
if (wrregvbusclk == 480000000) {
iowrite32(PERI_CLKDIV8_SEL_VCODECBUS_PLL2, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV5_SET_FREQ_DIV4_VCODECBUS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV5));
} else if(wrregvbusclk == 322000000){
iowrite32(PERI_CLKDIV8_SEL_VCODECBUS_PLL0, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV5_SET_FREQ_DIV5_VCODECBUS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV5));
} else if(wrregvbusclk == 207500000){
iowrite32(PERI_CLKDIV8_SEL_VCODECBUS_PLL0, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV5_SET_FREQ_DIV8_VCODECBUS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV5));
}
return (ssize_t)size;
}
static ssize_t wrregcnnclk_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "wrregcnnclk:0x%x!\n", wrregcnnclk);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>wrregcnnclk\n");
return ret;
}
static ssize_t wrregcnnclk_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
if (sscanf(buf, "%d", &wrregcnnclk) != 1)
return -EINVAL;
if (wrregcnnclk != 960000000 && wrregvbusclk != 640000000 && wrregvbusclk != 415000000) {
return -EINVAL;
}
if (wrregcnnclk == 960000000) {
iowrite32(PERI_CLKDIV8_SEL_ICS_PLL2, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV15_SEL_FREQ_DIV2_ICS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV15));
} else if (wrregcnnclk == 640000000) {
iowrite32(PERI_CLKDIV8_SEL_ICS_PLL2, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV15_SEL_FREQ_DIV3_ICS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV15));
} else if (wrregcnnclk == 415000000) {
iowrite32(PERI_CLKDIV8_SEL_ICS_PLL0, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV8));
iowrite32(PERI_CLKDIV15_SEL_FREQ_DIV4_ICS, (void *)((unsigned long)ics_adapter->peri_io_addr + PERI_OFFSET_CLKDIV15));
}
return (ssize_t)size;
}
static ssize_t wrreglmt_show(struct class *class, struct class_attribute *attr,
char *buf)
{
int ret = 0;
ret = snprintf(buf, PAGE_SIZE, "wrreglmt:0x%x!\n", wrreglmt);
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "usage: echo param>wrreglmt_es\n");
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "wrreglmt = 0xf6b ,ics core:400M,vcodec bus:207.5M\n");
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "wrreglmt = 0xaaa,ics core:640M,vcodec bus:480M\n");
ret += snprintf(buf+ret, (PAGE_SIZE-ret), "wrreglmt = 0xdd5 ,ics core:830M,vcodec bus:480M\n");
return ret;
}
static ssize_t wrreglmt_store(struct class *class, struct class_attribute *attr,
const char *buf, size_t size)
{
void __iomem *axi;
unsigned int read_value = 0;
if (sscanf(buf, "0x%x", &wrreglmt) != 1)
return -EINVAL;
if (wrreglmt != 0xf6b &&
wrreglmt != 0xaaa &&
wrreglmt != 0xdd5 ) {
printk(KERN_ERR"[%s]: limiter:input error value:%d!\n",
__FUNCTION__ , wrreglmt);
return -EINVAL;
}
axi = ioremap((unsigned long)0xe8950000,(unsigned long)0xfff);
iowrite32(0x1,(void *)((unsigned long)axi+0x0c));
udelay(10);
iowrite32(wrreglmt,(void *)((unsigned long)axi+0x10));
udelay(10);
iowrite32(0x40, (void *)((unsigned long)axi+0x14));
read_value = ioread32((void *)((unsigned long)axi+ 0x10));
printk(KERN_DEBUG"[%s]:limit value = 0x%x",__FUNCTION__, read_value);
iounmap(axi);
return (ssize_t)size;
}
static const struct class_attribute ics_attrs[] = {
__ATTR(setclkrate, 0644, setclkrate_show, setclkrate_store),
__ATTR(setprofile, 0644, setprofile_show, setprofile_store),
__ATTR(ipuopen, 0644, ipuopen_show, ipuopen_store),
__ATTR(ipurelease, 0644, ipurelease_show, ipurelease_store),
__ATTR(ipuversion, 0644, ipuversion_show, ipuversion_store),
__ATTR(resetproc, 0644, resetproc_show, resetproc_store),
__ATTR(ipurstcrtenv, 0644, ipurstcrtenv_show, ipurstcrtenv_store),
__ATTR(ipurstdstenv, 0644, ipurstdstenv_show, ipurstdstenv_store),
__ATTR(pusetreg, 0644, pusetreg_show, pusetreg_store),
__ATTR(pdsetreg, 0644, pdsetreg_show, pdsetreg_store),
__ATTR(rdcorereg, 0644, rdcorereg_show, rdcorereg_store),
__ATTR(wrcorereg, 0644, wrcorereg_show, wrcorereg_store),
__ATTR(wrregvbusclk, 0644, wrregvbusclk_show, wrregvbusclk_store),
__ATTR(wrregcnnclk, 0644, wrregcnnclk_show, wrregcnnclk_store),
__ATTR(wrreglmt, 0644, wrreglmt_show, wrreglmt_store),
};
static int create_ics_attrs(struct class *class)
{
unsigned int i = 0;
int ret = 0;
for (i = 0; i < (sizeof(ics_attrs)/sizeof(struct class_attribute)); i++) {
ret = class_create_file(class, &ics_attrs[i]);
if (ret < 0) {
break;
}
}
return ret;
}
static void remove_ics_attrs(struct class *class)
{
unsigned int i = 0;
for (i = 0; i < (sizeof(ics_attrs)/sizeof(struct class_attribute)); i++) {
class_remove_file(class, &ics_attrs[i]);
}
}
static int __init ics_debug_init(void) {
int ret = 0;
printk(KERN_ERR"[%s:%d], test begin\n", __FUNCTION__, __LINE__);
ics_class = class_create(THIS_MODULE, CLASS_NAME);
if (IS_ERR(ics_class)) {
printk(KERN_ERR"[%s:%d], class create error!\n", __FUNCTION__, __LINE__);
return -EFAULT;
}
ret = create_ics_attrs(ics_class);
if(ret < 0) {
class_destroy(ics_class);
printk(KERN_ERR"[%s:%d], create_ics_attrs error!\n", __FUNCTION__, __LINE__);
return -EFAULT;
}
ics_adapter = get_ipu_adapter();
return 0;
}
static void __exit ics_debug_exit(void) {
printk(KERN_ERR"[%s:%d], test end\n", __FUNCTION__, __LINE__);
remove_ics_attrs(ics_class);
class_destroy(ics_class);
return;
}
module_init(ics_debug_init);
module_exit(ics_debug_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Hisilicon");
drivers/hisi/ics/ics_debug.h
-6
View File
@@ -1,6 +0,0 @@
#ifndef __ICS_DEBUG_H__
#define __ICS_DEBUG_H__
#include "ics_debug_proxy.h"
#endif
drivers/hisi/ics/ics_debug_proxy.c
-77
View File
@@ -1,77 +0,0 @@
#include "ipu_clock.h"
#include "ipu_smmu_drv.h"
#include "ics_debug_proxy.h"
struct ioctl_out_params {
bool ret_directly;
void *memory_node;
//TODO: add more out params here
};
extern struct cambricon_ipu_private *adapter;
extern int regulator_ip_vipu_enable(void);
extern int regulator_ip_vipu_disable(void);
extern void ipu_reset_proc(unsigned int addr);
extern void ipu_interrupt_init(void);
extern long ipu_set_profile(struct cambricon_ipu_private *, unsigned long, struct ioctl_out_params *);
int call_regulator_ip_vipu_enable(void)
{
return regulator_ip_vipu_enable();
}
EXPORT_SYMBOL(call_regulator_ip_vipu_enable);
int call_regulator_ip_vipu_disable(void)
{
return regulator_ip_vipu_disable();
}
EXPORT_SYMBOL(call_regulator_ip_vipu_disable);
void call_ipu_reset_proc(unsigned int addr)
{
ipu_reset_proc(addr);
}
EXPORT_SYMBOL(call_ipu_reset_proc);
void call_ipu_interrupt_init(void)
{
ipu_interrupt_init();
}
EXPORT_SYMBOL(call_ipu_interrupt_init);
void * get_ipu_adapter(void)
{
return adapter;
}
EXPORT_SYMBOL(get_ipu_adapter);
int call_ipu_clock_start(void *clock)
{
return ipu_clock_start(clock);
}
EXPORT_SYMBOL(call_ipu_clock_start);
int call_ipu_clock_set_rate(void *clock, unsigned int clock_rate)
{
return ipu_clock_set_rate(clock, clock_rate);
}
EXPORT_SYMBOL(call_ipu_clock_set_rate);
void call_ipu_clock_stop(void *clock)
{
ipu_clock_stop(clock);
}
EXPORT_SYMBOL(call_ipu_clock_stop);
void call_ipu_smmu_init(unsigned long ttbr0, unsigned long smmu_rw_err_phy_addr, bool port_sel, bool hardware_start)
{
ipu_smmu_init(ttbr0, smmu_rw_err_phy_addr, port_sel, hardware_start);
}
EXPORT_SYMBOL(call_ipu_smmu_init);
void call_ipu_set_profile(unsigned long profile)
{
ipu_set_profile(0, profile, 0);
}
EXPORT_SYMBOL(call_ipu_set_profile);
drivers/hisi/ics/ics_debug_proxy.h
-17
View File
@@ -1,17 +0,0 @@
#ifndef __ICS_DEBUG_PROXY_H__
#define __ICS_DEBUG_PROXY_H__
#include "cambricon_ipu.h"
int call_regulator_ip_vipu_enable(void);
int call_regulator_ip_vipu_disable(void);
void call_ipu_reset_proc(unsigned int addr);
void call_ipu_interrupt_init(void);
void * get_ipu_adapter(void);
int call_ipu_clock_start(void *clk);
int call_ipu_clock_set_rate(void *clock, unsigned int clock_rate);
void call_ipu_clock_stop(void *clock);
void call_ipu_smmu_init(unsigned long ttbr0, unsigned long smmu_rw_err_phy_addr, bool port_sel, bool hardware_start);
void call_ipu_set_profile(unsigned long profile);
#endif
drivers/hisi/ics/ipu_clock.c
-3
View File
@@ -1,7 +1,6 @@
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include "ipu_clock.h" #include "ipu_clock.h"
// #include "ipu_mntn.h"
#include "cambricon_ipu.h" #include "cambricon_ipu.h"
// #define CONFIG_IPU_CLOCK_CONTROL // #define CONFIG_IPU_CLOCK_CONTROL
@@ -96,7 +95,6 @@ static int ipu_clock_set(struct ics_clock *clk, unsigned int new_rate)
ret = clk_set_rate(clk->ipu_clk_ptr, (unsigned long)target_rate); ret = clk_set_rate(clk->ipu_clk_ptr, (unsigned long)target_rate);
if (ret) { if (ret) {
printk(KERN_ERR"[%s]: IPU_ERROR:set ipu rate %d fail, ret:%d\n", __func__, target_rate, ret); printk(KERN_ERR"[%s]: IPU_ERROR:set ipu rate %d fail, ret:%d\n", __func__, target_rate, ret);
rdr_system_error((unsigned int)MODID_NPU_EXC_SET_BACK_CLOCK_FAIL, 0, 0);
return ret; return ret;
} }
} else { } else {
@@ -131,7 +129,6 @@ static int ipu_clock_set(struct ics_clock *clk, unsigned int new_rate)
if (ret) { if (ret) {
/* in low temperature, clk set rate to HIGH will fail, in this case try to set rate to MIDDLE */ /* in low temperature, clk set rate to HIGH will fail, in this case try to set rate to MIDDLE */
printk(KERN_ERR"[%s]: IPU_ERROR:set ipu rate %d fail, ret:%d\n", __func__, target_rate, ret); printk(KERN_ERR"[%s]: IPU_ERROR:set ipu rate %d fail, ret:%d\n", __func__, target_rate, ret);
rdr_system_error((unsigned int)MODID_NPU_EXC_SET_CLOCK_FAIL, 0, 0);
return ret; return ret;
} }
} }
drivers/hisi/ics/ipu_mntn.c
-433
View File
@@ -1,433 +0,0 @@
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/ioctl.h>
#include <linux/io.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/workqueue.h>
#include <linux/errno.h>
#include <asm/uaccess.h>
#include <asm/compiler.h>
#include <mntn_subtype_exception.h>
#include <mntn_public_interface.h>
#include "ipu_mntn.h"
#include "ipu_smmu_drv.h"
#include "cambricon_ipu.h"
struct rdr_exception_info_s ipu_excetption_info[] = {
{
.e_modid = (u32)MODID_NPU_EXC_DEAD,
.e_modid_end = (u32)MODID_NPU_EXC_DEAD,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_EXC_DEAD,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_EXC_DEAD",
},
{
.e_modid = (u32)MODID_NPU_EXC_SET_BACK_CLOCK_FAIL,
.e_modid_end = (u32)MODID_NPU_EXC_SET_BACK_CLOCK_FAIL,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_SET_BACK_CLOCK_FAIL,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_SET_BACK_CLOCK_FAIL",
},
{
.e_modid = (u32)MODID_NPU_EXC_SET_CLOCK_FAIL,
.e_modid_end = (u32)MODID_NPU_EXC_SET_CLOCK_FAIL,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_SET_CLOCK_FAIL,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_SET_CLOCK_FAIL",
},
{
.e_modid = (u32)MODID_NPU_EXC_SET_POWER_UP_FAIL,
.e_modid_end = (u32)MODID_NPU_EXC_SET_POWER_UP_FAIL,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_POWER_UP_FAIL,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_POWER_UP_FAIL",
},
{
.e_modid = (u32)MODID_NPU_EXC_SET_POWER_UP_STATUS_FAULT,
.e_modid_end = (u32)MODID_NPU_EXC_SET_POWER_UP_STATUS_FAULT,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_POWER_UP_STA_FAULT,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_POWER_UP_STA_FAULT",
},
{
.e_modid = (u32)MODID_NPU_EXC_SET_POWER_DOWN_FAIL,
.e_modid_end = (u32)MODID_NPU_EXC_SET_POWER_DOWN_FAIL,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_POWER_DOWN_FAIL,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_POWER_DOWN_FAIL",
},
{
.e_modid = (u32)MODID_NPU_EXC_INTERRUPT_ABNORMAL,
.e_modid_end = (u32)MODID_NPU_EXC_INTERRUPT_ABNORMAL,
.e_process_priority = RDR_ERR,
.e_reboot_priority = RDR_REBOOT_NO,
.e_notify_core_mask = RDR_NPU,
.e_reset_core_mask = RDR_NPU,
.e_from_core = RDR_NPU,
.e_reentrant = (u32)RDR_REENTRANT_DISALLOW,
.e_exce_type = NPU_S_EXCEPTION,
.e_exce_subtype = NPU_INTERRUPT_ABNORMAL,
.e_upload_flag = (u32)RDR_UPLOAD_YES,
.e_from_module = "NPU",
.e_desc = "NPU_INTERRUPT_ABNORMAL",
}
};
struct work_struct ipu_dump_work;
struct workqueue_struct *ipu_mntn_rdr_wq;
struct ipu_mntn_info_s ipu_mntn_info;
struct ipu_reg_info_s ipu_reg_info;
extern struct cambricon_ipu_private *adapter;
/********************************************************************
Description: ipu_mntn_copy_reg_to_bbox
input: char *src_addr, unsigned int* offset, unsigned int len
output: NA
return: void
********************************************************************/
static int ipu_mntn_copy_reg_to_bbox(char *src_addr, unsigned int len)
{
unsigned int temp_offset = 0;
if ((NULL == src_addr) || (0 == len)) {
printk(KERN_ERR"[%s]:IPU_ERROR:Input parameter is error!\n", __func__);
return -EINVAL;
}
temp_offset = ipu_mntn_info.bbox_addr_offset + len;
//ipu_bbox alloc size 64k
if (temp_offset > 0x10000) {
printk(KERN_ERR"[%s]:IPU_ERROR:Copy log to bbox size is error! temp_offset=%d\n", __func__, temp_offset);
temp_offset = 0;
ipu_mntn_info.bbox_addr_offset = 0;
return -ENOMEM ;
}
memcpy(((char*)ipu_mntn_info.rdr_addr + ipu_mntn_info.bbox_addr_offset), src_addr, len);
ipu_mntn_info.bbox_addr_offset = temp_offset;
return 0;
}
/********************************************************************
Description: ipu_mntn_write_adapter_info
input: char *file_path
output: NA
return: void
********************************************************************/
static void ipu_mntn_write_adapter_info(void)
{
char log_buf[IPU_LINE_MAX + 1] = {0};
snprintf(log_buf, IPU_LINE_MAX, "npu_status=%d, ttbr0=%lx, inst_set=%d, offchip{set=%x, base=%x}, last_computed_task=%ld.\r\n",
adapter->ipu_power_up,
adapter->smmu_ttbr0,
adapter->boot_inst_set.boot_inst_recorded_is_config,
adapter->boot_inst_set.access_ddr_addr_is_config,
adapter->boot_inst_set.ipu_access_ddr_addr,
adapter->computed_task_cnt);
ipu_mntn_copy_reg_to_bbox(log_buf, strlen(log_buf));
return;
}
/********************************************************************
Description: ipu_mntn_write_peri_reg_info
input: char *file_path
output: NA
return: void
********************************************************************/
static void ipu_mntn_write_peri_reg_info(void)
{
char log_buf[IPU_LINE_MAX + 1] = {0};
snprintf(log_buf, IPU_LINE_MAX, "peri_stat=%x, ppll_select=%x, power_stat=%x, power_ack=%x, reset_stat=%x, perclken=%x, perstat=%x.\r\n",
ipu_reg_info.peri_reg.peri_stat,
ipu_reg_info.peri_reg.ppll_select,
ipu_reg_info.peri_reg.power_stat,
ipu_reg_info.peri_reg.power_ack,
ipu_reg_info.peri_reg.reset_stat,
ipu_reg_info.peri_reg.perclken0,
ipu_reg_info.peri_reg.perstat0);
ipu_mntn_copy_reg_to_bbox(log_buf, strlen(log_buf));
return;
}
/********************************************************************
Description: ipu_mntn_write_mstr_reg_info
input: char *file_path
output: NA
return: void
********************************************************************/
static void ipu_mntn_write_mstr_reg_info(void)
{
char log_buf[IPU_BUF_LEN_MAX + 1] = {0};
snprintf(log_buf, IPU_BUF_LEN_MAX, "RD_BITMAP=%x, WR_BITMAP=%x, rd_cmd_total_cnt[0-3]={%x, %x, %x}, wr_cmd_total_cnt=%x\n",
ipu_reg_info.mstr_reg.rd_bitmap,
ipu_reg_info.mstr_reg.wr_bitmap,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt0,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt0,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt2,
ipu_reg_info.mstr_reg.wr_cmd_total_cnt);
ipu_mntn_copy_reg_to_bbox(log_buf, strlen(log_buf));
return;
}
/********************************************************************
Description: ipu_mntn_write_reg_log
input: void
output: NA
return: void
********************************************************************/
static void ipu_mntn_write_reg_log(void)
{
switch (ipu_mntn_info.dump_info.modid) {
case MODID_NPU_EXC_DEAD: //lint !e650
ipu_mntn_write_adapter_info();
ipu_mntn_write_peri_reg_info();
ipu_mntn_write_mstr_reg_info();
#ifdef CONFIG_HUAWEI_DSM
ipu_mntn_copy_reg_to_bbox(register_info, strlen(register_info));
#endif
break;
case MODID_NPU_EXC_SET_BACK_CLOCK_FAIL: //lint !e650
case MODID_NPU_EXC_SET_CLOCK_FAIL: //lint !e650
case MODID_NPU_EXC_SET_POWER_UP_FAIL: //lint !e650
case MODID_NPU_EXC_SET_POWER_UP_STATUS_FAULT: //lint !e650
case MODID_NPU_EXC_SET_POWER_DOWN_FAIL: //lint !e650
case MODID_NPU_EXC_INTERRUPT_ABNORMAL: //lint !e650
break;
default:
break;
}
return;
}
/********************************************************************
Description: ipu_mntn_rdr_dump
input: modid: module id
etype:exception type
coreid: core id
pathname: log path
pfn_cb: callback function
output: NA
return: NA
********************************************************************/
static void ipu_mntn_rdr_dump(u32 modid, u32 etype, u64 coreid, char *pathname, pfn_cb_dump_done pfn_cb)
{
if (NULL == pathname) {
printk(KERN_ERR"[%s]:IPU_ERROR:pathname is empty\n", __func__);
return;
}
ipu_mntn_info.dump_info.modid = modid;
ipu_mntn_info.dump_info.coreid = coreid;
ipu_mntn_info.dump_info.pathname = pathname;
ipu_mntn_info.dump_info.cb = pfn_cb;
ipu_mntn_info.bbox_addr_offset = 0;
queue_work(ipu_mntn_rdr_wq, &ipu_dump_work);
return;
}
/********************************************************************
Description: ipu_mntn_rdr_reset
input: modid:module id
etype:exception type
coreid:core id
output: NA
return: NA
********************************************************************/
static void ipu_mntn_rdr_reset(u32 modid, u32 etype, u64 coreid)
{
return;
}
/********************************************************************
Description: ipu_mntn_dump_work
input: struct work_struct *work
output: NA
return: NA
********************************************************************/
static void ipu_mntn_dump_work(struct work_struct *work)
{
ipu_mntn_write_reg_log();
if (ipu_mntn_info.dump_info.cb) {
ipu_mntn_info.dump_info.cb(ipu_mntn_info.dump_info.modid, ipu_mntn_info.dump_info.coreid);
}
return;
}
/********************************************************************
Description: ipu_mntn_register_exception
input: NA
output: NA
return: int
********************************************************************/
static int ipu_mntn_register_exception(void)
{
int ret;
unsigned int size;
unsigned long index;
size = sizeof(ipu_excetption_info)/sizeof(struct rdr_exception_info_s);
for (index = 0; index < size; index++) {
/* error return 0, ok return modid */
ret = rdr_register_exception(&ipu_excetption_info[index]);
if (!ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:rdr_register_exception is failed! index=%ld ret=%d\n", __func__, index, ret);
return -EINTR;
}
}
return 0;
}
/********************************************************************
Description: register ipu dump and reset function
input: NA
output: NA
return: int
********************************************************************/
static int ipu_mntn_register_core(void)
{
int ret;
struct rdr_module_ops_pub s_soc_ops;
s_soc_ops.ops_dump = ipu_mntn_rdr_dump;
s_soc_ops.ops_reset = ipu_mntn_rdr_reset;
/* register ipu core dump and reset function */
ret = rdr_register_module_ops((u64)RDR_NPU, &s_soc_ops, &ipu_mntn_info.ipu_ret_info);
if (ret != 0) {
printk(KERN_ERR"[%s]:IPU_ERROR:rdr_register_module_ops is failed! ret=0x%08x\n", __func__, ret);
}
return ret;
}
/********************************************************************
Description: init ipu addr function
input: NA
output: NA
return: int
********************************************************************/
static int ipu_mntn_addr_map(void)
{
ipu_mntn_info.rdr_addr = hisi_bbox_map((phys_addr_t)ipu_mntn_info.ipu_ret_info.log_addr, ipu_mntn_info.ipu_ret_info.log_len);
if (!ipu_mntn_info.rdr_addr) {
printk(KERN_ERR"[%s]:IPU_ERROR:hisi_bbox_map is failed!\n", __func__);
return -EFAULT;
}
return 0;
}
/********************************************************************
Description: ipu_mntn_rdr_resource_init
input: NA
output: NA
return: int
********************************************************************/
static int ipu_mntn_rdr_resource_init(void)
{
ipu_mntn_rdr_wq = create_singlethread_workqueue("ipu_mntn_rdr_wq");
if (!ipu_mntn_rdr_wq) {
printk(KERN_ERR"[%s]:IPU_ERROR:Create_singlethread_workqueue is failed!\n", __func__);
return -EINTR;
}
INIT_WORK(&ipu_dump_work, ipu_mntn_dump_work);
return 0;
}
/********************************************************************
Description: ipu_mntn_rdr_init
input: void
output: NA
return: int
********************************************************************/
int ipu_mntn_rdr_init(void)
{
int ret;
ret = ipu_mntn_rdr_resource_init();
if (0 != ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:ipu_mntn_rdr_resource_init is faild!ret=%d\n", __func__, ret);
return ret;
}
/* register ics exception */
ret = ipu_mntn_register_exception();
if (0 != ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:ipu_mntn_register_exception is faild!ret=%d\n", __func__, ret);
return ret;
}
/* register ics dump and reset function */
ret = ipu_mntn_register_core();
if (0 != ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:ipu_register_core is failed!ret=%d\n", __func__, ret);
return ret;
}
ret = ipu_mntn_addr_map();
if (0 != ret) {
printk(KERN_ERR"[%s]:IPU_ERROR:ipu_mntn_addr_map is failed!ret=%d\n", __func__, ret);
return ret;
}
return 0;
}
drivers/hisi/ics/ipu_mntn.h
-69
View File
@@ -1,69 +0,0 @@
#ifndef _IPU_MNTN_H_
#define _IPU_MNTN_H_
#include <linux/netlink.h>
#include <linux/sched.h>
#include <net/sock.h>
#include <linux/hisi/rdr_pub.h>
/* AI DRD */
#define IPU_BUF_LEN_MAX (256)
#define IPU_LINE_MAX (128)
enum rdr_ipu_system_error_type {
MODID_NPU_START = HISI_BB_MOD_NPU_START,
MODID_NPU_EXC_DEAD = MODID_NPU_START,
MODID_NPU_EXC_SET_BACK_CLOCK_FAIL,
MODID_NPU_EXC_SET_CLOCK_FAIL,
MODID_NPU_EXC_SET_POWER_UP_FAIL,
MODID_NPU_EXC_SET_POWER_UP_STATUS_FAULT,
MODID_NPU_EXC_SET_POWER_DOWN_FAIL,
MODID_NPU_EXC_INTERRUPT_ABNORMAL,
MODID_NPU_EXC_END = HISI_BB_MOD_NPU_END
};
struct rdr_dump_info_s {
u32 modid;
u64 coreid;
pfn_cb_dump_done cb;
char *pathname;
};
struct ipu_peri_reg_s {
unsigned int peri_stat;
unsigned int ppll_select;
unsigned int power_stat;
unsigned int power_ack;
unsigned int reset_stat;
unsigned int perclken0;
unsigned int perstat0;
};
struct ipu_mstr_reg_s {
unsigned int rd_bitmap;
unsigned int wr_bitmap;
unsigned int rd_cmd_total_cnt0;
unsigned int rd_cmd_total_cnt1;
unsigned int rd_cmd_total_cnt2;
unsigned int wr_cmd_total_cnt;
};
struct ipu_mntn_info_s {
unsigned int ipu_run_status;
unsigned int bbox_addr_offset;
struct rdr_register_module_result ipu_ret_info;
struct rdr_dump_info_s dump_info;
void *rdr_addr;
};
struct ipu_reg_info_s {
struct ipu_peri_reg_s peri_reg;
struct ipu_mstr_reg_s mstr_reg;
};
extern struct workqueue_struct *ipu_mntn_rdr_wq;
extern struct ipu_reg_info_s ipu_reg_info;
extern int ipu_mntn_rdr_init(void);
#endif
drivers/hisi/ics/ipu_smmu_drv.c
+8 -15
View File
@@ -5,7 +5,6 @@
#include <linux/list.h> #include <linux/list.h>
#include <linux/dma-buf.h> #include <linux/dma-buf.h>
#include "ipu_smmu_drv.h" #include "ipu_smmu_drv.h"
// #include "ipu_mntn.h"
#define SMMU_MSTR_DEBUG_CONFIG_WR (16) #define SMMU_MSTR_DEBUG_CONFIG_WR (16)
#define SMMU_MSTR_DEBUG_CONFIG_CS (17) #define SMMU_MSTR_DEBUG_CONFIG_CS (17)
@@ -988,6 +987,7 @@ void ipu_smmu_dump_strm(void)
unsigned int port_in[IPU_SMMU_MSTR_DEBUG_BASE_NUM] = { unsigned int port_in[IPU_SMMU_MSTR_DEBUG_BASE_NUM] = {
IPU_SMMU_MSTR_DEBUG_AXI_RD_CMD_ADDR, IPU_SMMU_MSTR_DEBUG_AXI_RD_CMD_INFO, IPU_SMMU_MSTR_DEBUG_AXI_RD_CMD_ADDR, IPU_SMMU_MSTR_DEBUG_AXI_RD_CMD_INFO,
IPU_SMMU_MSTR_DEBUG_AXI_WR_CMD_ADDR, IPU_SMMU_MSTR_DEBUG_AXI_WR_CMD_INFO}; IPU_SMMU_MSTR_DEBUG_AXI_WR_CMD_ADDR, IPU_SMMU_MSTR_DEBUG_AXI_WR_CMD_INFO};
unsigned int rd_bitmap, wr_bitmap, rd_cmd_total_cnt0, rd_cmd_total_cnt1, rd_cmd_total_cnt2, wr_cmd_total_cnt;
#ifdef CONFIG_HUAWEI_DSM #ifdef CONFIG_HUAWEI_DSM
int sz = REGISTER_INFO_MAX_LEN; int sz = REGISTER_INFO_MAX_LEN;
@@ -1033,20 +1033,13 @@ void ipu_smmu_dump_strm(void)
iowrite32(IPU_SMMU_RD_CMD_BUF_BITMAP, (void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_in_0)); iowrite32(IPU_SMMU_RD_CMD_BUF_BITMAP, (void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_in_0));
iowrite32(IPU_SMMU_WR_CMD_BUF_BITMAP, (void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_in_0)); iowrite32(IPU_SMMU_WR_CMD_BUF_BITMAP, (void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_in_0));
#ifdef CONFIG_HISI_IPU_MNTN rd_bitmap = ioread32((void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_out));
ipu_reg_info.mstr_reg.rd_bitmap = ioread32((void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_out)); wr_bitmap = ioread32((void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_out));
ipu_reg_info.mstr_reg.wr_bitmap = ioread32((void *)(mstr_io_addr + (unsigned long)offset->smmu_mstr_dbg_port_out)); rd_cmd_total_cnt0 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[0]));
ipu_reg_info.mstr_reg.rd_cmd_total_cnt0 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[0])); rd_cmd_total_cnt1 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[1]));
ipu_reg_info.mstr_reg.rd_cmd_total_cnt1 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[1])); rd_cmd_total_cnt2 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[2]));
ipu_reg_info.mstr_reg.rd_cmd_total_cnt2 = ioread32((void *)(mstr_io_addr + (unsigned long)offset->read_cmd_total_cnt[2])); wr_cmd_total_cnt = ioread32((void *)(mstr_io_addr + (unsigned long)offset->write_cmd_total_cnt));
ipu_reg_info.mstr_reg.wr_cmd_total_cnt = ioread32((void *)(mstr_io_addr + (unsigned long)offset->write_cmd_total_cnt));
printk(KERN_ERR"RD_BITMAP=%x, WR_BITMAP=%x, rd_cmd_total_cnt[0-3]={%x, %x, %x}, wr_cmd_total_cnt=%x\n", printk(KERN_ERR"RD_BITMAP=%x, WR_BITMAP=%x, rd_cmd_total_cnt[0-3]={%x, %x, %x}, wr_cmd_total_cnt=%x\n",
ipu_reg_info.mstr_reg.rd_bitmap, rd_bitmap, wr_bitmap, rd_cmd_total_cnt0, rd_cmd_total_cnt1, rd_cmd_total_cnt2, wr_cmd_total_cnt);
ipu_reg_info.mstr_reg.wr_bitmap,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt0,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt1,
ipu_reg_info.mstr_reg.rd_cmd_total_cnt2,
ipu_reg_info.mstr_reg.wr_cmd_total_cnt);
#endif
} }