From 4bc8280d093409119914fe09c06366b099a87bcb Mon Sep 17 00:00:00 2001 From: Zhong Kaihua Date: Wed, 2 Aug 2017 10:32:27 -0700 Subject: [PATCH] HACK: clk-hi3660: Fix clk_factor_uart3 to be 100000000, not 200000000 TODO: The division ratio of clk_gate_iomcu_peri0 should be 16, which means correct value of iomcu_peri0_div(bit [12:13] of 0xffd7e004) should be 0x1. However, there is a extremely low probability that these two bits are stepped to 0x0 during work time, making uart3 clock rate double. The reappearance scene and root cause is not clear yet. Change-Id: I62b74cf36fa09870b1c750cda62d6a52fce7dcc7 Signed-off-by: Dmitry Shmidt --- drivers/clk/hisilicon/clk-hi3660.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 267869b0a601..039f57cbc34d 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { /* crgctrl */ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { - { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, + { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, }, { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },