usb: dwc3: add support for USB functionality of Hikey960
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Hisilicon hi3660 usb PHY
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-----------------------
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Required properties:
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- compatible: should be "hisilicon,hi3660-usb-phy"
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- #phy-cells: must be 0
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- hisilicon,pericrg-syscon: phandle of syscon used to control phy.
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- hisilicon,pctrl-syscon: phandle of syscon used to control phy.
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- hisilicon,usb3-otg-bc-syscon: phandle of syscon used to control phy.
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- eye-diagram-param: parameter set for phy
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Refer to phy/phy-bindings.txt for the generic PHY binding properties
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Example:
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usb_phy: usbphy {
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compatible = "hisilicon,hi3660-usb-phy";
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#phy-cells = <0>;
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hisilicon,pericrg-syscon = <&crg_ctrl>;
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hisilicon,pctrl-syscon = <&pctrl>;
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hisilicon,usb3-otg-bc-syscon = <&usb3_otg_bc>;
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eye-diagram-param = <0x22466e4>;
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};
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+91
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HiSilicon DWC3 USB SoC controller
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This file documents the parameters for the dwc3-hisi driver.
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Required properties:
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- compatible: should be "hisilicon,hi3660-dwc3" or "hisilicon,kirin970-dwc3"
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Specify clock names
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- resets: list of phandle and reset specifier pairs.
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Sub-nodes:
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The dwc3 core should be added as subnode to HiSilicon DWC3 as shown in the
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example below. The DT binding details of dwc3 can be found in:
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Documentation/devicetree/bindings/usb/dwc3.txt
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Example:
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usb3: hisi_dwc3 {
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compatible = "hisilicon,hi3660-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
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<&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
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clock-names = "clk_usb3phy_ref", "aclk_usb3otg";
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assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
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assigned-clock-rates = <229000000>;
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resets = <&crg_rst 0x90 8>,
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<&crg_rst 0x90 7>,
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<&crg_rst 0x90 6>,
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<&crg_rst 0x90 5>;
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dwc3: dwc3@ff100000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xff100000 0x0 0x100000>;
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interrupts = <0 159 4>, <0 161 4>;
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phys = <&usb_phy>;
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phy-names = "usb3-phy";
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dr_mode = "otg";
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maximum-speed = "super-speed";
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phy_type = "utmi";
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snps,dis-del-phy-power-chg-quirk;
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snps,lfps_filter_quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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snps,tx_de_emphasis_quirk;
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snps,tx_de_emphasis = <1>;
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snps,dis_enblslpm_quirk;
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extcon = <&hisi_pd>;
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};
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};
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usb3: hisi_dwc3 {
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compatible = "hisilicon,kirin970-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&crg_ctrl KIRIN970_CLK_GATE_ABB_USB>,
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<&crg_ctrl KIRIN970_HCLK_GATE_USB3OTG>,
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<&crg_ctrl KIRIN970_CLK_GATE_USB3OTG_REF>,
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<&crg_ctrl KIRIN970_ACLK_GATE_USB3DVFS>;
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clock-names = "clk_gate_abb_usb",
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"hclk_gate_usb3otg",
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"clk_gate_usb3otg_ref",
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"aclk_gate_usb3dvfs";
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assigned-clocks = <&crg_ctrl KIRIN970_ACLK_GATE_USB3DVFS>;
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assigned-clock-rates = <238000000>;
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resets = <&crg_rst 0x90 6>,
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<&crg_rst 0x90 7>,
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<&usb31_misc_rst 0xA0 8>,
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<&usb31_misc_rst 0xA0 9>;
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dwc3: dwc3@ff100000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xff100000 0x0 0x100000>;
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interrupts = <0 159 4>, <0 161 4>;
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phys = <&usb_phy>;
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phy-names = "usb3-phy";
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dr_mode = "otg";
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maximum-speed = "super-speed";
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phy_type = "utmi";
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snps,dis-del-phy-power-chg-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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snps,tx_de_emphasis_quirk;
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snps,tx_de_emphasis = <1>;
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extcon = <&hisi_pd>;
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};
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};
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@@ -0,0 +1,21 @@
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Hisilicon support hub controller
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-----------------------------
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Required properties:
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- compatible: "hisilicon,gpio_hubv1","hisilicon,gpio_hubv2"
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Example
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-----
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hubv2: gpio_hubv2 {
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compatible = "hisilicon,gpio_hubv2";
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typc_vbus_int_gpio,typec-gpios = <&gpio25 2 0>;
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typc_vbus_enable_val = <1>;
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otg_gpio = <&gpio25 6 0>;
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hub_vdd12_en_gpio = <&gpio2 1 0>;
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hub_vdd33_en_gpio = <&gpio5 6 0>;
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hub_reset_en_gpio = <&gpio4 4 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&usbhub5734_pmx_func>;
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};
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