From 8094511eeec4dd0dad6ff59bd97e9e539aa05cc1 Mon Sep 17 00:00:00 2001 From: xwx495457 Date: Mon, 12 Feb 2018 18:27:29 +0800 Subject: [PATCH] Drivers/VCODEC: support vcodec function for hikey970. Add VCODEC code in kernel to support vcodec for hikey970. Signed-off-by: xwx495457 --- .../boot/dts/hisilicon/kirin970-hikey970.dts | 0 drivers/Kconfig | 3 + drivers/Makefile | 2 + drivers/vcodec/vdec_hivna/Kconfig | 9 + drivers/vcodec/vdec_hivna/Makefile | 1 + drivers/vcodec/vdec_hivna/omxvdec/Kconfig | 5 + drivers/vcodec/vdec_hivna/omxvdec/Makefile | 22 + drivers/vcodec/vdec_hivna/omxvdec/omxvdec.c | 569 + drivers/vcodec/vdec_hivna/omxvdec/omxvdec.h | 122 + drivers/vcodec/vdec_hivna/omxvdec/regulator.c | 395 + drivers/vcodec/vdec_hivna/omxvdec/regulator.h | 27 + drivers/vcodec/vdec_hivna/vfmw_v4.0/Kconfig | 5 + drivers/vcodec/vdec_hivna/vfmw_v4.0/Makefile | 12 + .../vdec_hivna/vfmw_v4.0/format/vdm_drv.h | 166 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal.c | 553 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal.h | 85 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal_api.h | 31 + .../vfmw_v4.0/format/vdm_hal_h264.c | 107 + .../vfmw_v4.0/format/vdm_hal_h264.h | 8 + .../vfmw_v4.0/format/vdm_hal_hevc.c | 119 + .../vfmw_v4.0/format/vdm_hal_hevc.h | 9 + .../vfmw_v4.0/format/vdm_hal_local.h | 283 + .../vfmw_v4.0/format/vdm_hal_mpeg2.c | 105 + .../vfmw_v4.0/format/vdm_hal_mpeg2.h | 8 + .../vfmw_v4.0/format/vdm_hal_mpeg4.c | 110 + .../vfmw_v4.0/format/vdm_hal_mpeg4.h | 9 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.c | 100 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.h | 9 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.c | 140 + .../vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.h | 9 + .../vdec_hivna/vfmw_v4.0/linux_kernel_osal.c | 408 + .../vdec_hivna/vfmw_v4.0/linux_kernel_osal.h | 84 + .../vcodec/vdec_hivna/vfmw_v4.0/mem_manage.c | 180 + .../vcodec/vdec_hivna/vfmw_v4.0/mem_manage.h | 34 + drivers/vcodec/vdec_hivna/vfmw_v4.0/public.h | 55 + drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.c | 261 + drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.h | 166 + drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.c | 479 + drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.h | 64 + .../vcodec/vdec_hivna/vfmw_v4.0/sysconfig.h | 54 + drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw.h | 66 + .../vdec_hivna/vfmw_v4.0/vfmw_config.cfg | 73 + .../vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.c | 82 + .../vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.h | 8 + .../vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.c | 376 + .../vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.h | 33 + .../vcodec/vdec_hivna/vfmw_v4.0/vfmw_make.cfg | 147 + .../vdec_hivna/vfmw_v4.0/vfmw_osal_ext.h | 121 + drivers/vcodec/venc_hivna/Kconfig | 8 + drivers/vcodec/venc_hivna/Makefile | 16 + .../vcodec/venc_hivna/Vedu_RegAll_Kirin970.h | 12728 ++++++++++++++++ drivers/vcodec/venc_hivna/drv_venc.c | 48 + drivers/vcodec/venc_hivna/drv_venc.h | 85 + drivers/vcodec/venc_hivna/drv_venc_config.cfg | 65 + drivers/vcodec/venc_hivna/drv_venc_efl.c | 196 + drivers/vcodec/venc_hivna/drv_venc_efl.h | 47 + drivers/vcodec/venc_hivna/drv_venc_intf.c | 534 + drivers/vcodec/venc_hivna/drv_venc_make.cfg | 82 + drivers/vcodec/venc_hivna/drv_venc_osal.c | 258 + drivers/vcodec/venc_hivna/drv_venc_osal.h | 59 + drivers/vcodec/venc_hivna/hal_venc.c | 3296 ++++ drivers/vcodec/venc_hivna/hi_drv_mem.c | 239 + drivers/vcodec/venc_hivna/hi_drv_mem.h | 72 + drivers/vcodec/venc_hivna/venc_regulator.c | 275 + drivers/vcodec/venc_hivna/venc_regulator.h | 12 + 65 files changed, 23734 insertions(+) mode change 100755 => 100644 arch/arm64/boot/dts/hisilicon/kirin970-hikey970.dts create mode 100755 drivers/vcodec/vdec_hivna/Kconfig create mode 100755 drivers/vcodec/vdec_hivna/Makefile create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/Kconfig create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/Makefile create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/omxvdec.c create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/omxvdec.h create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/regulator.c create mode 100755 drivers/vcodec/vdec_hivna/omxvdec/regulator.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/Kconfig create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/Makefile create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_drv.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_api.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_local.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/public.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/sysconfig.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_config.cfg create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.c create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.h create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_make.cfg create mode 100755 drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_osal_ext.h create mode 100755 drivers/vcodec/venc_hivna/Kconfig create mode 100755 drivers/vcodec/venc_hivna/Makefile create mode 100755 drivers/vcodec/venc_hivna/Vedu_RegAll_Kirin970.h create mode 100755 drivers/vcodec/venc_hivna/drv_venc.c create mode 100755 drivers/vcodec/venc_hivna/drv_venc.h create mode 100755 drivers/vcodec/venc_hivna/drv_venc_config.cfg create mode 100755 drivers/vcodec/venc_hivna/drv_venc_efl.c create mode 100755 drivers/vcodec/venc_hivna/drv_venc_efl.h create mode 100755 drivers/vcodec/venc_hivna/drv_venc_intf.c create mode 100755 drivers/vcodec/venc_hivna/drv_venc_make.cfg create mode 100755 drivers/vcodec/venc_hivna/drv_venc_osal.c create mode 100755 drivers/vcodec/venc_hivna/drv_venc_osal.h create mode 100755 drivers/vcodec/venc_hivna/hal_venc.c create mode 100755 drivers/vcodec/venc_hivna/hi_drv_mem.c create mode 100755 drivers/vcodec/venc_hivna/hi_drv_mem.h create mode 100755 drivers/vcodec/venc_hivna/venc_regulator.c create mode 100755 drivers/vcodec/venc_hivna/venc_regulator.h diff --git a/arch/arm64/boot/dts/hisilicon/kirin970-hikey970.dts b/arch/arm64/boot/dts/hisilicon/kirin970-hikey970.dts old mode 100755 new mode 100644 diff --git a/drivers/Kconfig b/drivers/Kconfig index a9472678c4e7..90c0db36e8c2 100755 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -210,4 +210,7 @@ source "drivers/fpga/Kconfig" source "drivers/tee/Kconfig" +source "drivers/vcodec/venc_hivna/Kconfig" + +source "drivers/vcodec/vdec_hivna/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 606569e0344f..bf0985254016 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -177,3 +177,5 @@ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_HISILICON_PLATFORM)+= hisi/ +obj-$(CONFIG_HI_VCODEC_VENC) += vcodec/venc_hivna/ +obj-$(CONFIG_HI_VCODEC_VDEC) += vcodec/vdec_hivna/ diff --git a/drivers/vcodec/vdec_hivna/Kconfig b/drivers/vcodec/vdec_hivna/Kconfig new file mode 100755 index 000000000000..e0b6d2acd50c --- /dev/null +++ b/drivers/vcodec/vdec_hivna/Kconfig @@ -0,0 +1,9 @@ +menu "Hisilicon video vdec support" +config HI_VCODEC_VDEC + tristate "Hisilicon video decoder support" + default n + help + This is the hisilicon decoder driver +endmenu + + diff --git a/drivers/vcodec/vdec_hivna/Makefile b/drivers/vcodec/vdec_hivna/Makefile new file mode 100755 index 000000000000..d13e142462f4 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HI_VCODEC_VDEC) += omxvdec/ vfmw_v4.0/ diff --git a/drivers/vcodec/vdec_hivna/omxvdec/Kconfig b/drivers/vcodec/vdec_hivna/omxvdec/Kconfig new file mode 100755 index 000000000000..fd4e31e3401d --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/Kconfig @@ -0,0 +1,5 @@ +config OMXVDEC + tristate "hisilicon omx video decoder support" + default n + ---help--- + This is the omxvdec driver \ No newline at end of file diff --git a/drivers/vcodec/vdec_hivna/omxvdec/Makefile b/drivers/vcodec/vdec_hivna/omxvdec/Makefile new file mode 100755 index 000000000000..e3773971fd01 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/Makefile @@ -0,0 +1,22 @@ + +TOP := drivers/../.. + +EXTRA_CFLAGS += -DENV_ARMLINUX_KERNEL +EXTRA_CFLAGS += -DHIVDEC_SMMU_SUPPORT + +EXTRA_CFLAGS += -Idrivers/vcodec/hi_vcodec/vdec_hivna/omxvdec +EXTRA_CFLAGS += -Idrivers/vcodec/hi_vcodec/vdec_hivna/vfmw_v4.0 +EXTRA_CFLAGS += -Idrivers/vcodec/hi_vcodec/vdec_hivna/vfmw_v4.0/format +EXTRA_CFLAGS += -fno-pic +EXTRA_CFLAGS += -DOMXVDEC_TVP_CONFLICT + +ifneq ($(TARGET_BUILD_VARIANT), user) +EXTRA_CFLAGS += -DUSER_DISABLE_VDEC_PROC +endif + +EXTRA_CFLAGS +=-DPLATFORM_KIRIN970 + +#build in +obj-$(CONFIG_HI_VCODEC_VDEC) += hi_omxvdec.o +hi_omxvdec-objs += omxvdec.o regulator.o + diff --git a/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.c b/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.c new file mode 100755 index 000000000000..c32191c42ced --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.c @@ -0,0 +1,569 @@ +/* + * vdec driver interface + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ + +#include +#include +#include + +#include "omxvdec.h" +#include "../vfmw_v4.0/linux_kernel_osal.h" +#include "../vfmw_v4.0/vfmw_dts.h" +#include "../vfmw_v4.0/scd_drv.h" +#include "../vfmw_v4.0/format/vdm_drv.h" +#include "../vfmw_v4.0/vfmw_intf.h" +/*lint -e774*/ + +#define PCTRL_PERI (0xE8A090A4) +#define PCTRL_PERI_SATA0 (0xE8A090BC) + +static int gIsNormalInit = 0; + +static int gIsDeviceDetected = 0; +static struct class *g_OmxVdecClass = NULL; +static const char g_OmxVdecDrvName[] = OMXVDEC_NAME; +static dev_t g_OmxVdecDevNum; +static OMXVDEC_ENTRY g_OmxVdecEntry; + +//Modified for 64-bit platform +typedef enum { + T_IOCTL_ARG, + T_IOCTL_ARG_COMPAT, + T_BUTT, +} COMPAT_TYPE_E; + +typedef enum { + KIRIN_970_ES, + KIRIN_970_CS, + KIRIN_980, + KIRIN_BUTT, +} KIRIN_PLATFORM_E; + +#define CHECK_PARA_SIZE_RETURN(size, para_size, command) \ +do { \ + if (size != para_size) { \ + printk(KERN_CRIT "%s: prarameter_size is error\n", command); \ + return -EINVAL; \ + } \ +}while(0) + +#define CHECK_RETURN(cond, else_print) \ +do { \ + if (!(cond)) { \ + printk(KERN_CRIT "%s : %s\n", __func__, else_print); \ + return -EINVAL; \ + } \ +}while(0) + +#define CHECK_SCENE_EQ_RETURN(cond, else_print) \ +do { \ + if (cond) { \ + printk(KERN_INFO "%s : %s\n", __func__, else_print); \ + return -EIO; \ + } \ +}while(0) + +static int omxvdec_setup_cdev(OMXVDEC_ENTRY *omxvdec, const struct file_operations *fops) +{ + int rc; + struct device *dev; + + g_OmxVdecClass = class_create(THIS_MODULE, "omxvdec_class"); + if (IS_ERR(g_OmxVdecClass)) { + rc = PTR_ERR(g_OmxVdecClass); + g_OmxVdecClass = NULL; + printk(KERN_CRIT "%s call class_create failed, rc : %d\n", __func__, rc); + return rc; + } + + rc = alloc_chrdev_region(&g_OmxVdecDevNum, 0, 1, "hisi video decoder"); + if (rc) { + printk(KERN_CRIT "%s call alloc_chrdev_region failed, rc : %d\n", __func__, rc); + goto cls_destroy; + } + + dev = device_create(g_OmxVdecClass, NULL, g_OmxVdecDevNum, NULL, OMXVDEC_NAME); + if (IS_ERR(dev)) { + rc = PTR_ERR(dev); + printk(KERN_CRIT "%s call device_create failed, rc : %d\n", __func__, rc); + goto unregister_region; + } + + cdev_init(&omxvdec->cdev, fops); + omxvdec->cdev.owner = THIS_MODULE; + omxvdec->cdev.ops = fops; + rc = cdev_add(&omxvdec->cdev, g_OmxVdecDevNum, 1); + if (rc < 0) { + printk(KERN_CRIT "%s call cdev_add failed, rc : %d\n", __func__, rc); + goto dev_destroy; + } + + return HI_SUCCESS; + +dev_destroy: + device_destroy(g_OmxVdecClass, g_OmxVdecDevNum); +unregister_region: + unregister_chrdev_region(g_OmxVdecDevNum, 1); +cls_destroy: + class_destroy(g_OmxVdecClass); + g_OmxVdecClass = NULL; + + return rc; +} + +static int omxvdec_cleanup_cdev(OMXVDEC_ENTRY *omxvdec) +{ + if (!g_OmxVdecClass) { + printk(KERN_CRIT "%s: Invalid g_OmxVdecClass is NULL", __func__); + return HI_FAILURE; + } + + cdev_del(&omxvdec->cdev); + device_destroy(g_OmxVdecClass, g_OmxVdecDevNum); + unregister_chrdev_region(g_OmxVdecDevNum, 1); + class_destroy(g_OmxVdecClass); + g_OmxVdecClass = NULL; + + return HI_SUCCESS; +} + +static int omxvdec_open(struct inode *inode, struct file *file) +{ + int ret = -EBUSY; + OMXVDEC_ENTRY *omxvdec = NULL; + + omxvdec = container_of(inode->i_cdev, OMXVDEC_ENTRY, cdev); + + VDEC_MUTEX_LOCK(&omxvdec->omxvdec_mutex); + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_scd); + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_vdh); + + if (omxvdec->open_count < MAX_OPEN_COUNT) { + omxvdec->open_count++; + if (omxvdec->open_count == 1) { + ret = VDEC_Regulator_Enable(); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s : VDEC_Regulator_Enable failed\n", __func__); + goto error0; + } + ret = VCTRL_OpenVfmw(); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s : vfmw open failed\n", __func__); + goto error1; + } + gIsNormalInit = 1; + } + + file->private_data = omxvdec; + ret = HI_SUCCESS; + } else { + printk(KERN_CRIT "%s open omxvdec instance too much\n", __func__); + ret = -EBUSY; + } + + printk(KERN_INFO "%s, open_count : %d\n", __func__, omxvdec->open_count); + goto exit; + +error1: + (void)VDEC_Regulator_Disable(); +error0: + omxvdec->open_count--; +exit: + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_vdh); + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_scd); + VDEC_MUTEX_UNLOCK(&omxvdec->omxvdec_mutex); + + return ret; +} + +static int omxvdec_release(struct inode *inode, struct file *file) +{ + OMXVDEC_ENTRY *omxvdec = NULL; + int ret = HI_SUCCESS; + + omxvdec = file->private_data; + if (omxvdec == NULL) { + printk(KERN_CRIT "%s: invalid omxvdec is null\n", __func__); + return -EFAULT; + } + + VDEC_MUTEX_LOCK(&omxvdec->omxvdec_mutex); + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_scd); + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_vdh); + + if (file->private_data == NULL) { + printk(KERN_CRIT "%s: invalid file->private_data is null\n", __func__); + ret = -EFAULT; + goto exit; + } + + if (omxvdec->open_count > 0) + omxvdec->open_count--; + + if (omxvdec->open_count == 0) { + VCTRL_CloseVfmw(); + VDEC_Regulator_Disable(); + gIsNormalInit = 0; + } + file->private_data = NULL; + + printk(KERN_INFO "exit %s , open_count : %d\n", __func__, omxvdec->open_count); +exit: + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_vdh); + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_scd); + VDEC_MUTEX_UNLOCK(&omxvdec->omxvdec_mutex); + + return ret; +} + +/* Modified for 64-bit platform */ +static int omxvdec_compat_get_data(COMPAT_TYPE_E eType, void __user *pUser, void *pData) +{ + int ret = HI_SUCCESS; + int s32Data = 0; + compat_ulong_t CompatData = 0; + OMXVDEC_IOCTL_MSG *pIoctlMsg = (OMXVDEC_IOCTL_MSG *)pData; + + if (NULL == pUser || NULL == pData) { + printk(KERN_CRIT "%s: param is null\n", __func__); + return HI_FAILURE; + } + + switch (eType) { + case T_IOCTL_ARG: + if (copy_from_user(pIoctlMsg, pUser, sizeof(*pIoctlMsg))) { + printk(KERN_CRIT "%s puser copy failed\n", __func__); + ret = HI_FAILURE; + } + break; + case T_IOCTL_ARG_COMPAT: { + COMPAT_IOCTL_MSG __user *pCompatMsg = pUser; + + ret |= get_user(s32Data, &(pCompatMsg->chan_num)); + pIoctlMsg->chan_num = s32Data; + + ret |= get_user(s32Data, &(pCompatMsg->in_size)); + pIoctlMsg->in_size = s32Data; + + ret |= get_user(s32Data, &(pCompatMsg->out_size)); + pIoctlMsg->out_size = s32Data; + + ret |= get_user(CompatData, &(pCompatMsg->in)); + pIoctlMsg->in = (void *) ((unsigned long)CompatData); + + ret |= get_user(CompatData, &(pCompatMsg->out)); + pIoctlMsg->out = (void *) ((unsigned long)CompatData); + } + break; + default: + printk(KERN_CRIT "%s: unkown type %d\n", __func__, eType); + ret = HI_FAILURE; + break; + } + + return ret; +} + +static long omxvdec_ioctl_common(struct file *file, unsigned int cmd, unsigned long arg, COMPAT_TYPE_E type) +{ + int ret; + int x_scene; + OMXVDEC_IOCTL_MSG vdec_msg; + void *u_arg = (void *)arg; + OMXVDEC_ENTRY *omxvdec = file->private_data; + + OMXSCD_REG_CFG_S scd_reg_cfg; + SCD_STATE_REG_S scd_state_reg; + OMXVDH_REG_CFG_S vdm_reg_cfg; + VDMHAL_BACKUP_S vdm_state_reg; + int vdm_is_run; + + x_scene = VCTRL_Scen_Ident(cmd); + CHECK_SCENE_EQ_RETURN(x_scene == 1, "xxx scene"); + + CHECK_RETURN(omxvdec != NULL, "omxvdec is null"); + + ret = omxvdec_compat_get_data(type, u_arg, &vdec_msg); + CHECK_RETURN(ret == HI_SUCCESS, "compat data get failed"); + + switch (cmd) { + case VDEC_IOCTL_VDM_PROC: + CHECK_PARA_SIZE_RETURN(sizeof(vdm_reg_cfg), vdec_msg.in_size, "VDEC_IOCTL_VDM_PROC_IN"); + CHECK_PARA_SIZE_RETURN(sizeof(vdm_state_reg), vdec_msg.out_size, "VDEC_IOCTL_VDM_PROC_OUT"); + if (copy_from_user(&vdm_reg_cfg, vdec_msg.in, sizeof(vdm_reg_cfg))) { + printk(KERN_CRIT "VDEC_IOCTL_VDM_PROC : copy_from_user failed\n"); + return -EFAULT; + } + + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_vdh); + dsb(sy); + + ret = VCTRL_VDMHal_Process(&vdm_reg_cfg, &vdm_state_reg); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "VCTRL_VDMHal_Process failed\n"); + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_vdh); + return -EIO; + } + + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_vdh); + if (copy_to_user(vdec_msg.out, &vdm_state_reg, sizeof(vdm_state_reg))) { + printk(KERN_CRIT "VDEC_IOCTL_VDM_PROC : copy_to_user failed\n"); + return -EFAULT; + } + break; + + case VDEC_IOCTL_GET_VDM_HWSTATE: + CHECK_PARA_SIZE_RETURN(sizeof(vdm_is_run), vdec_msg.out_size, "VDEC_IOCTL_GET_VDM_HWSTATE"); + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_vdh); + vdm_is_run = VCTRL_VDMHAL_IsRun(); + + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_vdh); + if (copy_to_user(vdec_msg.out, &vdm_is_run, sizeof(vdm_is_run))) { + printk(KERN_CRIT "VDEC_IOCTL_GET_VDM_HWSTATE : copy_to_user failed\n"); + return -EFAULT; + } + break; + + case VDEC_IOCTL_SCD_PROC: + CHECK_PARA_SIZE_RETURN(sizeof(scd_reg_cfg), vdec_msg.in_size, "VDEC_IOCTL_SCD_PROC_IN"); + CHECK_PARA_SIZE_RETURN(sizeof(scd_state_reg), vdec_msg.out_size, "VDEC_IOCTL_SCD_PROC_OUT"); + if (copy_from_user(&scd_reg_cfg, vdec_msg.in, sizeof(scd_reg_cfg))) { + printk(KERN_CRIT "VDEC_IOCTL_SCD_PROC : copy_from_user failed\n"); + return -EFAULT; + } + + VDEC_MUTEX_LOCK(&omxvdec->vdec_mutex_scd); + dsb(sy); + + ret = VCTRL_SCDHal_Process(&scd_reg_cfg, &scd_state_reg); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "VCTRL_SCDHal_Process failed\n"); + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_scd); + return -EIO; + } + + VDEC_MUTEX_UNLOCK(&omxvdec->vdec_mutex_scd); + if (copy_to_user(vdec_msg.out, &scd_state_reg, sizeof(scd_state_reg))) { + printk(KERN_CRIT "VDEC_IOCTL_SCD_PROC : copy_to_user failed\n"); + return -EFAULT; + } + break; + + default: + /* could not handle ioctl */ + printk(KERN_CRIT "%s %d: cmd : %d is not supported\n", __func__, __LINE__, _IOC_NR(cmd)); + return -ENOTTY; + } + + return 0; +} + +static long omxvdec_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return omxvdec_ioctl_common(file, cmd, arg, T_IOCTL_ARG); +} +/* Modified for 64-bit platform */ +#ifdef CONFIG_COMPAT +static long omxvdec_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + void *user_ptr = compat_ptr(arg); + return omxvdec_ioctl_common(file, cmd, (unsigned long)user_ptr, T_IOCTL_ARG_COMPAT); +} +#endif + +static const struct file_operations omxvdec_fops = { + .owner = THIS_MODULE, + .open = omxvdec_open, + .unlocked_ioctl = omxvdec_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = omxvdec_compat_ioctl, +#endif + .release = omxvdec_release, +}; + +static int omxvdec_probe(struct platform_device *pltdev) +{ + int ret; + + if (gIsDeviceDetected == 1) { + printk(KERN_DEBUG "Already probe omxvdec\n"); + return 0; + } + + platform_set_drvdata(pltdev, NULL); + + memset(&g_OmxVdecEntry, 0, sizeof(OMXVDEC_ENTRY)); /* unsafe_function_ignore: memset */ + VDEC_INIT_MUTEX(&g_OmxVdecEntry.omxvdec_mutex); + VDEC_INIT_MUTEX(&g_OmxVdecEntry.vdec_mutex_scd); + VDEC_INIT_MUTEX(&g_OmxVdecEntry.vdec_mutex_vdh); + + ret = omxvdec_setup_cdev(&g_OmxVdecEntry, &omxvdec_fops); + if (ret < 0) { + printk(KERN_CRIT "%s call omxvdec_setup_cdev failed\n", __func__); + goto cleanup0; + } + + ret = VDEC_Regulator_Probe(&pltdev->dev); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s call Regulator_Initialize failed\n", __func__); + goto cleanup1; + } + + g_OmxVdecEntry.device = &pltdev->dev; + platform_set_drvdata(pltdev, &g_OmxVdecEntry); + gIsDeviceDetected = 1; + + return 0; + +cleanup1: + omxvdec_cleanup_cdev(&g_OmxVdecEntry); + +cleanup0: + return ret; +} + +static int omxvdec_remove(struct platform_device *pltdev) +{ + OMXVDEC_ENTRY *omxvdec = NULL; + + omxvdec = platform_get_drvdata(pltdev); + if (omxvdec != NULL) { + if (IS_ERR(omxvdec)) { + printk(KERN_ERR "call platform_get_drvdata err, errno : %ld\n", PTR_ERR(omxvdec)); + } else { + omxvdec_cleanup_cdev(omxvdec); + VDEC_Regulator_Remove(&pltdev->dev); + platform_set_drvdata(pltdev, NULL); + gIsDeviceDetected = 0; + } + } + + return 0; +} + +static int omxvdec_suspend(struct platform_device *pltdev, pm_message_t state) +{ + int ret; + + printk(KERN_INFO "%s enter\n", __func__); + + if (gIsNormalInit != 0) + VCTRL_Suspend(); + + ret = VDEC_Regulator_Disable(); + if (ret != HI_SUCCESS) + printk(KERN_CRIT "%s disable regulator failed\n", __func__); + + printk(KERN_INFO "%s success\n", __func__); + + return HI_SUCCESS; +} + +static int omxvdec_resume(struct platform_device *pltdev) +{ + int ret; + CLK_RATE_E resume_clk = VDEC_CLK_RATE_NORMAL; + + printk(KERN_INFO "%s enter\n", __func__); + VDEC_Regulator_GetClkRate(&resume_clk); + + if (gIsNormalInit != 0) { + ret = VDEC_Regulator_Enable(); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s enable regulator failed\n", __func__); + return HI_FAILURE; + } + + ret = VDEC_Regulator_SetClkRate(resume_clk); + if (ret != HI_SUCCESS) + { + printk(KERN_CRIT "%s, set clk failed\n", __func__); + } + + VCTRL_Resume(); + } + + printk(KERN_INFO "%s success\n", __func__); + + return HI_SUCCESS; +} + +static void omxvdec_device_release(struct device *dev) +{ + return; +} + +static struct platform_driver omxvdec_driver = { + + .probe = omxvdec_probe, + .remove = omxvdec_remove, + .suspend = omxvdec_suspend, + .resume = omxvdec_resume, + .driver = { + .name = (char*) g_OmxVdecDrvName, + .owner = THIS_MODULE, + .of_match_table = Hisi_Vdec_Match_Table + }, +}; + +static struct platform_device omxvdec_device = { + + .name = g_OmxVdecDrvName, + .id = -1, + .dev = { + .platform_data = NULL, + .release = omxvdec_device_release, + }, +}; + +int __init OMXVDEC_DRV_ModInit(void) +{ + int ret; + + ret = platform_device_register(&omxvdec_device); + if (ret < 0) { + printk(KERN_CRIT "%s call platform_device_register failed\n", __func__); + return ret; + } + + ret = platform_driver_register(&omxvdec_driver); + if (ret < 0) { + printk(KERN_CRIT "%s call platform_driver_register failed\n", __func__); + goto exit; + } +#ifdef MODULE + printk(KERN_INFO "Load hi_omxvdec.ko :%d success\n", OMXVDEC_VERSION); +#endif + + return HI_SUCCESS; +exit: + platform_device_unregister(&omxvdec_device); + + return ret; +} + +void __exit OMXVDEC_DRV_ModExit(void) +{ + platform_driver_unregister(&omxvdec_driver); + platform_device_unregister(&omxvdec_device); + +#ifdef MODULE + printk(KERN_INFO "Unload hi_omxvdec.ko : %d success\n", OMXVDEC_VERSION); +#endif + +} + +module_init(OMXVDEC_DRV_ModInit); +module_exit(OMXVDEC_DRV_ModExit); + +MODULE_AUTHOR("gaoyajun@hisilicon.com"); +MODULE_DESCRIPTION("vdec driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.h b/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.h new file mode 100755 index 000000000000..12e6456720d1 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/omxvdec.h @@ -0,0 +1,122 @@ +#ifndef __OMXVDEC_H__ +#define __OMXVDEC_H__ + +#include "regulator.h" +#include "../vfmw_v4.0/public.h" +#include "../vfmw_v4.0/scd_drv.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_COMPAT +#include +#endif + +#if defined(__KERNEL__) +#include +#endif + +#define OMXVDEC_NAME "hi_vdec" +#define PATH_LEN (256) +#define OMXVDEC_VERSION (2017032300) +#define MAX_OPEN_COUNT (32) + +#ifndef NULL +#define NULL (0L) +#endif + +#define HI_SUCCESS (0) +#define HI_FAILURE (-1) + +#define RETURN_FAIL_IF_COND_IS_TRUE(cond, str) \ +do { \ + if (cond) \ + { \ + printk(KERN_CRIT "[%s : %d]- %s\n", __func__, __LINE__, str); \ + return HI_FAILURE; \ + } \ +}while(0) + +#define VDEC_INIT_MUTEX(lock) \ +do { \ + mutex_init(lock); \ +} while(0) + +#define VDEC_MUTEX_LOCK(lock) \ +do { \ + mutex_lock(lock); \ +} while(0) + +#define VDEC_MUTEX_UNLOCK(lock) \ +do { \ + mutex_unlock(lock); \ +} while(0) + +typedef struct { + unsigned char u8IsMapVirtual; + unsigned char u8IsMapped; + unsigned int u32ShareFd; + unsigned int u32StartPhyAddr; + unsigned int u32Size; + void *pStartVirAddr; +} MEM_BUFFER_S; + +typedef struct hi_OMXVDEC_IOCTL_MSG { + int chan_num; + int in_size; + int out_size; + void *in; + void *out; +} OMXVDEC_IOCTL_MSG; + +//Modified for 64-bit platform +typedef struct hi_COMPAT_IOCTL_MSG { + int chan_num; + int in_size; + int out_size; + compat_ulong_t in; + compat_ulong_t out; +} COMPAT_IOCTL_MSG; + +typedef struct { + unsigned int open_count; + atomic_t nor_chan_num; + atomic_t sec_chan_num; + MEM_BUFFER_S com_msg_pool; + struct mutex omxvdec_mutex; + struct mutex vdec_mutex_scd; + struct mutex vdec_mutex_vdh; + struct cdev cdev; + struct device *device; +} OMXVDEC_ENTRY; + +typedef int(*VDEC_PROC_CMD) (OMXVDEC_IOCTL_MSG *pVdecMsg); + +#define VDEC_IOCTL_MAGIC 'v' + +#define VDEC_IOCTL_SET_CLK_RATE \ + _IO(VDEC_IOCTL_MAGIC, 20) + +#define VDEC_IOCTL_GET_VDM_HWSTATE \ + _IO(VDEC_IOCTL_MAGIC, 21) + +#define VDEC_IOCTL_SCD_PROC \ + _IO(VDEC_IOCTL_MAGIC, 22) + +#define VDEC_IOCTL_VDM_PROC \ + _IO(VDEC_IOCTL_MAGIC, 23) + +#endif diff --git a/drivers/vcodec/vdec_hivna/omxvdec/regulator.c b/drivers/vcodec/vdec_hivna/omxvdec/regulator.c new file mode 100755 index 000000000000..8fe86ba42c0f --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/regulator.c @@ -0,0 +1,395 @@ +/* + * vdec regulator manager + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ + +#include "regulator.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*lint -e774*/ +#define VDEC_REGULATOR_NAME "ldo_vdec" +#define MEDIA_REGULATOR_NAME "ldo_media" +#define VCODEC_CLOCK_NAME "clk_gate_vdecfreq" +#define VCODEC_CLK_RATE "dec_clk_rate" + +static unsigned int g_clock_values[] = {450000000, 300000000, 185000000}; +static unsigned int g_VdecClkRate_l = 185000000; +static unsigned int g_VdecClkRate_n = 300000000; +static unsigned int g_VdecClkRate_h = 450000000; +static unsigned int g_CurClkRate = 0; +static int g_VdecPowerOn = 0; + +static struct clk *g_PvdecClk = NULL; +static struct regulator *g_VdecRegulator = NULL; +static struct regulator *g_MediaRegulator = NULL; +static struct iommu_domain *g_VdecSmmuDomain = NULL; + +struct mutex g_RegulatorMutex; +static VFMW_DTS_CONFIG_S g_DtsConfig; +static CLK_RATE_E g_ResumeClkType = VDEC_CLK_RATE_LOW; + +#ifdef HIVDEC_SMMU_SUPPORT +/*---------------------------------------- + func: iommu enable intf + ----------------------------------------*/ +static int VDEC_Enable_Iommu(struct device *dev) +{ + int ret = HI_FAILURE; + g_VdecSmmuDomain = iommu_domain_alloc(dev->bus); + if (NULL == g_VdecSmmuDomain) { + printk(KERN_ERR "%s iommu_domain_alloc failed!\n", __func__); + return HI_FAILURE; + } + + ret = iommu_attach_device(g_VdecSmmuDomain, dev); + if (ret) { + printk(KERN_ERR "iommu_attach_device failed!\n"); + goto out_free_domain; + } + return HI_SUCCESS; +out_free_domain: + iommu_domain_free(g_VdecSmmuDomain); + return HI_FAILURE; +} + +static void VDEC_Disable_Iommu(struct device *dev) +{ + g_VdecSmmuDomain = NULL; + if( g_VdecSmmuDomain && dev) { + iommu_detach_device(g_VdecSmmuDomain, dev); + iommu_domain_free(g_VdecSmmuDomain); + g_VdecSmmuDomain = NULL; + } + +} + +static unsigned long long VDEC_GetSmmuBasePhy(struct device *dev) +{ + struct iommu_domain_data *domain_data = NULL; + + if (VDEC_Enable_Iommu(dev) == HI_FAILURE) + return 0; + + domain_data = (struct iommu_domain_data *)(g_VdecSmmuDomain->priv); + + return (unsigned long long) (domain_data->phy_pgd_base); +} + +#endif + +static int read_clock_rate_value(struct device_node *np, unsigned int index, unsigned int *clock) +{ + int ret; + ret = of_property_read_u32_index(np, VCODEC_CLK_RATE, index, clock); + if (ret) { + printk(KERN_CRIT "read clock rate[%d] failed\n", index); + *clock = g_clock_values[index]; + return HI_FAILURE; + } + + return HI_SUCCESS; +} + +static int VDEC_Init_ClockRate(struct device *dev) +{ + int ret; + struct clk *pvdec_clk = NULL; + + pvdec_clk = devm_clk_get(dev, VCODEC_CLOCK_NAME); + if (IS_ERR_OR_NULL(pvdec_clk)) { + printk(KERN_CRIT "%s can not get clock\n", __func__); + return HI_FAILURE; + } + + g_PvdecClk = pvdec_clk; + ret = read_clock_rate_value(dev->of_node, 0, &g_VdecClkRate_h); + ret += read_clock_rate_value(dev->of_node, 1, &g_VdecClkRate_n); + ret += read_clock_rate_value(dev->of_node, 2, &g_VdecClkRate_l); + RETURN_FAIL_IF_COND_IS_TRUE(ret, "read clock failed"); + + g_CurClkRate = g_VdecClkRate_l; + + return HI_SUCCESS; +} + +static int VDEC_GetDtsConfigInfo(struct device *dev, VFMW_DTS_CONFIG_S *pDtsConfig) +{ + int ret; + struct device_node *np_crg = NULL; + struct device_node *np = dev->of_node; + struct resource res; + + RETURN_FAIL_IF_COND_IS_TRUE(dev->of_node == NULL, "device node is null"); + RETURN_FAIL_IF_COND_IS_TRUE(pDtsConfig == NULL, "dts config is null"); + + pDtsConfig->VdecIrqNumNorm = irq_of_parse_and_map(np, 0); + RETURN_FAIL_IF_COND_IS_TRUE(pDtsConfig->VdecIrqNumNorm == 0, "get irq num failed"); + + /* + FIXME irq_of_parse_and_map(np, 1); + FIXME irq_of_parse_and_map(np, 2); + */ + pDtsConfig->VdecIrqNumProt = 323; + pDtsConfig->VdecIrqNumSafe = 324; + + /* Get reg base addr & size, return 0 if success */ + ret = of_address_to_resource(np, 0, &res); + RETURN_FAIL_IF_COND_IS_TRUE(ret, "of_address_to_resource failed"); + + pDtsConfig->VdhRegBaseAddr = res.start; + pDtsConfig->VdhRegRange = resource_size(&res); + +#ifdef HIVDEC_SMMU_SUPPORT + /* Get reg base addr, return 0 if failed */ + pDtsConfig->SmmuPageBaseAddr = VDEC_GetSmmuBasePhy(dev); + RETURN_FAIL_IF_COND_IS_TRUE(pDtsConfig->SmmuPageBaseAddr == 0, "get smmu base addr failed"); +#endif + + np_crg = of_find_compatible_node(NULL, NULL, "hisilicon,media2-crg"); + RETURN_FAIL_IF_COND_IS_TRUE(!np_crg, "can't find media2-crg node"); + + ret = of_address_to_resource(np_crg, 0, &res); + RETURN_FAIL_IF_COND_IS_TRUE(ret, "of_address_to_resource failed"); + pDtsConfig->PERICRG_RegBaseAddr = res.start; + + ret = VDEC_Init_ClockRate(dev); + RETURN_FAIL_IF_COND_IS_TRUE(ret != HI_SUCCESS, "init clock failed"); + + return HI_SUCCESS; +} + +/******************************** SHARE FUNC **********************************/ + +/*---------------------------------------- + func: regulator probe entry + ----------------------------------------*/ +int VDEC_Regulator_Probe(struct device *dev) +{ + int ret; + g_VdecRegulator = NULL; + g_MediaRegulator = NULL; + + if (dev == NULL) { + printk(KERN_CRIT "%s, invalid params", __func__); + return HI_FAILURE; + } + + memset(&g_DtsConfig, 0, sizeof(g_DtsConfig)); /* unsafe_function_ignore: memset */ + ret = VDEC_GetDtsConfigInfo(dev, &g_DtsConfig); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s Regulator_GetDtsConfigInfo failed\n", __func__); + return HI_FAILURE; + } + + ret = VFMW_SetDtsConfig(&g_DtsConfig); + if (ret != HI_SUCCESS) { + printk(KERN_CRIT "%s VFMW_SetDtsConfig failed\n", __func__); + return HI_FAILURE; + } + VDEC_INIT_MUTEX(&g_RegulatorMutex); + + return HI_SUCCESS; +} + +/*---------------------------------------- + func: regulator deinitialize + ----------------------------------------*/ +int VDEC_Regulator_Remove(struct device * dev) +{ + VDEC_MUTEX_LOCK(&g_RegulatorMutex); + + VDEC_Disable_Iommu(dev); + g_VdecRegulator = NULL; + g_MediaRegulator = NULL; + g_PvdecClk = NULL; + + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_SUCCESS; +} + +/*---------------------------------------- + func: enable regulator + ----------------------------------------*/ +int VDEC_Regulator_Enable(void) +{ + int ret; + VDEC_MUTEX_LOCK(&g_RegulatorMutex); + + if (g_VdecPowerOn == 1) { + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + return HI_SUCCESS; + } + + if (g_PvdecClk == NULL) { + printk(KERN_CRIT "%s: invalid g_PvdecClk is NULL\n", __func__); + goto error_exit; + } + + ret = clk_prepare_enable(g_PvdecClk); + if (ret != 0) { + printk(KERN_CRIT "%s clk_prepare_enable failed\n", __func__); + goto error_exit; + } + + ret = clk_set_rate(g_PvdecClk, g_VdecClkRate_l); + if (ret) + { + printk(KERN_CRIT "%s Failed to clk_set_rate:%u, return %d\n", __func__, g_VdecClkRate_l, ret); + goto error_unprepare_clk; + } + + printk(KERN_INFO "vdec regulator enable\n"); + g_VdecPowerOn = 1; + + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_SUCCESS; + +error_unprepare_clk: + clk_disable_unprepare(g_PvdecClk); +error_exit: + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_FAILURE; +} + +/*---------------------------------------- + func: disable regulator + ----------------------------------------*/ +int VDEC_Regulator_Disable(void) +{ + int ret; + + VDEC_MUTEX_LOCK(&g_RegulatorMutex); + + if (g_VdecPowerOn == 0) { + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + return HI_SUCCESS; + } + + if (g_PvdecClk == NULL) { + printk(KERN_CRIT "%s g_PvdecClk is NULL\n", __func__); + goto error_exit; + } + + ret = clk_set_rate(g_PvdecClk, g_VdecClkRate_l); + if (ret) { + printk(KERN_CRIT "%s Failed to clk_set_rate:%u, return %d\n", __func__, g_VdecClkRate_l, ret); + //goto error_exit;//continue, no return + } + + clk_disable_unprepare(g_PvdecClk); + + g_VdecPowerOn = 0; + + printk(KERN_INFO "vdec regulator disable\n"); + + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_SUCCESS; + +error_exit: + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_FAILURE; +} + +/*---------------------------------------- + func: get decoder clock rate + ----------------------------------------*/ +void VDEC_Regulator_GetClkRate(CLK_RATE_E *pClkRate) +{ + VDEC_MUTEX_LOCK(&g_RegulatorMutex); + *pClkRate = g_ResumeClkType; + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); +} + +int VDEC_Regulator_SetClkRate(CLK_RATE_E eClkRate) +{ + int ret = 0; + unsigned int rate = 0; + unsigned char need_set_flag = 1; + + VDEC_MUTEX_LOCK(&g_RegulatorMutex); + + if (g_DtsConfig.IsFPGA) { + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + return HI_SUCCESS; + } + + if (IS_ERR_OR_NULL(g_PvdecClk)) { + printk(KERN_ERR "Couldn't get clk [%s]\n", __func__); + goto error_exit; + } + + rate = (unsigned int) clk_get_rate(g_PvdecClk); + switch (eClkRate) { + case VDEC_CLK_RATE_LOW: + if (g_VdecClkRate_l == rate) { + need_set_flag = 0; + } else { + rate = g_VdecClkRate_l; + need_set_flag = 1; + } + break; + + case VDEC_CLK_RATE_NORMAL: + if (g_VdecClkRate_n == rate) { + need_set_flag = 0; + } + else { + rate = g_VdecClkRate_n; + need_set_flag = 1; + } + break; + + case VDEC_CLK_RATE_HIGH: + if (g_VdecClkRate_h == rate) { + need_set_flag = 0; + } else { + rate = g_VdecClkRate_h; + need_set_flag = 1; + } + break; + + default: + printk(KERN_ERR "[%s] unsupport clk rate enum %d\n", __func__, eClkRate); + goto error_exit; + } + + if (need_set_flag == 1) { + ret = clk_set_rate(g_PvdecClk, rate); + if (ret != 0) { + printk(KERN_ERR "Failed to clk_set_rate %u HZ[%s] ret : %d\n", rate, __func__, ret); + goto error_exit; + } + g_CurClkRate = rate; + g_ResumeClkType = eClkRate; + } + + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_SUCCESS; + +error_exit: + VDEC_MUTEX_UNLOCK(&g_RegulatorMutex); + + return HI_FAILURE; +} diff --git a/drivers/vcodec/vdec_hivna/omxvdec/regulator.h b/drivers/vcodec/vdec_hivna/omxvdec/regulator.h new file mode 100755 index 000000000000..0c8173b3ecd6 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/omxvdec/regulator.h @@ -0,0 +1,27 @@ +#ifndef __VDEC_REGULATOR_H__ +#define __VDEC_REGULATOR_H__ + +#include "../vfmw_v4.0/vfmw_dts.h" +#include "omxvdec.h" +#include + +typedef enum { + VDEC_CLK_RATE_LOW = 0, + VDEC_CLK_RATE_NORMAL, + VDEC_CLK_RATE_HIGH, + VDEC_CLK_RATE_BUTT, +}CLK_RATE_E; + +static const struct of_device_id Hisi_Vdec_Match_Table[] = { + {.compatible = "hisi,kirin970-vdec",}, + { } +}; +int VDEC_Regulator_Probe(struct device *dev); +int VDEC_Regulator_Remove(struct device *dev); +int VDEC_Regulator_Enable(void); +int VDEC_Regulator_Disable(void); +void VDEC_Regulator_GetClkRate(CLK_RATE_E *pClkRate); +int VDEC_Regulator_SetClkRate(CLK_RATE_E eClkRate); + +#endif + diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/Kconfig b/drivers/vcodec/vdec_hivna/vfmw_v4.0/Kconfig new file mode 100755 index 000000000000..b367adc0ee24 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/Kconfig @@ -0,0 +1,5 @@ +config VDEC_VFMW + tristate "hisilicon video firmware support" + default n + ---help--- + This is the vfmw driver diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/Makefile b/drivers/vcodec/vdec_hivna/vfmw_v4.0/Makefile new file mode 100755 index 000000000000..bf06514a99d4 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/Makefile @@ -0,0 +1,12 @@ +TOP := drivers/../.. +VFMW_DIR := drivers/vcodec/vdec_hivna + +include $(VFMW_DIR)/vfmw_v4.0/vfmw_make.cfg + +EXTRA_CFLAGS += -Idrivers/vcodec/vdec_hivna +EXTRA_CFLAGS += -Idrivers/vcodec/vdec_hivna/omxvdec +EXTRA_CFLAGS += $(VFMW_CFLAGS) -fno-pic + +#build in +obj-$(CONFIG_HI_VCODEC_VDEC) += hi_vfmw.o +hi_vfmw-objs := $(VFMW_CFILES) diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_drv.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_drv.h new file mode 100755 index 000000000000..f6f1e19621b1 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_drv.h @@ -0,0 +1,166 @@ +#ifndef __VDM_DRV_HEADER__ +#define __VDM_DRV_HEADER__ +#include "../vfmw.h" +#include "../sysconfig.h" + +#define VDMDRV_OK (0) +#define VDMDRV_ERR (-1) + +#define MSG_SLOT_SIZE (256) + +#define LUMA_HISTORGAM_NUM (32) + +#define HEVC_ONE_MSG_SLOT_LEN (320) // 64*5 +#define MAX_FRAME_NUM (32) +#ifdef VFMW_HEVC_SUPPORT +#define USE_MSG_SLOT_SIZE HEVC_ONE_MSG_SLOT_LEN +#else +#define USE_MSG_SLOT_SIZE MSG_SLOT_SIZE +#endif +typedef enum { + VDH_SHAREFD_MESSAGE_POOL = 0, + VDH_SHAREFD_STREAM_BUF = 1, + VDH_SHAREFD_PMV_BUF = 2, + VDH_SHAREFD_FRM_BUF = 3, + VDH_SHAREFD_MAX = (VDH_SHAREFD_FRM_BUF + MAX_FRAME_NUM) +}VDH_SHAREFD; +typedef enum { + VDH_STATE_REG = 1, + INT_STATE_REG = 2, + INT_MASK_REG = 3, + VCTRL_STATE_REG = 4, +} REG_ID_E; + +typedef enum { + VDM_IDLE_STATE = 0, + VDM_DECODE_STATE = 1, + VDM_REPAIR_STATE_0 = 2, + VDM_REPAIR_STATE_1 = 3 +} VDMDRV_STATEMACHINE_E; + +typedef enum { + VDMDRV_SLEEP_STAGE_NONE = 0, + VDMDRV_SLEEP_STAGE_PREPARE, + VDMDRV_SLEEP_STAGE_SLEEP +} VDMDRV_SLEEP_STAGE_E; + +typedef enum { + FIRST_REPAIR = 0, + SECOND_REPAIR +} REPAIRTIME_S; + +typedef enum hi_CONFIG_VDH_CMD { + CONFIG_VDH_AfterDec_CMD = 200, + CONFIG_VDH_ACTIVATEDEC_CMD +} CONFIG_VDH_CMD; + +typedef struct { + unsigned int vdh_reset_flag; + unsigned int GlbResetFlag; + int VdhStartRepairFlag; + int VdhStartHwDecFlag; + int VdhBasicCfg0; + int VdhBasicCfg1; + int VdhAvmAddr; + int VdhVamAddr; + int VdhStreamBaseAddr; + int VdhEmarId; + int VdhYstAddr; + int VdhYstride; + int VdhUvstride;//VREG_UVSTRIDE_1D + int VdhCfgInfoAddr;//CFGINFO_ADDR + int VdhUvoffset; + int VdhRefPicType; + int VdhFfAptEn; + REPAIRTIME_S RepairTime; + VID_STD_E VidStd; + int ValidGroupNum0; + int vdh_share_fd[VDH_SHAREFD_MAX]; + unsigned int vdhFrmBufNum; + int IsFrmBufRemap; + int IsPmvBufRemap; + int IsAllBufRemap; +} OMXVDH_REG_CFG_S; + +typedef struct { + // vdm register base vir addr + int *pVdmRegVirAddr; + + // vdm hal base addr + unsigned int HALMemBaseAddr; + int HALMemSize; + int VahbStride; + + /* message pool */ + unsigned int MsgSlotAddr[256]; + int ValidMsgSlotNum; + + /* vlc code table */ + unsigned int H264TabAddr; /* 32 Kbyte */ + unsigned int MPEG2TabAddr; /* 32 Kbyte */ + unsigned int MPEG4TabAddr; /* 32 Kbyte */ + unsigned int AVSTabAddr; /* 32 Kbyte */ + unsigned int VC1TabAddr; + /* cabac table */ + unsigned int H264MnAddr; + /* nei info for vdh for hevc */ + unsigned int sed_top_phy_addr; + unsigned int pmv_top_phy_addr; + unsigned int pmv_left_phy_addr; + unsigned int rcn_top_phy_addr; + unsigned int mn_phy_addr; + unsigned int tile_segment_info_phy_addr; + unsigned int dblk_left_phy_addr; + unsigned int dblk_top_phy_addr; + unsigned int sao_left_phy_addr; + unsigned int sao_top_phy_addr; + unsigned int ppfd_phy_addr; + int ppfd_buf_len; + + /*nei info for vdh */ + unsigned int SedTopAddr; /* len = 64*4*x */ + unsigned int PmvTopAddr; /* len = 64*4*x */ + unsigned int RcnTopAddr; /* len = 64*4*x */ + unsigned int ItransTopAddr; + unsigned int DblkTopAddr; + unsigned int PpfdBufAddr; + unsigned int PpfdBufLen; + + unsigned int IntensityConvTabAddr; + unsigned int BitplaneInfoAddr; + unsigned int Vp6TabAddr; + unsigned int Vp8TabAddr; + + /* VP9 */ + unsigned int DblkLeftAddr; + unsigned int Vp9ProbTabAddr; + unsigned int Vp9ProbCntAddr; + + unsigned char *luma_2d_vir_addr; + unsigned int luma_2d_phy_addr; + unsigned char *chrom_2d_vir_addr; + unsigned int chrom_2d_phy_addr; +} VDMHAL_HWMEM_S; + +typedef struct { + unsigned int Int_State_Reg; + + unsigned int BasicCfg1; + unsigned int VdmState; + unsigned int Mb0QpInCurrPic; + unsigned int SwitchRounding; + unsigned int SedSta; + unsigned int SedEnd0; + + unsigned int DecCyclePerPic; + unsigned int RdBdwidthPerPic; + unsigned int WrBdWidthPerPic; + unsigned int RdReqPerPic; + unsigned int WrReqPerPic; + unsigned int LumaSumHigh; + unsigned int LumaSumLow; + unsigned int LumaHistorgam[LUMA_HISTORGAM_NUM]; +} VDMHAL_BACKUP_S; + +extern VDMHAL_HWMEM_S g_HwMem[MAX_VDH_NUM]; +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.c new file mode 100755 index 000000000000..9c10bb41a66f --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.c @@ -0,0 +1,553 @@ +/* + * vdm hal interface + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ + +#include "vfmw.h" +#include "mem_manage.h" +//#include "public.h" +#include "scd_drv.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "omxvdec.h" +#include "linux_kernel_osal.h" + +#ifdef VFMW_MPEG2_SUPPORT +#include "vdm_hal_mpeg2.h" +#endif +#ifdef VFMW_H264_SUPPORT +#include "vdm_hal_h264.h" +#endif +#ifdef VFMW_HEVC_SUPPORT +#include "vdm_hal_hevc.h" +#endif +#ifdef VFMW_MPEG4_SUPPORT +#include "vdm_hal_mpeg4.h" +#endif +#ifdef VFMW_VP8_SUPPORT +#include "vdm_hal_vp8.h" +#endif +#ifdef VFMW_VP9_SUPPORT +#include "vdm_hal_vp9.h" +#endif +#include "vfmw_intf.h" +#ifdef HIVDEC_SMMU_SUPPORT +#include "smmu.h" +#endif + +VDMHAL_HWMEM_S g_HwMem[MAX_VDH_NUM]; +VDMHAL_BACKUP_S g_VdmRegState; + +static VDMDRV_SLEEP_STAGE_E s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_NONE; +static VDMDRV_STATEMACHINE_E s_VdmState = VDM_IDLE_STATE; + +void VDMHAL_EnableInt(int VdhId) +{ + unsigned int D32 = 0xFFFFFFFE; + int *p32 = NULL; + + if (VdhId != 0) { + printk(KERN_ERR "VDH ID is wrong\n"); + return; + } + + if (g_HwMem[VdhId].pVdmRegVirAddr == NULL) { + p32 = (int *) MEM_Phy2Vir(gVdhRegBaseAddr); + if (p32 == NULL) { + printk(KERN_ERR "vdm register virtual address not mapped, reset failed\n"); + return; + } + + g_HwMem[VdhId].pVdmRegVirAddr = p32; + } + + WR_VREG(VREG_INT_MASK, D32, VdhId); + + return; +} + +int VDMHAL_CfgRpReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int D32 = 0; + + WR_VREG(VREG_AVM_ADDR, pVdhRegCfg->VdhAvmAddr, 0); + + D32 = 0x2000C203; + WR_VREG(VREG_BASIC_CFG1, D32, 0); + + D32 = 0x00300C03; + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + return VDMHAL_OK; +} + +void VDMHAL_IMP_Init(void) +{ + memset(g_HwMem, 0, sizeof(g_HwMem)); + memset(&g_VdmRegState, 0, sizeof(g_VdmRegState)); + + g_HwMem[0].pVdmRegVirAddr = (int *) MEM_Phy2Vir(gVdhRegBaseAddr); + + VDMHAL_IMP_GlbReset(); + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_NONE; + s_VdmState = VDM_IDLE_STATE; +} + +void VDMHAL_IMP_DeInit(void) +{ + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_NONE; + s_VdmState = VDM_IDLE_STATE; +} + +void VDMHAL_IMP_ResetVdm(int VdhId) +{ + int i; + int tmp = 0; + unsigned int reg; + unsigned int reg_rst_ok; + unsigned int *pVdmResetVirAddr; + unsigned int *pVdmResetOkVirAddr; + + pVdmResetVirAddr = (unsigned int *) MEM_Phy2Vir(gSOFTRST_REQ_Addr); + pVdmResetOkVirAddr = (unsigned int *) MEM_Phy2Vir(gSOFTRST_OK_ADDR); + + if ((pVdmResetVirAddr == NULL) + || (pVdmResetOkVirAddr == NULL) + || (g_HwMem[VdhId].pVdmRegVirAddr == NULL)) { + printk(KERN_ERR "map vdm register fail, vir(pVdmResetVirAddr) : (%pK), vir(pVdmResetOkVirAddr) : (%pK)\n", pVdmResetVirAddr, pVdmResetOkVirAddr); + return; + } + + RD_VREG(VREG_INT_MASK, tmp, VdhId); + + /* require mfde reset */ + reg = *(volatile unsigned int *)pVdmResetVirAddr; + *(volatile unsigned int *)pVdmResetVirAddr = reg | (unsigned int) (1 << MFDE_RESET_CTRL_BIT); + + /* wait for reset ok */ + for (i = 0; i < 100; i++) { + reg_rst_ok = *(volatile unsigned int *)pVdmResetOkVirAddr; + if (reg_rst_ok & (1 << MFDE_RESET_OK_BIT)) + break; + VFMW_OSAL_uDelay(10); + } + + if (i >= 100) + printk(KERN_ERR "%s reset failed\n", __func__); + + /* clear reset require */ + *(volatile unsigned int *)pVdmResetVirAddr = reg & (unsigned int) (~(1 << MFDE_RESET_CTRL_BIT)); + + + WR_VREG(VREG_INT_MASK, tmp, VdhId); + s_VdmState = VDM_IDLE_STATE; + + return; +} + +void VDMHAL_IMP_GlbReset(void) +{ + int i; + unsigned int reg, reg_rst_ok; + unsigned int *pResetVirAddr = NULL; + unsigned int *pResetOKVirAddr = NULL; + + pResetVirAddr = (unsigned int *) MEM_Phy2Vir(gSOFTRST_REQ_Addr); + pResetOKVirAddr = (unsigned int *) MEM_Phy2Vir(gSOFTRST_OK_ADDR); + + if (pResetVirAddr == NULL || pResetOKVirAddr == NULL) { + printk(KERN_ERR "VDMHAL_GlbReset: map vdm register fail, vir(pResetVirAddr) : (%pK), vir(pResetOKVirAddr) : (%pK)\n", pResetVirAddr, pResetOKVirAddr); + return; + } + + + /* require all reset, include mfde scd bpd */ + reg = *(volatile unsigned int *)pResetVirAddr; + *(volatile unsigned int *)pResetVirAddr = reg | (unsigned int) (1 << ALL_RESET_CTRL_BIT); + + /* wait for reset ok */ + for (i = 0; i < 100; i++) { + reg_rst_ok = *(volatile unsigned int *)pResetOKVirAddr; + if (reg_rst_ok & (1 << ALL_RESET_OK_BIT)) + break; + VFMW_OSAL_uDelay(10); + } + + if (i >= 100) + printk(KERN_ERR "Glb Reset Failed\n"); + + /* clear reset require */ + *(volatile unsigned int *)pResetVirAddr = reg & (unsigned int) (~(1 << ALL_RESET_CTRL_BIT)); + + + return; +} + +void VDMHAL_IMP_ClearIntState(int VdhId) +{ + int *p32; + unsigned int D32 = 0xFFFFFFFF; + + if (VdhId > (MAX_VDH_NUM - 1)) { + printk(KERN_ERR "%s: VdhId : %d is more than %d\n", __func__, VdhId, (MAX_VDH_NUM - 1)); + return; + } + + if (g_HwMem[VdhId].pVdmRegVirAddr == NULL) { + if ((p32 = (int *) MEM_Phy2Vir(gVdhRegBaseAddr)) != NULL) { + g_HwMem[VdhId].pVdmRegVirAddr = p32; + } else { + printk(KERN_ERR " %s %d vdm register virtual address not mapped, reset failed\n", __func__, __LINE__); + return; + } + } + + WR_VREG(VREG_INT_STATE, D32, VdhId); + + return; +} + +int VDMHAL_IMP_CheckReg(REG_ID_E reg_id, int VdhId) +{ + int *p32; + int dat = 0; + unsigned int reg_type; + + if (VdhId > (MAX_VDH_NUM - 1)) { + printk(KERN_ERR "%s: Invalid VdhId is %d\n", __func__, VdhId); + return VDMHAL_ERR; + } + + if (g_HwMem[VdhId].pVdmRegVirAddr == NULL) { + if ((p32 = (int *) MEM_Phy2Vir(gVdhRegBaseAddr)) != NULL) { + g_HwMem[VdhId].pVdmRegVirAddr = p32; + } else { + printk(KERN_ERR " %s %d vdm register virtual address not mapped, reset failed\n", __func__, __LINE__); + return 0; + } + } + + switch (reg_id) { + case VDH_STATE_REG: + reg_type = VREG_VDH_STATE; + break; + + case INT_STATE_REG: + reg_type = VREG_INT_STATE; + break; + + case INT_MASK_REG: + reg_type = VREG_INT_MASK; + break; + + case VCTRL_STATE_REG: + reg_type = VREG_VCTRL_STATE; + break; + + default: + printk(KERN_ERR "%s: unkown reg_id is %d\n", __func__, reg_id); + return 0; + } + + RD_VREG(reg_type, dat, 0); + return dat; +} + +int VDMHAL_IMP_PrepareDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + VDMHAL_HWMEM_S *pHwMem = &(g_HwMem[0]); + int *p32; + + if (NULL == pHwMem->pVdmRegVirAddr) + { + if (NULL != (p32 = (int *)MEM_Phy2Vir(gVdhRegBaseAddr))) + { + pHwMem->pVdmRegVirAddr = p32; + } + else + { + printk(KERN_ERR "vdm register virtual address not mapped, VDMHAL_PrepareDecfailed\n"); + return VDMHAL_ERR; + } + } + if (VFMW_AVS == pVdhRegCfg->VidStd) + WR_SCDREG(REG_AVS_FLAG, 0x00000001); + else + WR_SCDREG(REG_AVS_FLAG, 0x00000000); + + WR_SCDREG(REG_VDH_SELRST, 0x00000001); + + switch (pVdhRegCfg->VidStd) { +#ifdef VFMW_H264_SUPPORT + case VFMW_H264: + return H264HAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_HEVC_SUPPORT + case VFMW_HEVC: + return HEVCHAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_MPEG2_SUPPORT + case VFMW_MPEG2: + return MP2HAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_MPEG4_SUPPORT + case VFMW_MPEG4: + return MP4HAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_VP8_SUPPORT + case VFMW_VP8: + return VP8HAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_VP9_SUPPORT + case VFMW_VP9: + return VP9HAL_StartDec(pVdhRegCfg); +#endif +#ifdef VFMW_MVC_SUPPORT + case VFMW_MVC: + return H264HAL_StartDec(pVdhRegCfg); +#endif + default: + break; + } + + return VDMHAL_ERR; +} + +int VDMHAL_IsVdmRun(int VdhId) +{ + int Data32 = 0; + + if (g_HwMem[VdhId].pVdmRegVirAddr == NULL) { + printk(KERN_ERR "VDM register not mapped yet\n"); + return 0; + } + + RD_VREG(VREG_VCTRL_STATE, Data32, VdhId); + + return (Data32 == 1 ? 0 : 1); +} + +int VDMHAL_IMP_BackupInfo(void) +{ + int i = 0; + int regTmp; + g_VdmRegState.Int_State_Reg = VDMHAL_IMP_CheckReg(INT_STATE_REG, 0); + + RD_VREG(VREG_BASIC_CFG1, g_VdmRegState.BasicCfg1, 0); + RD_VREG(VREG_VDH_STATE, g_VdmRegState.VdmState, 0); + + RD_VREG(VREG_MB0_QP_IN_CURR_PIC, g_VdmRegState.Mb0QpInCurrPic, 0); + RD_VREG(VREG_SWITCH_ROUNDING, g_VdmRegState.SwitchRounding, 0); + + { + RD_VREG(VREG_SED_STA, g_VdmRegState.SedSta, 0); + RD_VREG(VREG_SED_END0, g_VdmRegState.SedEnd0, 0); + RD_VREG(VREG_DEC_CYCLEPERPIC, g_VdmRegState.DecCyclePerPic, 0); + RD_VREG(VREG_RD_BDWIDTH_PERPIC, g_VdmRegState.RdBdwidthPerPic, 0); + RD_VREG(VREG_WR_BDWIDTH_PERPIC, g_VdmRegState.WrBdWidthPerPic, 0); + RD_VREG(VREG_RD_REQ_PERPIC, g_VdmRegState.RdReqPerPic, 0); + RD_VREG(VREG_WR_REQ_PERPIC, g_VdmRegState.WrReqPerPic, 0); + RD_VREG(VREG_LUMA_SUM_LOW, g_VdmRegState.LumaSumLow, 0); + RD_VREG(VREG_LUMA_SUM_HIGH, g_VdmRegState.LumaSumHigh, 0); + } + for (i = 0; i < 32; i++) { + regTmp = VREG_LUMA_HISTORGRAM + i * 4; + RD_VREG(regTmp, g_VdmRegState.LumaHistorgam[i], 0); + } + + return VDMHAL_OK; +} + +void VDMHAL_GetRegState(VDMHAL_BACKUP_S *pVdmRegState) +{ + memcpy(pVdmRegState, &g_VdmRegState, sizeof(*pVdmRegState)); + s_VdmState = VDM_IDLE_STATE; +} + +int VDMHAL_IMP_PrepareRepair(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + VDMHAL_HWMEM_S *pHwMem = &(g_HwMem[0]); + int *p32; + int ret; + + if (NULL == pVdhRegCfg) + { + printk(KERN_ERR "%s: parameter is NULL\n", __func__); + return VDMHAL_ERR; + } + if ( NULL == pHwMem->pVdmRegVirAddr ) + { + if ( NULL != (p32 = (int *)MEM_Phy2Vir(gVdhRegBaseAddr)) ) + { + pHwMem->pVdmRegVirAddr = p32; + } + else + { + printk(KERN_ERR "vdm register virtual address not mapped, VDMHAL_PrepareRepair failed\n"); + return VDMHAL_ERR; + } + } + if (pVdhRegCfg->RepairTime == FIRST_REPAIR) { + if (pVdhRegCfg->ValidGroupNum0 > 0) + ret = VDMHAL_CfgRpReg(pVdhRegCfg); + else + ret = VDMHAL_ERR; + } else if (pVdhRegCfg->RepairTime == SECOND_REPAIR) { + printk(KERN_ERR "SECOND_REPAIR Parameter Error\n"); + ret = VDMHAL_ERR; + } else { + printk(KERN_ERR " parameter error\n"); + ret = VDMHAL_ERR; + } + + return ret; +} + +void VDMHAL_IMP_StartHwRepair(int VdhId) +{ + int D32 = 0; + + RD_VREG(VREG_BASIC_CFG0, D32, VdhId); + + D32 = 0x4000000; + WR_VREG(VREG_BASIC_CFG0, D32, VdhId); + +#ifdef HIVDEC_SMMU_SUPPORT + SMMU_SetMasterReg(MFDE, SECURE_OFF, SMMU_ON); +#endif + + VDMHAL_IMP_ClearIntState(VdhId); + VDMHAL_EnableInt(VdhId); + + VFMW_OSAL_Mb(); + WR_VREG(VREG_VDH_START, 0, VdhId); + WR_VREG(VREG_VDH_START, 1, VdhId); + WR_VREG(VREG_VDH_START, 0, VdhId); + + return; +} + +void VDMHAL_IMP_StartHwDecode(int VdhId) +{ + +#ifdef HIVDEC_SMMU_SUPPORT + SMMU_SetMasterReg(MFDE, SECURE_OFF, SMMU_ON); +#endif + + VDMHAL_IMP_ClearIntState(VdhId); + VDMHAL_EnableInt(VdhId); + + VFMW_OSAL_Mb(); + WR_VREG(VREG_VDH_START, 0, 0); + WR_VREG(VREG_VDH_START, 1, 0); + WR_VREG(VREG_VDH_START, 0, 0); + + return; +} + +void VDMHAL_ISR(int VdhId) +{ + VDMHAL_IMP_BackupInfo(); + VDMHAL_IMP_ClearIntState(VdhId); + VFMW_OSAL_GiveEvent(G_VDMHWDONEEVENT); +} + +int VDMHAL_HwDecProc(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int ret = VDMDRV_ERR; + + s_VdmState = VDM_DECODE_STATE; + + if (pVdhRegCfg->VdhStartHwDecFlag == 1) { + ret = VDMHAL_IMP_PrepareDec(pVdhRegCfg); + if (ret == VDMDRV_OK) { + VDMHAL_IMP_StartHwDecode(0); + } else { + ret = VDMDRV_ERR; + printk(KERN_ERR "%s prepare dec fail \n", __func__); + } + } else if (pVdhRegCfg->VdhStartRepairFlag == 1) { + ret = VDMHAL_IMP_PrepareRepair(pVdhRegCfg); + if (ret == VDMDRV_OK) { + VDMHAL_IMP_StartHwRepair(0); + } else { + ret = VDMDRV_ERR; + printk(KERN_ERR "%s prepare repair fail \n", __func__); + } + } else { + ret = VDMDRV_ERR; + printk(KERN_ERR "%s process type error \n", __func__); + } + + if (ret != VDMDRV_OK) { + s_VdmState = VDM_IDLE_STATE; + } + return ret; +} + +int VDMHAL_PrepareSleep(void) +{ + int ret = VDMDRV_OK; + + VFMW_OSAL_SemaDown(G_VDH_SEM); + if (s_eVdmDrvSleepState == VDMDRV_SLEEP_STAGE_NONE) { + if (VDM_IDLE_STATE == s_VdmState) { + printk(KERN_INFO "%s, idle state \n", __func__); + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_SLEEP; + } else { + printk(KERN_INFO "%s, work state \n", __func__); + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_PREPARE; + } + + ret = VDMDRV_OK; + } else { + ret = VDMDRV_ERR; + } + + VFMW_OSAL_SemaUp(G_VDH_SEM); + return ret; +} + +void VDMHAL_ForceSleep(void) +{ + printk(KERN_INFO "%s, force state \n", __func__); + VFMW_OSAL_SemaDown(G_VDH_SEM); + if (s_eVdmDrvSleepState != VDMDRV_SLEEP_STAGE_SLEEP) { + VDMHAL_IMP_ResetVdm(0); + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_SLEEP; + } + + VFMW_OSAL_SemaUp(G_VDH_SEM); +} + +void VDMHAL_ExitSleep(void) +{ + VFMW_OSAL_SemaDown(G_VDH_SEM); + s_eVdmDrvSleepState = VDMDRV_SLEEP_STAGE_NONE; + VFMW_OSAL_SemaUp(G_VDH_SEM); +} + +VDMDRV_SLEEP_STAGE_E VDMHAL_GetSleepStage(void) +{ + return s_eVdmDrvSleepState; +} + +void VDMHAL_SetSleepStage(VDMDRV_SLEEP_STAGE_E sleepState) +{ + VFMW_OSAL_SemaDown(G_VDH_SEM); + s_eVdmDrvSleepState = sleepState; + VFMW_OSAL_SemaUp(G_VDH_SEM); +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.h new file mode 100755 index 000000000000..1070b6d94968 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal.h @@ -0,0 +1,85 @@ +#ifndef _VDM_HAL_HEADER_ +#define _VDM_HAL_HEADER_ + +#include "vdm_drv.h" +#include +#include "../../omxvdec/omxvdec.h" + +#define VDMHAL_OK (0) +#define VDMHAL_ERR (-1) + +#define MAX_SLICE_SLOT_NUM (200) + +#define FIRST_REPAIR (0) +#define SECOND_REPAIR (1) + +#define MAX_IMG_WIDTH_IN_MB (512) +#define MAX_IMG_HALF_HEIGHT_IN_MB (256) +#define MAX_IMG_HEIGHT_IN_MB (MAX_IMG_HALF_HEIGHT_IN_MB * 2) +#define MAX_MB_NUM_IN_PIC (MAX_IMG_WIDTH_IN_MB * MAX_IMG_HEIGHT_IN_MB) + +#define MAX_SLOT_WIDTH (4096) +#define MAX_STRIDE ((1024 * MAX_SLOT_WIDTH / 64 + ((1024) - 1)) & (~ ((1024) - 1))) +/************************************************************************/ +/* Register read/write interface */ +/************************************************************************/ +/* mfde register read/write */ +#if 1 +#define RD_VREG( reg, dat, VdhId ) \ +do { \ + if (VdhId < MAX_VDH_NUM) \ + dat = readl(((volatile int*)((char*)g_HwMem[VdhId].pVdmRegVirAddr + reg))); \ + else \ + dprint(PRN_ALWS,"%s: RD_VREG but VdhId : %d is more than MAX_VDH_NUM : %d\n", __func__, VdhId, MAX_VDH_NUM); \ +} while(0) + +#define WR_VREG( reg, dat, VdhId ) \ +do { \ + if (VdhId < MAX_VDH_NUM) \ + writel((dat), ((volatile int*)((char*)g_HwMem[VdhId].pVdmRegVirAddr + reg))); \ + else \ + dprint(PRN_ALWS,"%s: WR_VREG but VdhId : %d is more than MAX_VDH_NUM : %d\n", __func__, VdhId, MAX_VDH_NUM); \ +} while(0) +#else // xy test +#define RD_VREG( reg, dat, VdhId ) \ +do { \ + if (VdhId < MAX_VDH_NUM) { \ + printk(KERN_INFO "%s: RD_VREG \n", __func__ ); \ + dat = *((volatile int*)((char*)g_HwMem[VdhId].pVdmRegVirAddr + reg)); \ + } \ + else \ + printk(KERN_INFO "%s: RD_VREG but VdhId : %d is more than MAX_VDH_NUM : %d\n", __func__, VdhId, MAX_VDH_NUM); \ +} while(0) + +#define WR_VREG( reg, dat, VdhId ) \ +do { \ + if (VdhId < MAX_VDH_NUM) \ + (*(volatile int*)((char*)g_HwMem[VdhId].pVdmRegVirAddr + reg)) = dat; \ + else \ + printk(KERN_INFO "%s: WR_VREG but VdhId : %d is more than MAX_VDH_NUM : %d\n", __func__, VdhId, MAX_VDH_NUM); \ +} while(0) +#endif + +#if 0 +/* message pool read/write */ +#define RD_MSGWORD( vir_addr, dat ) \ +do { \ + dat = *((volatile int*)(vir_addr)); \ +} while(0) + +#define WR_MSGWORD( vir_addr, dat ) \ +do { \ + *((volatile int*)((char*)(vir_addr))) = dat; \ +} while(0) + +/* condition check */ +#define VDMHAL_ASSERT_RET( cond, else_print ) \ +do { \ + if (!(cond)) { \ + printk(KERN_ERR "%s %d: %s\n", __func__, __LINE__, else_print ); \ + return VDMHAL_ERR; \ + } \ +} while(0) +#endif + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_api.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_api.h new file mode 100755 index 000000000000..7bc35e27c113 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_api.h @@ -0,0 +1,31 @@ +#ifndef _VDM_HAL_API_HEADER_ +#define _VDM_HAL_API_HEADER_ + +#include "mem_manage.h" +#include "vfmw.h" +#include "vdm_hal_local.h" +#include "vfmw_intf.h" + +void VDMHAL_IMP_ResetVdm(int VdhId); +void VDMHAL_IMP_GlbReset(void); +void VDMHAL_IMP_ClearIntState(int VdhId); +int VDMHAL_IMP_CheckReg(REG_ID_E reg_id, int VdhId); +void VDMHAL_IMP_StartHwRepair(int VdhId); +void VDMHAL_IMP_StartHwDecode(int VdhId); +int VDMHAL_IMP_PrepareDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +int VDMHAL_IMP_PrepareRepair(OMXVDH_REG_CFG_S *pVdhRegCfg); +int VDMHAL_IMP_BackupInfo(void); +void VDMHAL_IMP_GetCharacter(void); +void VDMHAL_IMP_WriteScdEMARID(void); +void VDMHAL_IMP_Init(void); +void VDMHAL_IMP_DeInit(void); +void VDMHAL_ISR(int VdhId); +int VDMHAL_HwDecProc(OMXVDH_REG_CFG_S *pVdhRegCfg); +void VDMHAL_GetRegState(VDMHAL_BACKUP_S *pVdmRegState); +int VDMHAL_IsVdmRun(int VdhId); +int VDMHAL_PrepareSleep(void); +void VDMHAL_ForceSleep(void); +void VDMHAL_ExitSleep(void); +VDMDRV_SLEEP_STAGE_E VDMHAL_GetSleepStage(void); +void VDMHAL_SetSleepStage(VDMDRV_SLEEP_STAGE_E sleepState); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.c new file mode 100755 index 000000000000..11e44098fd30 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.c @@ -0,0 +1,107 @@ +/* + * vdec hal for h264 + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#include "vfmw.h" +#include "mem_manage.h" +//#include "public.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_h264.h" + +#include +int H264HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + unsigned int D32; + + D32 = 0; + ((BASIC_CFG0 *)(&D32))->mbamt_to_dec = ((BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->mbamt_to_dec; + ((BASIC_CFG0 *)(&D32))->load_qmatrix_flag = 1; + ((BASIC_CFG0 *)(&D32))->marker_bit_detect_en = 0; + ((BASIC_CFG0 *)(&D32))->ac_last_detect_en = 0; + ((BASIC_CFG0 *)(&D32))->coef_idx_detect_en = 1; + ((BASIC_CFG0 *)(&D32))->vop_type_detect_en = 0; + ((BASIC_CFG0 *)(&D32))->sec_mode_en = 0; + WR_VREG(VREG_BASIC_CFG0, D32, 0); + + D32 = 0; + ((BASIC_CFG1 *)(&D32))->video_standard = 0x0; + //((BASIC_CFG1 *)(&D32))->ddr_stride = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->ddr_stride; + ((BASIC_CFG1 *)(&D32))->fst_slc_grp = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->fst_slc_grp; + ((BASIC_CFG1 *)(&D32))->mv_output_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->mv_output_en; + ((BASIC_CFG1 *)(&D32))->uv_order_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->uv_order_en; + ((BASIC_CFG1 *)(&D32))->vdh_2d_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->vdh_2d_en; + ((BASIC_CFG1 *)(&D32))->max_slcgrp_num = 2; + ((BASIC_CFG1 *)(&D32))->compress_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->compress_en; + ((BASIC_CFG1 *)(&D32))->ppfd_en = 0; + ((BASIC_CFG1 *)(&D32))->line_num_output_en = 0; + WR_VREG(VREG_BASIC_CFG1, D32, 0); + + D32 = 0; + ((AVM_ADDR *)(&D32))->av_msg_addr = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; + WR_VREG(VREG_AVM_ADDR, D32, 0); + + D32 = 0; + ((VAM_ADDR *)(&D32))->va_msg_addr = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; + WR_VREG(VREG_VAM_ADDR, D32, 0); + + D32 = 0; + ((STREAM_BASE_ADDR *)(&D32))->stream_base_addr = (pVdhRegCfg->VdhStreamBaseAddr) & 0xFFFFFFF0; + WR_VREG(VREG_STREAM_BASE_ADDR, D32, 0); + + D32 = RD_SCDREG(REG_EMAR_ID); + if (pVdhRegCfg->VdhEmarId == 0) { + D32 = D32 & (~(0x100)); + } else { + D32 = D32 | 0x100; + } + WR_SCDREG(REG_EMAR_ID, D32); + + D32 = 0x00300C03; + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + D32 = 0; + ((YSTADDR_1D *)(&D32))->ystaddr_1d = (pVdhRegCfg->VdhYstAddr) & 0xFFFFFFF0; + WR_VREG(VREG_YSTADDR_1D, D32, 0); + + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + D32 = 0; + WR_VREG(VREG_HEAD_INF_OFFSET, D32, 0); + + WR_VREG(VREG_REF_PIC_TYPE, pVdhRegCfg->VdhRefPicType, 0); + + if (pVdhRegCfg->VdhFfAptEn == 0x2) { + D32 = 0x2; + } else { + D32 = 0x0; + } + WR_VREG(VREG_FF_APT_EN, D32, 0); + + //UVSTRIDE_1D + WR_VREG( VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0 ); + + //CFGINFO_ADDR + WR_VREG(VREG_CFGINFO_ADDR, pVdhRegCfg->VdhCfgInfoAddr, 0); + + //DDR_INTERLEAVE_MODE + D32 = 0x03; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + + return VDMHAL_OK; +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.h new file mode 100755 index 000000000000..d8b8312119dd --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_h264.h @@ -0,0 +1,8 @@ +#ifndef __VDM_HAL_H264_H__ +#define __VDM_HAL_H264_H__ + +#include "mem_manage.h" +//#include "memory.h" +#include "vfmw_intf.h" +int H264HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.c new file mode 100755 index 000000000000..4f89a50663fb --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.c @@ -0,0 +1,119 @@ +/* + * vdec hal for hevc + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#include "vfmw.h" +#include "mem_manage.h" +//#include "public.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_hevc.h" +#include +static int HEVCHAL_CfgVdmReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + unsigned int D32; + + //BASIC_CFG0 + D32 = 0; + ((HEVC_BASIC_CFG0 *)(&D32))->marker_bit_detect_en = 0; + ((HEVC_BASIC_CFG0 *)(&D32))->ac_last_detect_en = 0; + ((HEVC_BASIC_CFG0 *)(&D32))->coef_idx_detect_en = 1; //(run_cnt>64) check enable switch + ((HEVC_BASIC_CFG0 *)(&D32))->vop_type_detect_en = 0; + ((HEVC_BASIC_CFG0 *)(&D32))->load_qmatrix_flag = ((HEVC_BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->load_qmatrix_flag; + ((HEVC_BASIC_CFG0 *)(&D32))->luma_sum_en = 0; //enable switch:conculate luma pixel + ((HEVC_BASIC_CFG0 *)(&D32))->luma_histogram_en = 0; //enable switch:conculate luma histogram + ((HEVC_BASIC_CFG0 *)(&D32))->mbamt_to_dec = ((HEVC_BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->mbamt_to_dec; + ((HEVC_BASIC_CFG0*)(&D32))->vdh_safe_flag = 0; + WR_VREG( VREG_BASIC_CFG0, D32, 0 ); + + //BASIC_CFG1 + /*set uv order 0: v first; 1: u first */ + D32 = 0; + ((HEVC_BASIC_CFG1 *)(&D32))->video_standard = 0xD; + ((HEVC_BASIC_CFG1 *)(&D32))->fst_slc_grp = ((HEVC_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->fst_slc_grp; + ((HEVC_BASIC_CFG1 *)(&D32))->mv_output_en = 1; + ((HEVC_BASIC_CFG1 *)(&D32))->uv_order_en = ((HEVC_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->uv_order_en; + ((HEVC_BASIC_CFG1 *)(&D32))->vdh_2d_en = ((HEVC_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->vdh_2d_en; + ((HEVC_BASIC_CFG1 *)(&D32))->max_slcgrp_num = 3; + ((HEVC_BASIC_CFG1 *)(&D32))->line_num_output_en = 0; //enable switch:output "decodered pixel line of current frame" to DDR + ((HEVC_BASIC_CFG1 *)(&D32))->frm_cmp_en = ((HEVC_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->frm_cmp_en; + ((HEVC_BASIC_CFG1 *)(&D32))->ppfd_en = 0; + WR_VREG( VREG_BASIC_CFG1, D32, 0 ); + + //AVM_ADDR + D32 = 0; + ((AVM_ADDR *)(&D32))->av_msg_addr = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; + WR_VREG(VREG_AVM_ADDR, D32, 0); + + //VAM_ADDR + D32 = 0; + ((VAM_ADDR *)(&D32))->va_msg_addr = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; + WR_VREG(VREG_VAM_ADDR, D32, 0); + + //STREAM_BASE_ADDR + D32 = 0; + ((STREAM_BASE_ADDR *)(&D32))->stream_base_addr = (pVdhRegCfg->VdhStreamBaseAddr) & 0xFFFFFFF0; + WR_VREG(VREG_STREAM_BASE_ADDR, D32, 0); + + //TIME_OUT + D32 = 0x00300C03; //Õâ¸öÖµÅäÖà l00214825 + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + WR_VREG(VREG_YSTADDR_1D, pVdhRegCfg->VdhYstAddr, 0); + + //YSTRIDE_1D + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + + //UVOFFSET_1D + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + //HEAD_INF_OFFSET + D32 = 0; + WR_VREG(VREG_HEAD_INF_OFFSET, D32, 0); //don't match with document l00214825 + + //UVSTRIDE_1D + WR_VREG( VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0 ); + + //CFGINFO_ADDR + WR_VREG(VREG_CFGINFO_ADDR, pVdhRegCfg->VdhCfgInfoAddr, 0); + + //DDR_INTERLEAVE_MODE + D32 = 0x03; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + + //FF_APT_EN + D32 = 0x2; + WR_VREG(VREG_FF_APT_EN, D32, 0); + + //EMAR_ADDR + D32 = 0x101; + WR_SCDREG(REG_EMAR_ID, D32); + + return VDMHAL_OK; +} + +int HEVCHAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int Ret; + + Ret = HEVCHAL_CfgVdmReg(pVdhRegCfg); + if (Ret != VDMHAL_OK) { + printk(KERN_ERR "HEVC register config failed\n"); + return VDMHAL_ERR; + } + + return VDMHAL_OK; +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.h new file mode 100755 index 000000000000..fba7e5654227 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_hevc.h @@ -0,0 +1,9 @@ +#ifndef __VDM_HAL__HEVC_H__ +#define __VDM_HAL__HEVC_H__ + +#include "mem_manage.h" +//#include "memory.h" +#include "vfmw_intf.h" + +int HEVCHAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_local.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_local.h new file mode 100755 index 000000000000..eb9f0a7b692c --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_local.h @@ -0,0 +1,283 @@ + +#ifndef _VDM_HAL_LOCAL_HEADER_ +#define _VDM_HAL_LOCAL_HEADER_ + +#include "mem_manage.h" +#include "vfmw.h" +#include "vdm_hal.h" + +#define VHB_STRIDE_BYTE (0x400) // byte stride +#define HW_MEM_SIZE (640 * 1024 + 64 * 4) +#define HW_HEVC_MEM_SIZE (2 * 1024 * 1024 + 64 * 4) //(4*1024*1024 + 100*1024) + +#define MSG_SLOT_NUM (MAX_SLICE_SLOT_NUM + 5 + 1) +#define UP_MSG_SLOT_INDEX (0) +#define RP_MSG_SLOT_INDEX (2) +#define DN_MSG_HEAD_SLOT_INDEX (4) +#define DN_MSG_SLOT_INDEX (5) +#define CA_HEVC_MN_ADDR_LEN (1024) +#define CA_MN_ADDR_LEN (64 * 4 * 20) +#define SED_TOP_ADDR_LEN (352 * 96) //(64*4*96) +#define PMV_TOP_ADDR_LEN (352 * 128) //(64*4*96) +#define RCN_TOP_ADDR_LEN (352 * 128) //(64*4*96) +#define ITRANS_TOP_ADDR_LEN (352 * 128) //(128*128) +#define DBLK_TOP_ADDR_LEN (352 * 192) //(128*512) +#define PPFD_BUF_LEN_DEFAULT (64 * 4 * 400) //(64*4*800) + +#define INTENSITY_CONV_TAB_ADDR_LEN (256 * 2 * 2 * 3) +#define VP8_TAB_ADDR_LEN (32 * 1024) +#define VP6_TAB_ADDR_LEN (4 * 1024) +#define MAX_REF_FRAME_NUM (16) + +/********************************************************* + for hevc +**********************************************************/ +#ifdef VFMW_HEVC_SUPPORT + +/*** UHD decode memory define ***/ +#define CFG_HEVC_PROFILE_LEVEL_5 +#define CFG_HEVC_MAX_PIX_HEIGHT (2304) + +#if defined (CFG_HEVC_PROFILE_LEVEL_5) +#define HEVC_PROFILE_LEVEL_5 +#else +#define HEVC_PROFILE_LEVEL_6 +#endif + +#if defined (HEVC_PROFILE_LEVEL_5) +#define HEVC_MAX_SLICE_NUM (200) +#else +#define HEVC_MAX_SLICE_NUM (600) +#endif + +#if !defined (CFG_HEVC_MAX_PIX_WIDTH) +#define HEVC_MAX_PIX_WIDTH (4096) +#else +#define HEVC_MAX_PIX_WIDTH (CFG_HEVC_MAX_PIX_WIDTH) +#endif + +// 3798MV100 logic support tile num is 20x22 +#if !defined (CFG_HEVC_MAX_PIX_HEIGHT) +#define HEVC_MAX_PIX_HEIGHT (4096) +#else +#define HEVC_MAX_PIX_HEIGHT (CFG_HEVC_MAX_PIX_HEIGHT) +#endif + + +#define HEVC_SED_TOP_ADDR_LEN (64*4*HEVC_MAX_PIX_WIDTH) +#define HEVC_PMV_TOP_ADDR_LEN (64*4*HEVC_MAX_PIX_WIDTH) +#define HEVC_PMV_LEFT_ADDR_LEN (64*4*HEVC_MAX_PIX_HEIGHT) +#define HEVC_RCN_TOP_ADDR_LEN (64*4*HEVC_MAX_PIX_WIDTH) +#define HEVC_TILE_SEGMENT_INFO_LEN (2048) //(512*2+20*4+22*4=1192, 1024????) z00290437 20141024 +#define HEVC_SAO_LEFT_ADDR_LEN (64*4*HEVC_MAX_PIX_HEIGHT) +#define HEVC_DBLK_LEFT_ADDR_LEN (64*4*HEVC_MAX_PIX_HEIGHT) +#define HEVC_SAO_TOP_ADDR_LEN (64*4*HEVC_MAX_PIX_WIDTH) +#define HEVC_DBLK_TOP_ADDR_LEN (64*4*HEVC_MAX_PIX_WIDTH) +/*********************** MSG SLOT PARA DEFINE *********************/ +#define HEVC_MAX_SLOT_NUM (HEVC_MAX_SLICE_NUM+5) //z00290437 20141025 +#ifdef VFMW_VP9_SUPPORT +#define VP9_MAX_PIC_WIDTH 8192 +#define VP9_MAX_PIC_HEIGHT 8192 + +//============================== VP9 ============================= +#define VP9_SED_TOP_ADDR_LEN (64*4*VP9_MAX_PIC_WIDTH) +#define VP9_PMV_TOP_ADDR_LEN (64*4*VP9_MAX_PIC_WIDTH) +#define VP9_RCN_TOP_ADDR_LEN (64*4*VP9_MAX_PIC_WIDTH) +#define VP9_DBLK_TOP_ADDR_LEN (64*4*VP9_MAX_PIC_WIDTH) +#define VP9_DBLK_LEFT_ADDR_LEN (VP9_MAX_PIC_HEIGHT * 8) + +#ifndef VP9_NEW_PROB +#define VP9_PROB_TAB_ADDR_LEN (20 * 64 * 4)//(18 * 64 * 4) +#define VP9_PROB_CNT_ADDR_LEN (VP9_MAX_PIC_WIDTH * 4) /* 3301 is enought */ +#else +#define VP9_PROB_TAB_ADDR_LEN (20*64*4) +#define VP9_PROB_CNT_ADDR_LEN (20*64*4) +#endif // modified by j00367396@20160923 +#endif + +#endif + + +//control registers +#define VREG_VDH_START 0x000 +#define VREG_BASIC_CFG0 0x008 +#define VREG_BASIC_CFG1 0x00c +#define VREG_AVM_ADDR 0x010 +#define VREG_VAM_ADDR 0x014 +#define VREG_STREAM_BASE_ADDR 0x018 +//state registers +#define VREG_VDH_STATE 0x01c +#define VREG_VCTRL_STATE 0x028 +//0x0001FF00: all RAM OnChip +//0x0002FF00: all RAM OnChip, except DBLK RAM +#define VREG_SED_TO 0x03c +#define VREG_ITRANS_TO 0x040 +#define VREG_PMV_TO 0x044 +#define VREG_PRC_TO 0x048 +#define VREG_RCN_TO 0x04c +#define VREG_DBLK_TO 0x050 +#define VREG_PPFD_TO 0x054 +#define VREG_PART_DEC_OVER_INT_LEVEL 0x05c +//1d registers +#define VREG_YSTADDR_1D 0x060 +#define VREG_YSTRIDE_1D 0x064 +#define VREG_UVOFFSET_1D 0x068 +//prc registers +#define VREG_HEAD_INF_OFFSET 0x06c +//ppfd registers +#define VREG_PPFD_BUF_ADDR 0x080 +#define VREG_PPFD_BUF_LEN 0x084 +#define VREG_REF_PIC_TYPE 0x094 +#define VREG_FF_APT_EN 0x098 + +//mask & clear +#define VREG_SAFE_INT_STATE 0x0a8 +#define VREG_SAFE_INT_MASK 0x0aC +#define VREG_NORM_INT_STATE 0x020 +#define VREG_NORM_INT_MASK 0x024 + +#define VREG_INT_STATE VREG_NORM_INT_STATE +#define VREG_INT_MASK VREG_NORM_INT_MASK + +#define VREG_UVSTRIDE_1D 0x0c4 +#define VREG_CFGINFO_ADDR 0x0C8 +#define VREG_DDR_INTERLEAVE_MODE 0x0F4 +//clock div offset +#define PERI_CRG_CORE_DIV 0xCC +#define PERI_CRG_AXI_DIV 0xD0 + +//performance count registers +#define VREG_DEC_CYCLEPERPIC 0x0B0 +#define VREG_RD_BDWIDTH_PERPIC 0x0B4 +#define VREG_WR_BDWIDTH_PERPIC 0x0B8 +#define VREG_RD_REQ_PERPIC 0x0BC +#define VREG_WR_REQ_PERPIC 0x0C0 +#define VREG_MB0_QP_IN_CURR_PIC 0x0D0 +#define VREG_SWITCH_ROUNDING 0x0D4 +//sed registers +#define VREG_SED_STA 0x1000 +#define VREG_SED_END0 0x1014 +#define VREG_LUMA_HISTORGRAM 0x8100 +#define VREG_LUMA_SUM_LOW 0x8180 +#define VREG_LUMA_SUM_HIGH 0x8184 + +typedef struct { + unsigned int mbamt_to_dec :20; + unsigned int memory_clock_gating_en :1; + unsigned int module_clock_gating_en :1; + unsigned int marker_bit_detect_en :1; + unsigned int ac_last_detect_en :1; + unsigned int coef_idx_detect_en :1; + unsigned int vop_type_detect_en :1; + unsigned int reserved :2; + unsigned int luma_sum_en :1; + unsigned int luma_historgam_en :1; + unsigned int load_qmatrix_flag :1; + unsigned int sec_mode_en :1; +} BASIC_CFG0; + +typedef struct { + unsigned int mbamt_to_dec :20; + unsigned int memory_clock_gating_en :1; + unsigned int module_clock_gating_en :1; + unsigned int marker_bit_detect_en :1; + unsigned int ac_last_detect_en :1; + unsigned int coef_idx_detect_en :1; + unsigned int vop_type_detect_en :1; + unsigned int work_mode :2; + unsigned int luma_sum_en :1; + unsigned int luma_histogram_en :1; + unsigned int load_qmatrix_flag :1; + unsigned int vdh_safe_flag :1; +} HEVC_BASIC_CFG0; + +typedef struct { + unsigned int video_standard :4; + unsigned int reserved: 9; + unsigned int uv_order_en :1; + unsigned int fst_slc_grp :1; + unsigned int mv_output_en :1; + unsigned int max_slcgrp_num :12; + unsigned int line_num_output_en :1; + unsigned int vdh_2d_en :1; + unsigned int compress_en :1; + unsigned int ppfd_en :1; +} BASIC_CFG1; + +typedef struct { + unsigned int video_standard :4; + unsigned int reserved :9; + unsigned int uv_order_en :1; + unsigned int fst_slc_grp :1; + unsigned int mv_output_en :1; + unsigned int max_slcgrp_num :12; + unsigned int line_num_output_en :1; + unsigned int vdh_2d_en :1; + unsigned int frm_cmp_en :1; + unsigned int ppfd_en :1; +} HEVC_BASIC_CFG1; + +typedef struct { + unsigned int video_standard: 4; + unsigned int reserved: 9; + unsigned int uv_order_en: 1; //l00214825 0624 + unsigned int fst_slc_grp: 1; + unsigned int mv_output_en: 1; + unsigned int max_slcgrp_num: 12; + unsigned int line_num_output_en: 1; + unsigned int vdh_2d_en: 1; + unsigned int frm_cmp_en: 1; + unsigned int ppfd_en: 1; +} VP9_BASIC_CFG1; + +typedef struct { + unsigned int av_msg_addr :32; +} AVM_ADDR; + +typedef struct { + unsigned int va_msg_addr :32; +} VAM_ADDR; + +typedef struct { + unsigned int stream_base_addr :32; +} STREAM_BASE_ADDR; + +typedef struct { + unsigned int ystaddr_1d :32; +} YSTADDR_1D; + +typedef struct { + unsigned int ff_apt_en :1; + unsigned int reserved :31; +} FF_APT_EN; + +typedef struct { + unsigned int ref_pic_type_0 :2; + unsigned int ref_pic_type_1 :2; + unsigned int ref_pic_type_2 :2; + unsigned int ref_pic_type_3 :2; + unsigned int ref_pic_type_4 :2; + unsigned int ref_pic_type_5 :2; + unsigned int ref_pic_type_6 :2; + unsigned int ref_pic_type_7 :2; + + unsigned int ref_pic_type_8 :2; + unsigned int ref_pic_type_9 :2; + unsigned int ref_pic_type_10 :2; + unsigned int ref_pic_type_11 :2; + unsigned int ref_pic_type_12 :2; + unsigned int ref_pic_type_13 :2; + unsigned int ref_pic_type_14 :2; + unsigned int ref_pic_type_15 :2; +} REF_PIC_TYPE; + +typedef struct { + unsigned int ppfd_buf_addr :32; +} PPFD_BUF_ADDR; + +typedef struct { + unsigned int ppfd_buf_len :16; + unsigned int reserved :16; +} PPFD_BUF_LEN; + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.c new file mode 100755 index 000000000000..52f102c7c61c --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.c @@ -0,0 +1,105 @@ +/* + * vdec hal for mp2 + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#ifndef __VDM_HAL_MPEG2_C__ +#define __VDM_HAL_MPEG2_C__ + +#include "public.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_mpeg2.h" +#include + +static int MP2HAL_CfgReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int D32; + D32 = 0; + ((BASIC_CFG0 *)(&D32))->mbamt_to_dec = ((BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->mbamt_to_dec; + ((BASIC_CFG0 *)(&D32))->load_qmatrix_flag = 1; + ((BASIC_CFG0 *)(&D32))->marker_bit_detect_en = 1; + ((BASIC_CFG0 *)(&D32))->ac_last_detect_en = 0; + ((BASIC_CFG0 *)(&D32))->coef_idx_detect_en = 1; + ((BASIC_CFG0 *)(&D32))->vop_type_detect_en = 0; + ((BASIC_CFG0 *)(&D32))->sec_mode_en = 0; + WR_VREG( VREG_BASIC_CFG0, D32, 0 ); + + D32 = 0; + ((BASIC_CFG1 *)(&D32))->video_standard = 0x3; + //((BASIC_CFG1 *)(&D32))->ddr_stride = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->ddr_stride; + ((BASIC_CFG1 *)(&D32))->fst_slc_grp = 1; + ((BASIC_CFG1 *)(&D32))->mv_output_en = 1; + ((BASIC_CFG1 *)(&D32))->uv_order_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->uv_order_en; + ((BASIC_CFG1 *)(&D32))->vdh_2d_en = 1; + ((BASIC_CFG1 *)(&D32))->max_slcgrp_num = 3; + ((BASIC_CFG1 *)(&D32))->ppfd_en = 0; + ((BASIC_CFG1 *)(&D32))->line_num_output_en = 0; + ((BASIC_CFG1 *)(&D32))->compress_en = 0; + /*set uv order 0: v first; 1: u first */ + WR_VREG( VREG_BASIC_CFG1, D32, 0 ); + + D32 = 0; + ((AVM_ADDR *)(&D32))->av_msg_addr = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; + WR_VREG(VREG_AVM_ADDR, D32, 0); + + D32 = 0; + ((VAM_ADDR *)(&D32))->va_msg_addr = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; + WR_VREG(VREG_VAM_ADDR, D32, 0); + + WR_VREG(VREG_STREAM_BASE_ADDR, pVdhRegCfg->VdhStreamBaseAddr, 0); + + //EMAR_ADDR + D32 = 0x101; + WR_SCDREG(REG_EMAR_ID, D32); + + //TIME_OUT + D32 = 0x00300C03; + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + D32 = 0; + ((YSTADDR_1D *)(&D32))->ystaddr_1d = (pVdhRegCfg->VdhYstAddr) & 0xFFFFFFF0; + WR_VREG(VREG_YSTADDR_1D, D32, 0); + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + D32 = 0; + ((REF_PIC_TYPE *)(&D32))->ref_pic_type_0 = ((REF_PIC_TYPE *)(&pVdhRegCfg->VdhRefPicType))->ref_pic_type_0; + ((REF_PIC_TYPE *)(&D32))->ref_pic_type_1 = ((REF_PIC_TYPE *)(&pVdhRegCfg->VdhRefPicType))->ref_pic_type_1; + WR_VREG( VREG_REF_PIC_TYPE, D32, 0 ); + D32 = 0; + ((FF_APT_EN *)(&D32))->ff_apt_en = 0;//USE_FF_APT_EN; + WR_VREG( VREG_FF_APT_EN, D32, 0 ); + + //VREG_UVSTRIDE_1D + WR_VREG( VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0 ); + + //DDR_INTERLEAVE_MODE + D32 = 0x03; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + + return VDMHAL_OK; +} + +int MP2HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + if (MP2HAL_CfgReg(pVdhRegCfg) != VDMHAL_OK) { + printk(KERN_ERR "MP2 register config failed\n"); + return VDMHAL_ERR; + } + + return VDMHAL_OK; +} +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.h new file mode 100755 index 000000000000..3dcbb01fb21e --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg2.h @@ -0,0 +1,8 @@ +#ifndef __VDM_HAL_MPEG2_H__ +#define __VDM_HAL_MPEG2_H__ + +//#include "memory.h" +#include "vfmw_intf.h" + +int MP2HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.c new file mode 100755 index 000000000000..538261fa674d --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.c @@ -0,0 +1,110 @@ +/* + * vdec hal for mp4 + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#include "vfmw.h" +#include "mem_manage.h" +//#include "public.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_mpeg4.h" +#include + +static int MP4HAL_CfgReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + unsigned int D32; + int SlotWidth; + + //BASIC_CFG0 + D32 = 0; + D32 = (pVdhRegCfg->VdhBasicCfg0 & 0x000FFFFF) // [15:0] mbamt_to_dec + | ( 1 << 22 ) + | ( 0 << 23 ) + | ( 0 << 24 ) + | ( 1 << 25 ) + | ( 1 << 30 ) // ld_qmatrix_flag + | ( 0 << 31 ); // Normal Mode + WR_VREG( VREG_BASIC_CFG0, D32, 0); + + /*set uv order 0: v first; 1: u first */ + D32 = 0x2 // [3:0] video_standard + | (((pVdhRegCfg->VdhBasicCfg1 >> 13) & 0x1) << 13 ) // uv_order_en + | ( 1 << 14 ) // [14] fst_slc_grp + | ( 1 << 15 ) // [15] mv_output_en + | ( 1 << 16 ) // [27:16] max_slcgrp_num + | ( 0 << 28 ) // line_num_output_en + | ( 1 << 29 ) // vdh_2d_en //l00214825 0710 + | ( 0 << 30 ) //compress_en + | ( 0 << 31 ); // [31] ppfd_en 0==not ppfd dec + WR_VREG(VREG_BASIC_CFG1, D32, 0); + + D32 = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; // mpeg4 down msg + WR_VREG(VREG_AVM_ADDR, D32, 0); + + D32 = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; // mpeg4 up msg + WR_VREG(VREG_VAM_ADDR, D32, 0); + + WR_VREG(VREG_STREAM_BASE_ADDR, pVdhRegCfg->VdhStreamBaseAddr, 0); + + //EMAR_ADDR + D32 = 0x101; + + SlotWidth = pVdhRegCfg->VdhYstride / 8; + if (SlotWidth > 1920) + { + D32 = D32 & (~(0x100)); + } + else + { + D32 = D32 | (0x100); + } + + WR_SCDREG(REG_EMAR_ID, D32); + + D32 = 0x00300C03; + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + D32 = (pVdhRegCfg->VdhYstAddr) & 0xFFFFFFF0; + WR_VREG(VREG_YSTADDR_1D, D32, 0); + + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + D32 = 0; + WR_VREG(VREG_FF_APT_EN, D32, 0); + + WR_VREG( VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0 ); + + D32 = 0x03; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + + return VDMHAL_OK; +} + + +int MP4HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int ret; + + ret = MP4HAL_CfgReg(pVdhRegCfg); + if (ret != VDMHAL_OK) { + printk(KERN_ERR "MP4 register config failed\n"); + return VDMHAL_ERR; + } + + return VDMHAL_OK; +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.h new file mode 100755 index 000000000000..435e04f8cf5d --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_mpeg4.h @@ -0,0 +1,9 @@ +#ifndef _VDM_HAL_MPEG4_HEADER_ +#define _VDM_HAL_MPEG4_HEADER_ + +#include "mem_manage.h" +//#include "memory.h" +#include "vfmw_intf.h" + +int MP4HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.c new file mode 100755 index 000000000000..64ef67d34cdc --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.c @@ -0,0 +1,100 @@ +/* + * vdec hal for vp8 + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#ifndef __VDM_HAL_VP8_C__ +#define __VDM_HAL_VP8_C__ + +//#include "public.h" +#include "vdm_hal.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_vp8.h" +#include + +static int VP8HAL_CfgReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + unsigned int D32; + + //BASIC_CFG0 + D32 = 0; + ((BASIC_CFG0 *)(&D32))->mbamt_to_dec = ((BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->mbamt_to_dec; + ((BASIC_CFG0 *)(&D32))->load_qmatrix_flag = 0; + ((BASIC_CFG0 *)(&D32))->sec_mode_en = 0; + WR_VREG( VREG_BASIC_CFG0, D32, 0); + + //BASIC_CFG1 + /*set uv order 0: v first; 1: u first */ + D32 = 0x20000000; + ((BASIC_CFG1 *)(&D32))->video_standard = 0x0C; + //((BASIC_CFG1 *)(&D32))->ddr_stride = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->ddr_stride; + ((BASIC_CFG1 *)(&D32))->fst_slc_grp = 1; + ((BASIC_CFG1 *)(&D32))->mv_output_en = 1; + ((BASIC_CFG1 *)(&D32))->uv_order_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->uv_order_en; + ((BASIC_CFG1 *)(&D32))->vdh_2d_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->vdh_2d_en; + ((BASIC_CFG1 *)(&D32))->max_slcgrp_num = 0; + ((BASIC_CFG1 *)(&D32))->compress_en = ((BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->compress_en; + ((BASIC_CFG1 *)(&D32))->ppfd_en = 0; + WR_VREG( VREG_BASIC_CFG1, D32, 0); + + //AVM_ADDR + D32 = 0; + ((AVM_ADDR *)(&D32))->av_msg_addr = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; + WR_VREG(VREG_AVM_ADDR, D32, 0); + + //VAM_ADDR + D32 = 0; + ((VAM_ADDR *)(&D32))->va_msg_addr = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; + WR_VREG(VREG_VAM_ADDR, D32, 0); + + //STREAM_BASE_ADDR + WR_VREG(VREG_STREAM_BASE_ADDR, pVdhRegCfg->VdhStreamBaseAddr, 0); + + //EMAR_ADDR + D32 = 0x101; + WR_SCDREG(REG_EMAR_ID, D32); + + //YSTADDR_1D + D32 = 0; + ((YSTADDR_1D *)(&D32))->ystaddr_1d = (pVdhRegCfg->VdhYstAddr) & 0xFFFFFFF0; //caution + WR_VREG(VREG_YSTADDR_1D, D32, 0); + + //YSTRIDE_1D + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + + //UVOFFSET_1D + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + D32 = 0; + WR_VREG(VREG_HEAD_INF_OFFSET, D32, 0); + + WR_VREG( VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0 ); + + WR_VREG(VREG_CFGINFO_ADDR, pVdhRegCfg->VdhCfgInfoAddr, 0); + + D32 = 0x03; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + return VDMHAL_OK; +} + +int VP8HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int Ret; + + Ret = VP8HAL_CfgReg(pVdhRegCfg); + if (Ret != VDMHAL_OK) { + printk(KERN_ERR "VP8 register config failed\n"); + return VDMHAL_ERR; + } + + return VDMHAL_OK; +} + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.h new file mode 100755 index 000000000000..30f5e8756765 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp8.h @@ -0,0 +1,9 @@ +#ifndef __VDM_HAL_VP8_HERAER__ +#define __VDM_HAL_VP8_HERAER__ + +//#include "memory.h" +#include "vfmw_intf.h" + +int VP8HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif + diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.c new file mode 100755 index 000000000000..0730d10650a3 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.c @@ -0,0 +1,140 @@ +/*-----------------------------------------------------------------------*/ +/*!!Warning: Huawei key information asset. No spread without permission. */ +/*CODEMARK:EG4uRhTwMmgcVFBsBnYHCDadN5jJKSuVyxmmaCmKFU6eJEbB2fyHF9weu4/jer/hxLHb+S1e +E0zVg4C3NiZh4Rryzsvo1gOdvy7M+qFCBFQKTTAFAVC3Q4e533WXdeQrddo4r2cqTmRg3Xeb +SI3trXaSV012ETxvJrJ/pkfs27/lT6wemL9iW3PaGW8//pmW7hQ7qCDBgWp7sMvcMuyYAWRh +jMb6+4xlgVl55z+iUl5XDCi0pMRG2hXB2hXZd5i/HJastZrWJFR4dVOatPlImg==#*/ +/*--!!Warning: Deleting or modifying the preceding information is prohibited.--*/ + + + +/****************************************************************************** + + °æȨËùÓÐ (C), 2001-2015, »ªÎª¼¼ÊõÓÐÏÞ¹«Ë¾ + +****************************************************************************** + ÎÄ ¼þ Ãû : vdm_hal_vp9.c + °æ ±¾ ºÅ : ³õ¸å + ×÷ Õß : z00290437 + Éú³ÉÈÕÆÚ: 2015-02-03 + ×î½üÐÞ¸Ä : + ¹¦ÄÜÃèÊö : VDMV300 Ó²¼þ³éÏó + + ÐÞ¸ÄÀúÊ· : + 1.ÈÕ ÆÚ : + 2.×÷ Õß : + 3.ÐÞ¸ÄÄÚÈÝ: + +******************************************************************************/ + +#ifndef __VDM_HAL_VP9_C__ +#define __VDM_HAL_VP9_C__ + +//#include "public.h" +#include "vdm_hal.h" +#include "vdm_hal_api.h" +#include "vdm_hal_local.h" +#include "vdm_hal_vp9.h" +#include + +static int VP9HAL_CfgReg(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + unsigned int D32; + + //BASIC_CFG0 + D32 = 0; + ((BASIC_CFG0*)(&D32))->mbamt_to_dec = ((BASIC_CFG0 *)(&pVdhRegCfg->VdhBasicCfg0))->mbamt_to_dec; + ((BASIC_CFG0*)(&D32))->load_qmatrix_flag = 0; + //((BASIC_CFG0*)(&D32))->repair_en = 0; + + WR_VREG(VREG_BASIC_CFG0, D32, 0); + + //BASIC_CFG1 + D32 = 0; + ((VP9_BASIC_CFG1*)(&D32))->video_standard = 0x0E; //VFMW_VP9; + // ((VP9_BASIC_CFG1*)(&D32))->ddr_stride = pVp9DecParam->ddr_stride >> 6; + ((VP9_BASIC_CFG1*)(&D32))->uv_order_en = ((VP9_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->uv_order_en; + ((VP9_BASIC_CFG1*)(&D32))->fst_slc_grp = 1; + ((VP9_BASIC_CFG1*)(&D32))->mv_output_en = 1; + ((VP9_BASIC_CFG1*)(&D32))->max_slcgrp_num = 3; + ((VP9_BASIC_CFG1*)(&D32))->line_num_output_en = 0; + // ((BASIC_CFG1*)(&D32))->compress_en = pVp9DecParam->Compress_en; + ((VP9_BASIC_CFG1*)(&D32))->vdh_2d_en = ((VP9_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->vdh_2d_en; ////1; by j00367396 + ((VP9_BASIC_CFG1*)(&D32))->frm_cmp_en = ((VP9_BASIC_CFG1 *)(&pVdhRegCfg->VdhBasicCfg1))->frm_cmp_en; //for tmp linear + ((VP9_BASIC_CFG1*)(&D32))->ppfd_en = 0; + + WR_VREG(VREG_BASIC_CFG1, D32, 0); + + //AVM_ADDR + D32 = 0; + ((AVM_ADDR*)(&D32))->av_msg_addr = (pVdhRegCfg->VdhAvmAddr) & 0xFFFFFFF0; + WR_VREG(VREG_AVM_ADDR, D32, 0); + + //VAM_ADDR + D32 = 0; + ((VAM_ADDR*)(&D32))->va_msg_addr = (pVdhRegCfg->VdhVamAddr) & 0xFFFFFFF0; + WR_VREG(VREG_VAM_ADDR, D32, 0); + + //STREAM_BASE_ADDR + WR_VREG(VREG_STREAM_BASE_ADDR, pVdhRegCfg->VdhStreamBaseAddr, 0); + + //PRC_CACHE_TYPE + D32 = 0x0; + WR_VREG(VREG_FF_APT_EN, D32, 0); + + //EMAR_ADDR + D32 = 0x101; + WR_SCDREG(REG_EMAR_ID, D32); + + //TIME_OUT + D32 = 0x00300C03; + WR_VREG(VREG_SED_TO, D32, 0); + WR_VREG(VREG_ITRANS_TO, D32, 0); + WR_VREG(VREG_PMV_TO, D32, 0); + WR_VREG(VREG_PRC_TO, D32, 0); + WR_VREG(VREG_RCN_TO, D32, 0); + WR_VREG(VREG_DBLK_TO, D32, 0); + WR_VREG(VREG_PPFD_TO, D32, 0); + + //DEC_OVER_INT_LEVEL + D32 = 60; + WR_VREG(VREG_PART_DEC_OVER_INT_LEVEL, D32, 0); + + //YSTADDR_1D + D32 = 0; + ((YSTADDR_1D *)(&D32))->ystaddr_1d = (pVdhRegCfg->VdhYstAddr) & 0xFFFFFFF0; + WR_VREG(VREG_YSTADDR_1D, D32, 0); + + //YSTRIDE_1D + WR_VREG(VREG_YSTRIDE_1D, pVdhRegCfg->VdhYstride, 0); + + //UVOFFSET_1D + WR_VREG(VREG_UVOFFSET_1D, pVdhRegCfg->VdhUvoffset, 0); + + //UVSTRIDE_1D + WR_VREG(VREG_UVSTRIDE_1D, pVdhRegCfg->VdhUvstride, 0); + + //CFGINFO_ADDR + WR_VREG(VREG_CFGINFO_ADDR, pVdhRegCfg->VdhCfgInfoAddr, 0); + + //DDR_INTERLEAVE_MODE + D32 = 0x3; + WR_VREG(VREG_DDR_INTERLEAVE_MODE, D32, 0); + + return VDMHAL_OK; +} + +int VP9HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg) +{ + int Ret; + + Ret = VP9HAL_CfgReg(pVdhRegCfg); + if (Ret != VDMHAL_OK) { + printk(KERN_ERR "VP9 register config failed\n"); + return VDMHAL_ERR; + } + + return VDMHAL_OK; +} + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.h new file mode 100755 index 000000000000..a26466985ae4 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/format/vdm_hal_vp9.h @@ -0,0 +1,9 @@ + +#ifndef __VDM_HAL_VP9_H__ +#define __VDM_HAL_VP9_H__ + +//#include "memory.h" +#include "vfmw_intf.h" + +int VP9HAL_StartDec(OMXVDH_REG_CFG_S *pVdhRegCfg); +#endif //__VDM_HAL_AVS_H__ diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.c new file mode 100755 index 000000000000..8a209c844e47 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.c @@ -0,0 +1,408 @@ +/* + * osal + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ + +//#include "public.h" +#include "linux_kernel_osal.h" + +#ifdef ENV_ARMLINUX_KERNEL + +/* SpinLock */ +OSAL_IRQ_SPIN_LOCK g_SpinLock_SCD; +OSAL_IRQ_SPIN_LOCK g_SpinLock_VDH; +OSAL_IRQ_SPIN_LOCK g_SpinLock_Record; + +/* Mutext */ +OSAL_TASK_MUTEX g_IntEvent; + +OSAL_TASK_MUTEX g_ScdHwDoneEvent; +OSAL_TASK_MUTEX g_VdmHwDoneEvent; + +/* Semaphore */ +OSAL_SEMA g_SCDSem; +OSAL_SEMA g_VDHSem; +OSAL_SEMA g_BPDSem; + +/* Extern */ +extern Vfmw_Osal_Func_Ptr g_vfmw_osal_fun_ptr; + +#define OSAL_Print printk +#define MAX_WAIT_EVENT_CNT 100 +#define TIME_PERIOD(begin, end) ((end >= begin) ? (end - begin) : (0xffffffff - begin + end)) + +unsigned int OSAL_GetTimeInMs(void) +{ + unsigned long long SysTime; + + SysTime = sched_clock(); + do_div(SysTime, 1000000); + + return (unsigned int) SysTime; +} + +unsigned int OSAL_GetTimeInUs(void) +{ + unsigned long long SysTime; + + SysTime = sched_clock(); + do_div(SysTime, 1000); + + return (unsigned int) SysTime; +} + +static inline int OSAL_InitEvent(OSAL_EVENT *pEvent, int InitVal) +{ + pEvent->flag = InitVal; + init_waitqueue_head(&(pEvent->queue_head)); + return OSAL_OK; +} + +static inline int OSAL_GiveEvent(OSAL_EVENT *pEvent) +{ + pEvent->flag = 1; + wake_up_interruptible(&(pEvent->queue_head)); + + return OSAL_OK; +} + +static inline int OSAL_WaitEvent(OSAL_EVENT *pEvent, int msWaitTime) +{ + int ret; + unsigned int cnt = 0; + + unsigned int start_time, cur_time; + start_time = VFMW_OSAL_GetTimeInMs(); + + do { + ret = wait_event_interruptible_timeout((pEvent->queue_head), (pEvent->flag != 0), (msecs_to_jiffies(msWaitTime)));/*lint !e666*/ + if (ret < 0) { + cur_time = VFMW_OSAL_GetTimeInMs(); + if (TIME_PERIOD(start_time, cur_time) > (unsigned int)msWaitTime) { + printk(KERN_CRIT "wait event time out, time : %d, cnt: %d\n", TIME_PERIOD(start_time, cur_time), cnt); + ret = 0; + break; + } + } + cnt++; + } while ((pEvent->flag == 0) && (ret < 0)); + + if (cnt > MAX_WAIT_EVENT_CNT) { + printk(KERN_CRIT "the max cnt of wait_event interrupts by singal is %d\n", cnt); + } + + if (ret == 0) { + printk(KERN_CRIT "wait pEvent signal timeout\n"); + } + + pEvent->flag = 0; //(pEvent->flag>0)? (pEvent->flag-1): 0; + + return (ret != 0) ? OSAL_OK : OSAL_ERR; +} + +unsigned char *OSAL_RegisterMap(unsigned int PhyAddr, unsigned int Size) +{ + return (unsigned char *) ioremap_nocache(PhyAddr, Size); +} + +void OSAL_RegisterUnMap(unsigned char *VirAddr, unsigned int Size) +{ + iounmap(VirAddr); + return; +} + +int OSAL_FileWrite(char *buf, int len, struct file *filp) +{ + int writelen; + mm_segment_t oldfs; + + if (filp == NULL) + return -ENOENT; + + if (filp->f_op->write == NULL) + return -ENOSYS; + + if (((filp->f_flags & O_ACCMODE) & (O_WRONLY | O_RDWR)) == 0) + return -EACCES; + + oldfs = get_fs(); + set_fs(KERNEL_DS);/*lint !e501*/ + writelen = filp->f_op->write(filp, buf, len, &filp->f_pos); + set_fs(oldfs); + + return writelen; +} + +static inline void OSAL_SEMA_INTIT(OSAL_SEMA *pSem) +{ + sema_init(pSem, 1); +} + +static inline int OSAL_DOWN_INTERRUPTIBLE(OSAL_SEMA *pSem) +{ + return down_interruptible(pSem); +} + +static inline void OSAL_UP(OSAL_SEMA *pSem) +{ + up(pSem); +} + +static inline void OSAL_SpinLockIRQInit(OSAL_IRQ_SPIN_LOCK *pIntrMutex) +{ + spin_lock_init(&pIntrMutex->irq_lock); + pIntrMutex->isInit = 1; +} + +static inline int OSAL_SpinLockIRQ(OSAL_IRQ_SPIN_LOCK *pIntrMutex) +{ + if (pIntrMutex->isInit == 0) { + spin_lock_init(&pIntrMutex->irq_lock); + pIntrMutex->isInit = 1; + } + spin_lock_irqsave(&pIntrMutex->irq_lock, pIntrMutex->irq_lockflags); + + return OSAL_OK; +} + +static inline int OSAL_SpinUnLockIRQ(OSAL_IRQ_SPIN_LOCK *pIntrMutex) +{ + spin_unlock_irqrestore(&pIntrMutex->irq_lock, pIntrMutex->irq_lockflags); + + return OSAL_OK; +} + +void OSAL_Mb(void) +{ + mb(); +} + +void OSAL_uDelay(unsigned long usecs) +{ + udelay(usecs); +} + +void OSAL_mSleep(unsigned int msecs) +{ + msleep(msecs); +} + +int OSAL_RequestIrq(unsigned int irq, OSAL_IRQ_HANDLER_t handler, unsigned long flags, const char *name, void *dev) +{ + return request_irq(irq, (irq_handler_t) handler, flags, name, dev); +} + +void OSAL_FreeIrq(unsigned int irq, void *dev) +{ + free_irq(irq, dev); +} + +void *OSAL_AllocVirMem(int Size) +{ + return vmalloc(Size); +} + +void OSAL_FreeVirMem(void *p) +{ + if (p) + vfree(p); +} + +OSAL_IRQ_SPIN_LOCK *GetSpinLockByEnum(SpinLockType LockType) +{ + OSAL_IRQ_SPIN_LOCK *pSpinLock = NULL; + + switch (LockType) { + case G_SPINLOCK_SCD: + pSpinLock = &g_SpinLock_SCD; + break; + + case G_SPINLOCK_RECORD: + pSpinLock = &g_SpinLock_Record; + break; + + case G_SPINLOCK_VDH: + pSpinLock = &g_SpinLock_VDH; + break; + + default: + printk(KERN_ERR "%s unkown SpinLockType %d\n", __func__, LockType); + break; + } + + return pSpinLock; +} + +void OSAL_SpinLockInit(SpinLockType LockType) +{ + OSAL_IRQ_SPIN_LOCK *pSpinLock = NULL; + + pSpinLock = GetSpinLockByEnum(LockType); + + OSAL_SpinLockIRQInit(pSpinLock); +} + +int OSAL_SpinLock(SpinLockType LockType) +{ + OSAL_IRQ_SPIN_LOCK *pSpinLock = NULL; + + pSpinLock = GetSpinLockByEnum(LockType); + + return OSAL_SpinLockIRQ(pSpinLock); +} + +int OSAL_SpinUnLock(SpinLockType LockType) +{ + OSAL_IRQ_SPIN_LOCK *pSpinLock = NULL; + + pSpinLock = GetSpinLockByEnum(LockType); + + return OSAL_SpinUnLockIRQ(pSpinLock); +} + +OSAL_SEMA *GetSemByEnum(SemType Sem) +{ + OSAL_SEMA *pSem = NULL; + + switch (Sem) { + case G_SCD_SEM: + pSem = &g_SCDSem; + break; + + case G_VDH_SEM: + pSem = &g_VDHSem; + break; + + case G_BPD_SEM: + pSem = &g_BPDSem; + break; + + default: + printk(KERN_ERR "%s unkown SemType %d\n", __func__, Sem); + break; + } + + return pSem; +} + +void OSAL_SemInit(SemType Sem) +{ + OSAL_SEMA *pSem = NULL; + + pSem = GetSemByEnum(Sem); + + OSAL_SEMA_INTIT(pSem); +} + +int OSAL_SemDown(SemType Sem) +{ + OSAL_SEMA *pSem = NULL; + + pSem = GetSemByEnum(Sem); + + return OSAL_DOWN_INTERRUPTIBLE(pSem); +} + +void OSAL_SemUp(SemType Sem) +{ + OSAL_SEMA *pSem = NULL; + + pSem = GetSemByEnum(Sem); + + OSAL_UP(pSem); +} + +int OSAL_InitWaitQue(MutexType mutextType, int initVal) +{ + int retVal = OSAL_ERR; + + switch (mutextType) { + case G_SCDHWDONEEVENT: + retVal = OSAL_InitEvent(&g_ScdHwDoneEvent, initVal); + break; + + case G_VDMHWDONEEVENT: + retVal = OSAL_InitEvent(&g_VdmHwDoneEvent, initVal); + break; + + default: + break; + } + return retVal; +} + +int OSAL_WakeupWaitQue(MutexType mutexType) +{ + int retVal = OSAL_ERR; + + switch (mutexType) { + case G_SCDHWDONEEVENT: + retVal = OSAL_GiveEvent(&g_ScdHwDoneEvent); + break; + + case G_VDMHWDONEEVENT: + retVal = OSAL_GiveEvent(&g_VdmHwDoneEvent); + break; + + default: + break; + } + + return retVal; +} + +int OSAL_WaitWaitQue(MutexType mutexType, int waitTimeInMs) +{ + int retVal = OSAL_ERR; + + switch (mutexType) { + case G_SCDHWDONEEVENT: + retVal = OSAL_WaitEvent(&g_ScdHwDoneEvent, waitTimeInMs); + break; + + case G_VDMHWDONEEVENT: + retVal = OSAL_WaitEvent(&g_VdmHwDoneEvent, waitTimeInMs); + break; + + default: + break; + } + + return retVal; +} + +void OSAL_InitInterface(void) +{ + memset(&g_vfmw_osal_fun_ptr, 0, sizeof(g_vfmw_osal_fun_ptr)); + + g_vfmw_osal_fun_ptr.pfun_Osal_GetTimeInMs = OSAL_GetTimeInMs; + g_vfmw_osal_fun_ptr.pfun_Osal_GetTimeInUs = OSAL_GetTimeInUs; + g_vfmw_osal_fun_ptr.pfun_Osal_SpinLockInit = OSAL_SpinLockInit; + g_vfmw_osal_fun_ptr.pfun_Osal_SpinLock = OSAL_SpinLock; + g_vfmw_osal_fun_ptr.pfun_Osal_SpinUnLock = OSAL_SpinUnLock; + g_vfmw_osal_fun_ptr.pfun_Osal_SemaInit = OSAL_SemInit; + g_vfmw_osal_fun_ptr.pfun_Osal_SemaDown = OSAL_SemDown; + g_vfmw_osal_fun_ptr.pfun_Osal_SemaUp = OSAL_SemUp; + g_vfmw_osal_fun_ptr.pfun_Osal_Print = OSAL_Print; + g_vfmw_osal_fun_ptr.pfun_Osal_mSleep = OSAL_mSleep; + g_vfmw_osal_fun_ptr.pfun_Osal_Mb = OSAL_Mb; + g_vfmw_osal_fun_ptr.pfun_Osal_uDelay = OSAL_uDelay; + g_vfmw_osal_fun_ptr.pfun_Osal_InitEvent = OSAL_InitWaitQue; + g_vfmw_osal_fun_ptr.pfun_Osal_GiveEvent = OSAL_WakeupWaitQue; + g_vfmw_osal_fun_ptr.pfun_Osal_WaitEvent = OSAL_WaitWaitQue; + g_vfmw_osal_fun_ptr.pfun_Osal_RequestIrq = OSAL_RequestIrq; + g_vfmw_osal_fun_ptr.pfun_Osal_FreeIrq = OSAL_FreeIrq; + g_vfmw_osal_fun_ptr.pfun_Osal_RegisterMap = OSAL_RegisterMap; + g_vfmw_osal_fun_ptr.pfun_Osal_RegisterUnMap = OSAL_RegisterUnMap; + g_vfmw_osal_fun_ptr.pfun_Osal_AllocVirMem = OSAL_AllocVirMem; + g_vfmw_osal_fun_ptr.pfun_Osal_FreeVirMem = OSAL_FreeVirMem; +} + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.h new file mode 100755 index 000000000000..bd5b7c40e1e6 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/linux_kernel_osal.h @@ -0,0 +1,84 @@ + +#ifndef __VFMW_LINUX_KERNEL_OSAL_HEADER__ +#define __VFMW_LINUX_KERNEL_OSAL_HEADER__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vfmw_osal_ext.h" + +/*======================================================================*/ +/* struct define */ +/*======================================================================*/ +typedef struct hiKERN_EVENT_S { + wait_queue_head_t queue_head; + int flag; +} OSAL_EVENT; + +typedef struct hiKERN_IRQ_LOCK_S { + spinlock_t irq_lock; + unsigned long irq_lockflags; + int isInit; +} OSAL_IRQ_SPIN_LOCK; + +/*======================================================================*/ +/* define */ +/*======================================================================*/ +typedef struct task_struct* OSAL_TASK; +typedef struct file OSAL_FILE; +typedef struct semaphore OSAL_SEMA; +typedef OSAL_EVENT OSAL_TASK_MUTEX; + + +/*======================================================================*/ +/* function declare */ +/*======================================================================*/ + +/************************************************************************/ +/* time: get in ms/us */ +/************************************************************************/ +unsigned int OSAL_GetTimeInMs(void); +unsigned int OSAL_GetTimeInUs(void); + +/************************************************************************/ +/* file: open/close/read/write */ +/************************************************************************/ +int OSAL_FileWrite(char *buf, int len, struct file *filp); + +/************************************************************************/ +/* linux kernel osal function pointer initialize */ +/************************************************************************/ +void OSAL_InitInterface(void); + +#endif + + diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.c new file mode 100755 index 000000000000..ce931c7a9b05 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.c @@ -0,0 +1,180 @@ +/* + * vdec mem_manager + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#include "mem_manage.h" +#include "sysconfig.h" +#include "vfmw_osal_ext.h" +//#include "public.h" +#include "linux_kernel_osal.h" + +#define MAX_MEM_MAN_RECORD_NUM (MAX_CHAN_NUM*32) +MEM_RECORD_S s_MemRecord[MAX_MEM_MAN_RECORD_NUM]; + +void MEM_InitMemManager(void) +{ + VFMW_OSAL_SpinLock(G_SPINLOCK_RECORD); + + memset(s_MemRecord, 0, sizeof(s_MemRecord)); + + VFMW_OSAL_SpinUnLock(G_SPINLOCK_RECORD); + +} + +int MEM_AddMemRecord(unsigned int PhyAddr, void *VirAddr, unsigned int Length) +{ + int i; + char IsErrorFlag = 0; + int TargetPos = -1; + int ret = MEM_MAN_ERR; + + VFMW_OSAL_SpinLock(G_SPINLOCK_RECORD); + + for (i = 0; i < MAX_MEM_MAN_RECORD_NUM; i++) { + if ((s_MemRecord[i].PhyAddr <= PhyAddr) && (PhyAddr < s_MemRecord[i].PhyAddr + s_MemRecord[i].Length)) { + IsErrorFlag = 1; + break; + } + + if (s_MemRecord[i].Length == 0 && TargetPos == -1) + TargetPos = i; + } + + if (IsErrorFlag == 1) { + printk(KERN_CRIT "%s conflict occured\n ", __func__); + ret = MEM_MAN_ERR; + } else if (TargetPos == -1) { + printk(KERN_CRIT "%s no free record slot\n ", __func__); + ret = MEM_MAN_ERR; + } else { + s_MemRecord[TargetPos].PhyAddr = PhyAddr; + s_MemRecord[TargetPos].VirAddr = VirAddr; + s_MemRecord[TargetPos].Length = Length; + ret = MEM_MAN_OK; + } + + VFMW_OSAL_SpinUnLock(G_SPINLOCK_RECORD); + + return ret; +} + +int MEM_DelMemRecord(unsigned int PhyAddr, void *VirAddr, unsigned int Length) +{ + int i; + + VFMW_OSAL_SpinLock(G_SPINLOCK_RECORD); + for (i = 0; i < MAX_MEM_MAN_RECORD_NUM; i++) { + if (s_MemRecord[i].Length == 0) + continue; + + if (PhyAddr == s_MemRecord[i].PhyAddr && VirAddr == s_MemRecord[i].VirAddr && + Length == s_MemRecord[i].Length) { + s_MemRecord[i].Length = 0; + s_MemRecord[i].PhyAddr = 0; + s_MemRecord[i].VirAddr = 0; + VFMW_OSAL_SpinUnLock(G_SPINLOCK_RECORD); + + return MEM_MAN_OK; + } + } + VFMW_OSAL_SpinUnLock(G_SPINLOCK_RECORD); + + return MEM_MAN_ERR; +} + +void *MEM_Phy2Vir(unsigned int PhyAddr) +{ + unsigned int i; + unsigned char *VirAddr = NULL; + + for (i = 0; i < MAX_MEM_MAN_RECORD_NUM; i++) { + if (s_MemRecord[i].Length == 0) + continue; + + if ((PhyAddr >= s_MemRecord[i].PhyAddr) && (PhyAddr < s_MemRecord[i].PhyAddr + s_MemRecord[i].Length)) { + VirAddr = s_MemRecord[i].VirAddr + (PhyAddr - s_MemRecord[i].PhyAddr); + break; + } + } + + return (void *) VirAddr; +} + +unsigned int MEM_Vir2Phy(unsigned char *VirAddr) +{ + unsigned int i; + + unsigned int PhyAddr = 0; + for (i = 0; i < MAX_MEM_MAN_RECORD_NUM; i++) { + if (s_MemRecord[i].Length == 0) + continue; + + if ((VirAddr >= s_MemRecord[i].VirAddr) && (VirAddr < s_MemRecord[i].VirAddr + s_MemRecord[i].Length)) { + PhyAddr = s_MemRecord[i].PhyAddr + (VirAddr - s_MemRecord[i].VirAddr); + break; + } + } + + return PhyAddr; +} + +void MEM_WritePhyWord(unsigned int PhyAddr, unsigned int Data32) +{ + unsigned int *pDst; + + pDst = (unsigned int *) MEM_Phy2Vir(PhyAddr); + if (pDst != NULL) + writel(Data32, pDst); +} + +unsigned int MEM_ReadPhyWord(unsigned int PhyAddr) +{ + unsigned int *pDst; + unsigned int Data32; + + Data32 = 0; + pDst = (unsigned int *) MEM_Phy2Vir(PhyAddr); + if (pDst != NULL) { + Data32 = readl((volatile unsigned int *)pDst); + } + + return Data32; +} + +int MEM_MapRegisterAddr(unsigned int RegStartPhyAddr, unsigned int RegByteLen, MEM_RECORD_S *pMemRecord) +{ + unsigned char *ptr; + + if (pMemRecord == NULL || RegStartPhyAddr == 0 || RegByteLen == 0 || VFMW_OSAL_RegisterMap == NULL) + return MEM_MAN_ERR; + + memset(pMemRecord, 0, sizeof(*pMemRecord)); + + ptr = VFMW_OSAL_RegisterMap(RegStartPhyAddr, RegByteLen); + + if (ptr != NULL) { + pMemRecord->PhyAddr = RegStartPhyAddr; + pMemRecord->VirAddr = ptr; + pMemRecord->Length = RegByteLen; + return MEM_MAN_OK; + } + + return MEM_MAN_ERR; +} + +void MEM_UnmapRegisterAddr(unsigned int PhyAddr, unsigned char *VirAddr, unsigned int Size) +{ + if (PhyAddr == 0 || VirAddr == 0 || VFMW_OSAL_RegisterUnMap == NULL) + return; + + VFMW_OSAL_RegisterUnMap(VirAddr, Size); + + return; +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.h new file mode 100755 index 000000000000..256c79265469 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/mem_manage.h @@ -0,0 +1,34 @@ +#ifndef _VFMW_MEM_MANAGE_HEAD_ +#define _VFMW_MEM_MANAGE_HEAD_ + +#include "vfmw.h" + +#define MEM_MAN_ERR -1 +#define MEM_MAN_OK 0 + +typedef struct { + unsigned int PhyAddr; + unsigned int Length; + int IsSecMem; + unsigned char *VirAddr; +} MEM_RECORD_S; + +void MEM_InitMemManager(void); + +int MEM_AddMemRecord(unsigned int PhyAddr, void *VirAddr, unsigned int Length); + +int MEM_DelMemRecord(unsigned int PhyAddr, void *VirAddr, unsigned int Length); + +void *MEM_Phy2Vir(unsigned int PhyAddr); + +unsigned int MEM_Vir2Phy(unsigned char *VirAddr); + +void MEM_WritePhyWord(unsigned int PhyAddr, unsigned int Data32); + +unsigned int MEM_ReadPhyWord(unsigned int PhyAddr); + +int MEM_MapRegisterAddr(unsigned int RegStartPhyAddr, unsigned int RegByteLen, MEM_RECORD_S *pMemRecord); + +void MEM_UnmapRegisterAddr(unsigned int PhyAddr, unsigned char *VirAddr, unsigned int Size); + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/public.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/public.h new file mode 100755 index 000000000000..53a87b8ea5df --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/public.h @@ -0,0 +1,55 @@ +#ifndef __PUBLIC_H__ +#define __PUBLIC_H__ + +#include "vfmw.h" + +/* 0X0 : ALWYS, 0X1: ALWYS and FATAL, 0X3: ALWYS and FATAL and ERROR */ +#define DEFAULT_PRINT_ENABLE (0x3) + +typedef enum { + DEV_SCREEN = 1, + DEV_SYSLOG, + DEV_FILE, + DEV_MEM +} PRINT_DEVICE_TYPE; + + +#if 0 +#define dprint_vfmw_nothing(type, fmt, arg...) ({do{}while(0);0;}) + +#define dprint_sos_kernel(type, fmt, arg...) \ +do{ \ + if ((PRN_ALWS == type) || (0 != (DEFAULT_PRINT_ENABLE & (1LL << type)))) \ + { \ + printk(KERN_ALERT "VDEC S: "fmt, ##arg); \ + } \ +}while(0) + +#define dprint_linux_kernel(type, fmt, arg...) \ +do{ \ + if ((PRN_ALWS == type) || (0 != (DEFAULT_PRINT_ENABLE & (1LL << type)))) \ + { \ + printk(KERN_ALERT "VDEC : "fmt, ##arg); \ + } \ +}while(0) + +#ifdef HI_ADVCA_FUNCTION_RELEASE +#define dprint(type, fmt, arg...) dprint_vfmw_nothing(type, fmt, ##arg) +#else + +#ifdef ENV_ARMLINUX_KERNEL +#define dprint(type, fmt, arg...) dprint_linux_kernel(type, fmt, ##arg) +#else +#define dprint(type, fmt, arg...) dprint_vfmw_nothing(type, fmt, ##arg) +#endif + +#endif +#else +#ifdef HI_ADVCA_FUNCTION_RELEASE +#define dprint(type, fmt, arg...) +#else +//#define dprint(type, fmt, arg...) printk(type fmt, ##arg) +#define dprint(type, fmt, arg...) +#endif +#endif +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.c new file mode 100755 index 000000000000..8136f3c386fe --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.c @@ -0,0 +1,261 @@ +/* + * vdec driver for scd master + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +//#include "public.h" +#include "scd_drv.h" +#include "vfmw_intf.h" +#include "linux_kernel_osal.h" +#include "./format/vdm_hal_api.h" +#ifdef HIVDEC_SMMU_SUPPORT +#include "smmu.h" +#endif + +static SCDDRV_SLEEP_STAGE_E s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_NONE; +static SCD_STATE_REG_S gScdStateReg; +static SCD_STATE_E s_SCDState = SCD_IDLE; + +static void PrintScdVtrlReg(void); + +int SCDDRV_ResetSCD(void) +{ + unsigned int tmp; + unsigned int i; + unsigned int reg_rst_ok; + unsigned int reg; + unsigned int *pScdResetReg = NULL; + unsigned int *pScdResetOkReg = NULL; + + pScdResetReg = (unsigned int *) MEM_Phy2Vir(gSOFTRST_REQ_Addr); + pScdResetOkReg = (unsigned int *) MEM_Phy2Vir(gSOFTRST_OK_ADDR); + + if (pScdResetReg == NULL || pScdResetOkReg == NULL) { + printk(KERN_CRIT "scd reset register map fail\n"); + return VF_ERR_SYS; + } + + tmp = RD_SCDREG(REG_SCD_INT_MASK); + + + reg = *(volatile unsigned int *)pScdResetReg; + *(volatile unsigned int *)pScdResetReg = reg | (unsigned int) (1 << SCD_RESET_CTRL_BIT); + + for (i = 0; i < 100; i++) { + reg_rst_ok = *(volatile unsigned int *)pScdResetOkReg; + if (reg_rst_ok & (1 << SCD_RESET_OK_BIT)) + break; + VFMW_OSAL_uDelay(10); + } + + if (i >= 100) + printk(KERN_CRIT "%s reset failed\n", __func__); + else + printk(KERN_INFO "%s reset success\n", __func__); + + *(volatile unsigned int *)pScdResetReg = reg & (unsigned int) (~(1 << SCD_RESET_CTRL_BIT)); + + + WR_SCDREG(REG_SCD_INT_MASK, tmp); + + s_SCDState = SCD_IDLE; + return FMW_OK; +} + +int SCDDRV_PrepareSleep(void) +{ + int ret = SCDDRV_OK; + + VFMW_OSAL_SemaDown(G_SCD_SEM); + if (s_eScdDrvSleepStage == SCDDRV_SLEEP_STAGE_NONE) { + if (SCD_IDLE == s_SCDState) { + printk(KERN_INFO "%s, idle state \n", __func__); + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_SLEEP; + } else { + printk(KERN_INFO "%s, decoded state \n", __func__); + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_PREPARE; + } + + ret = SCDDRV_OK; + } else { + ret = SCDDRV_ERR; + } + + VFMW_OSAL_SemaUp(G_SCD_SEM); + return ret; +} + +SCDDRV_SLEEP_STAGE_E SCDDRV_GetSleepStage(void) +{ + return s_eScdDrvSleepStage; +} + +void SCDDRV_SetSleepStage(SCDDRV_SLEEP_STAGE_E sleepState) +{ + VFMW_OSAL_SemaDown(G_SCD_SEM); + s_eScdDrvSleepStage = sleepState; + VFMW_OSAL_SemaUp(G_SCD_SEM); +} + +void SCDDRV_ForceSleep(void) +{ + printk(KERN_INFO "%s, force state \n", __func__); + VFMW_OSAL_SemaDown(G_SCD_SEM); + if (s_eScdDrvSleepStage != SCDDRV_SLEEP_STAGE_SLEEP) { + SCDDRV_ResetSCD(); + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_SLEEP; + } + VFMW_OSAL_SemaUp(G_SCD_SEM); +} + +void SCDDRV_ExitSleep(void) +{ + VFMW_OSAL_SemaDown(G_SCD_SEM); + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_NONE; + VFMW_OSAL_SemaUp(G_SCD_SEM); +} + +int SCDDRV_WriteReg(SCD_CONFIG_REG_S *pSmCtrlReg ) +{ + if (s_SCDState != SCD_IDLE) + return SCDDRV_ERR; + + s_SCDState = SCD_WORKING; + WR_SCDREG(REG_SCD_INI_CLR, 1); + + // LIST_ADDRESS + WR_SCDREG(REG_LIST_ADDRESS, (unsigned int)pSmCtrlReg->DownMsgPhyAddr); + + // UP_ADDRESS + WR_SCDREG(REG_UP_ADDRESS, (unsigned int) pSmCtrlReg->UpMsgPhyAddr); + + // UP_LEN + WR_SCDREG(REG_UP_LEN, (unsigned int) pSmCtrlReg->UpLen); + + // BUFFER_FIRST + WR_SCDREG(REG_BUFFER_FIRST, (unsigned int) pSmCtrlReg->BufferFirst); + + // BUFFER_LAST + WR_SCDREG(REG_BUFFER_LAST, (unsigned int) pSmCtrlReg->BufferLast); + + // BUFFER_INI + WR_SCDREG(REG_BUFFER_INI, (unsigned int) pSmCtrlReg->BufferIni); + + // SCD_PROTOCOL + WR_SCDREG(REG_SCD_PROTOCOL, (unsigned int) ((pSmCtrlReg->ScdLowdlyEnable << 8) + | ((pSmCtrlReg->SliceCheckFlag << 4) & 0x10) + | (pSmCtrlReg->ScdProtocol & 0x0f))); +#ifdef HIVDEC_SMMU_SUPPORT + SMMU_SetMasterReg(SCD, SECURE_OFF, SMMU_ON); +#endif + +#ifndef SCD_BUSY_WAITTING + WR_SCDREG(REG_SCD_INT_MASK, 0); +#endif + + PrintScdVtrlReg(); + + // SCD_START + WR_SCDREG(REG_SCD_START, 0); + WR_SCDREG(REG_SCD_START, (unsigned int) (pSmCtrlReg->ScdStart & 0x01)); + + return SCDDRV_OK; +} + +void SCDDRV_SaveStateReg(void) +{ + gScdStateReg.ScdProtocol = RD_SCDREG(REG_SCD_PROTOCOL); + gScdStateReg.Scdover = RD_SCDREG(REG_SCD_OVER); + gScdStateReg.ScdInt = RD_SCDREG(REG_SCD_INT); + gScdStateReg.ScdNum = RD_SCDREG(REG_SCD_NUM); + gScdStateReg.ScdRollAddr = RD_SCDREG(REG_ROLL_ADDR); + gScdStateReg.SrcEaten = RD_SCDREG(REG_SRC_EATEN); + gScdStateReg.UpLen = RD_SCDREG(REG_UP_LEN); +} + +void SCDDRV_init(void) +{ + memset(&gScdStateReg, 0, sizeof(gScdStateReg)); + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_NONE; + s_SCDState = SCD_IDLE; +} + +void SCDDRV_DeInit(void) +{ + s_eScdDrvSleepStage = SCDDRV_SLEEP_STAGE_NONE; + s_SCDState = SCD_IDLE; +} + +void SCDDRV_ISR(void) +{ + int dat = 0; + + dat = RD_SCDREG(REG_SCD_OVER) & 0x01; + if ((dat & 1) == 0) { + printk(KERN_CRIT "End0: SM_SCDIntServeProc()\n"); + return; + } + + SCDDRV_SaveStateReg(); + WR_SCDREG(REG_SCD_INI_CLR, 1); + VFMW_OSAL_GiveEvent(G_SCDHWDONEEVENT); +} + +void SCDDRV_GetRegState(SCD_STATE_REG_S *pScdStateReg) +{ + memcpy(pScdStateReg, &gScdStateReg, sizeof(*pScdStateReg)); + s_SCDState = SCD_IDLE; +} + +int WaitSCDFinish(void) +{ + int i; + + if (SCD_WORKING == s_SCDState) { + for (i = 0; i < SCD_TIME_OUT_COUNT; i++) { + if ((RD_SCDREG(REG_SCD_OVER) & 1)) + return SCDDRV_OK; + } + + return SCDDRV_ERR; + } else { + return SCDDRV_OK; + } +} + +static void PrintScdVtrlReg(void) +{ + SCD_CONFIG_REG_S SmCtrlReg; + memset(&SmCtrlReg, 0, sizeof(SmCtrlReg)); + + SmCtrlReg.DownMsgPhyAddr = RD_SCDREG(REG_LIST_ADDRESS); + SmCtrlReg.UpMsgPhyAddr = RD_SCDREG(REG_UP_ADDRESS); + SmCtrlReg.UpLen = RD_SCDREG(REG_UP_LEN); + SmCtrlReg.BufferFirst = RD_SCDREG(REG_BUFFER_FIRST); + SmCtrlReg.BufferLast = RD_SCDREG(REG_BUFFER_LAST); + SmCtrlReg.BufferIni = RD_SCDREG(REG_BUFFER_INI); + SmCtrlReg.ScdProtocol = RD_SCDREG(REG_SCD_PROTOCOL); + SmCtrlReg.ScdStart = RD_SCDREG(REG_SCD_START); +} + +#ifdef ENV_ARMLINUX_KERNEL +int SCDDRV_IsScdIdle(void) +{ + int ret = SCDDRV_OK; + if (SCD_IDLE == s_SCDState) { + ret = SCDDRV_OK; + } else if (SCD_WORKING == s_SCDState) { + ret = SCDDRV_ERR; + } else { + ret = SCDDRV_ERR; + printk(KERN_ERR "%s : s_SCDState : %d is wrong\n", __func__, s_SCDState); + } + return ret; +} +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.h new file mode 100755 index 000000000000..4a4415aa7814 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/scd_drv.h @@ -0,0 +1,166 @@ +#ifndef __SCD_DRV_H__ +#define __SCD_DRV_H__ + +#include "mem_manage.h" +//#include "../omxvdec/memory.h" +#include "vfmw.h" + +#define SCDDRV_OK (0) +#define SCDDRV_ERR (-1) + +#define SCD_TIME_OUT_COUNT (200) + +#define REG_SCD_START (0x800) +#define REG_LIST_ADDRESS (0x804) +#define REG_UP_ADDRESS (0x808) +#define REG_UP_LEN (0x80c) +#define REG_BUFFER_FIRST (0x810) +#define REG_BUFFER_LAST (0x814) +#define REG_BUFFER_INI (0x818) +#define REG_SCD_PROTOCOL (0x820) + +/* state registers */ +#define REG_SCD_OVER (0x840) +#define REG_SCD_INT (0x844) +#define REG_SCD_NUM (0x84c) +#define REG_ROLL_ADDR (0x850) +#define REG_SRC_EATEN (0x854) + +#define REG_SCD_SAFE_INT_MASK (0x884) +#define REG_SCD_SAFE_INI_CLR (0x888) +#define REG_SCD_NORM_INT_MASK (0x81c) +#define REG_SCD_NORM_INI_CLR (0x824) + +#define REG_SCD_INT_MASK REG_SCD_NORM_INT_MASK +#define REG_SCD_INI_CLR REG_SCD_NORM_INI_CLR + +#define REG_AVS_FLAG (0x0000) +#define REG_EMAR_ID (0x0004) +#define REG_VDH_SELRST (0x0008) + +#define SM_SCD_UP_INFO_NUM (2) +#ifdef CFG_MAX_RAW_NUM +#define MAX_STREAM_RAW_NUM (CFG_MAX_RAW_NUM) +#else +#define MAX_STREAM_RAW_NUM (1024) +#endif +#ifdef CFG_MAX_SEG_NUM +#define MAX_STREAM_SEG_NUM (CFG_MAX_SEG_NUM) +#else +#define MAX_STREAM_SEG_NUM (1024 + 128) +#endif +#define SM_MAX_DOWNMSG_SIZE (3 * MAX_STREAM_RAW_NUM * sizeof(SINT32)) +#define SM_MAX_UPMSG_SIZE (SM_SCD_UP_INFO_NUM * MAX_STREAM_SEG_NUM * sizeof(SINT32)) +typedef enum { + FMW_OK = 0, + FMW_ERR_PARAM = -1, + FMW_ERR_NOMEM = -2, + FMW_ERR_NOTRDY = -3, + FMW_ERR_BUSY = -4, + FMW_ERR_RAWNULL = -5, + FMW_ERR_SEGFULL = -6, + FMW_ERR_SCD = -7 +} FMW_RETVAL_E; + +typedef enum { + SCDDRV_SLEEP_STAGE_NONE = 0, + SCDDRV_SLEEP_STAGE_PREPARE, + SCDDRV_SLEEP_STAGE_SLEEP +} SCDDRV_SLEEP_STAGE_E; + +typedef enum { + SCD_IDLE = 0, + SCD_WORKING, +} SCD_STATE_E; + +/* register operator */ +#define RD_SCDREG(reg) MEM_ReadPhyWord((gScdRegBaseAddr + reg)) +#define WR_SCDREG(reg, dat) MEM_WritePhyWord((gScdRegBaseAddr + reg),(dat)) + +#define FMW_ASSERT_RET( cond, ret ) \ +do{ \ + if (!(cond)) \ + return (ret); \ +} while (0) + +/*###################################################### + struct defs. + ######################################################*/ +typedef enum { + SCD_SHAREFD_MESSAGE_POOL = 0, + SCD_SHAREFD_OUTPUT_BUF = 1, + SCD_SHAREFD_MAX +}SCD_SHAREFD; + +typedef struct { + int Scdover; + int ScdInt; + int ShortScdNum; + int ScdNum; + unsigned int ScdRollAddr; + int SrcEaten; +} SM_STATEREG_S; + +typedef struct +{ + char SliceCheckFlag; + char ScdStart; + unsigned int DownMsgPhyAddr; + unsigned int UpMsgPhyAddr; + int UpLen; + unsigned int BufferFirst; + unsigned int BufferLast; + unsigned int BufferIni; + int ScdProtocol; + int ScdLowdlyEnable; + int scd_share_fd[SCD_SHAREFD_MAX]; + int IsScdAllBufRemap; +} SCD_CONFIG_REG_S; + +typedef struct { + int ScdProtocol; + int Scdover; + int ScdInt; + int ScdNum; + unsigned int ScdRollAddr; + int SrcEaten; + int UpLen; +} SCD_STATE_REG_S; + +typedef enum hi_CONFIG_SCD_CMD { + CONFIG_SCD_REG_CMD = 100, +} CONFIG_SCD_CMD; + +typedef struct { + CONFIG_SCD_CMD cmd; + int eVidStd; + unsigned int SResetFlag; + unsigned int GlbResetFlag; + SCD_CONFIG_REG_S SmCtrlReg; +} OMXSCD_REG_CFG_S; + +int SCDDRV_PrepareSleep(void); + +SCDDRV_SLEEP_STAGE_E SCDDRV_GetSleepStage(void); +void SCDDRV_SetSleepStage(SCDDRV_SLEEP_STAGE_E sleepState); + +void SCDDRV_ForceSleep(void); + +void SCDDRV_ExitSleep(void); + +int SCDDRV_ResetSCD(void); + +int SCDDRV_WriteReg(SCD_CONFIG_REG_S *pSmCtrlReg ); + +void SCDDRV_GetRegState(SCD_STATE_REG_S *pScdStateReg); + +void SCDDRV_ISR(void); + +void SCDDRV_init(void); + +void SCDDRV_DeInit(void); + +#ifdef ENV_ARMLINUX_KERNEL +int SCDDRV_IsScdIdle(void); +#endif +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.c new file mode 100755 index 000000000000..f2a387249360 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.c @@ -0,0 +1,479 @@ +/* + * vdec driver for smmu master + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ + +#ifdef ENV_ARMLINUX_KERNEL +#include +#include +#include +#endif +#include +#include "smmu.h" +//#include "public.h" +#include "mem_manage.h" +#include "linux_kernel_osal.h" +#include +#include "../omxvdec/omxvdec.h" + +#define SMRx_ID_SIZE 32 +#define SMMU_RWERRADDR_SIZE 128 + +#define HIVDEC_SMMU_COMMON_OFFSET (0x20000) +#define HIVDEC_SMMU_MASTER_OFFSET (0xF000) + +#define HIVDEC_SMMU_COMMON_BASE_ADDR (gVdhRegBaseAddr + HIVDEC_SMMU_COMMON_OFFSET) +#define HIVDEC_SMMU_MASTER_BASE_ADDR (gVdhRegBaseAddr + HIVDEC_SMMU_MASTER_OFFSET) + +//SMMU common and Master(MFDE/SCD/BPD) virtual base address +typedef struct { + int *pSMMUCommonBaseVirAddr; + int *pSMMUMasterBaseVirAddr; + int *pSMMUMFDERegVirAddr; + int *pSMMUBPDRegVirAddr; + int *pSMMUSCDRegVirAddr; +} SMMU_REG_VIR_S; + +SMMU_REG_VIR_S gSmmuRegVir; +MEM_DESC_S gAllocMem_RD; +MEM_DESC_S gAllocMem_WR; + +int gSmmuInitFlag = 0; +int gMfdeSecureFlag = 0; +int gMfdeSmmuFlag = 1; +int gScdSecureFlag = 0; +int gScdSmmuFlag = 1; +int gBpdSecureFlag = 0; +int gBpdSmmuFlag = 0; + +//smmu common regs r/w +#define RD_SMMU_COMMON_VREG( reg, dat ) \ +do { \ + (dat) = readl(((volatile int*)((char*)gSmmuRegVir.pSMMUCommonBaseVirAddr + (reg)))); \ +} while(0) + +#define WR_SMMU_COMMON_VREG( reg, dat ) \ +do { \ + writel((dat), ((volatile int*)((char*)gSmmuRegVir.pSMMUCommonBaseVirAddr + (reg)))); \ +} while(0) +//smmu master regs r/w +#define RD_SMMU_MASTER_VREG( reg, dat ) \ +do { \ + (dat) = readl(((volatile int*)((char*)gSmmuRegVir.pSMMUMasterBaseVirAddr + (reg)))); \ +} while(0) + +#define WR_SMMU_MASTER_VREG( reg, dat ) \ +do { \ + writel((dat), ((volatile int*)((char*)gSmmuRegVir.pSMMUMasterBaseVirAddr + (reg)))); \ +} while(0) + +//mfde regs r/w +#define RD_SMMU_MFDE_VREG( reg, dat ) \ +do { \ + (dat) = readl(((volatile int*)((char*)gSmmuRegVir.pSMMUMFDERegVirAddr + (reg)))); \ +} while(0) + +#define WR_SMMU_MFDE_VREG( reg, dat ) \ +do { \ + writel((dat), ((volatile int*)((char*)gSmmuRegVir.pSMMUMFDERegVirAddr + (reg)))); \ +} while(0) +//bpd regs r/w +#define RD_SMMU_BPD_VREG( reg, dat ) \ +do { \ + (dat) = readl(((volatile int*)((char*)gSmmuRegVir.pSMMUBPDRegVirAddr + (reg)))); \ +} while(0) + +#define WR_SMMU_BPD_VREG( reg, dat ) \ +do { \ + writel((dat), ((volatile int*)((char*)gSmmuRegVir.pSMMUBPDRegVirAddr + (reg)))); \ +} while(0) +//scd regs r/w +#define RD_SMMU_SCD_VREG( reg, dat ) \ +do { \ + (dat) = readl(((volatile int*)((char*)gSmmuRegVir.pSMMUSCDRegVirAddr + (reg)))); \ +} while(0) + +#define WR_SMMU_SCD_VREG( reg, dat ) \ +do { \ + writel((dat), ((volatile int*)((char*)gSmmuRegVir.pSMMUSCDRegVirAddr + (reg)))); \ +} while(0) + +/** + *function: set SMMU common register + *addr: register's vir addr + *val: value to be set + *bw: bit width + *bs: bit start + */ +static void set_common_reg(unsigned int addr, int val, int bw, int bs) +{ + int mask = (1UL << bw) - 1UL; + int tmp = 0; + + RD_SMMU_COMMON_VREG(addr, tmp); + tmp &= ~(mask << bs);/*lint !e502*/ + WR_SMMU_COMMON_VREG(addr, tmp | ((val & mask) << bs)); +} + +/** + *function: set SMMU master register + *addr: register's vir addr + *val: value to be set + *bw: bit width + *bs: bit start + */ +static void set_master_reg(unsigned int addr, int val, int bw, int bs) +{ + int mask = (1UL << bw) - 1UL; + int tmp = 0; + + RD_SMMU_MASTER_VREG(addr, tmp); + tmp &= ~(mask << bs);/*lint !e502*/ + WR_SMMU_MASTER_VREG(addr, (tmp | ((val & mask) << bs))); + +} + +/** + *function: set mfde/scd/bpd register + *master_type: MFDE/SCD/BPD + *addr: register's vir addr + *val: value to be set + *bw: bit width + *bs: bit start + */ +static void set_vdh_master_reg(SMMU_MASTER_TYPE master_type, unsigned int addr, int val, int bw, int bs) +{ + int mask = (1UL << bw) - 1UL; + int tmp = 0; + + switch (master_type) { + case MFDE: + RD_SMMU_MFDE_VREG(addr, tmp); + tmp &= ~(mask << bs);/*lint !e502*/ + WR_SMMU_MFDE_VREG(addr, tmp | ((val & mask) << bs)); + break; + + case BPD: + RD_SMMU_BPD_VREG(addr, tmp); + tmp &= ~(mask << bs);/*lint !e502*/ + WR_SMMU_BPD_VREG(addr, tmp | ((val & mask) << bs)); + break; + + case SCD: + RD_SMMU_SCD_VREG(addr, tmp); + tmp &= ~(mask << bs);/*lint !e502*/ + WR_SMMU_SCD_VREG(addr, tmp | ((val & mask) << bs)); + break; + + default: + break; + } +} + +/** + *function: set mfde mmu cfg register + */ +static void set_mmu_cfg_reg_mfde(SMMU_MASTER_TYPE master_type, unsigned int secure_en, unsigned int mmu_en) +{ + if (mmu_en) { //MMU enable + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_EN, 0x1, 1, 12); //[12]mmu_en=1 + if (secure_en) { //secure + printk(KERN_INFO "IN %s not support this mode: mmu_en:secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_SECURE, 0x1, 1, 31); //[31]secure_en=1 + } else { //non-secure + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_SECURE, 0x0, 1, 31); //[31]secure_en=0 + } + } else { //MMU disable + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_EN, 0x0, 1, 12); //[12]mmu_en=0 + if (secure_en) { //secure + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_SECURE, 0x1, 1, 31); //[31]secure_en=1 + } else { //non-secure + printk(KERN_INFO "IN %s not support this mode: non_mmu:non_secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_MFDE_MMU_CFG_SECURE, 0x0, 1, 31); //[31]secure_en=0 + } + } +} + +/** + *function: set bpd mmu cfg register + */ +static void set_mmu_cfg_reg_bpd(SMMU_MASTER_TYPE master_type, unsigned int secure_en, unsigned int mmu_en) +{ + if (mmu_en) { //MMU enable + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x1, 1, 21); //[21]mmu_en=1 + if (secure_en) { //secure + printk(KERN_INFO "IN %s not support this mode: mmu_en:secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x1, 1, 20); //[20]secure_en=1 + } else { //non-secure + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x0, 1, 20); //[20]secure_en=0 + } + } else { //MMU disable + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x0, 1, 21); //[21]mmu_en=0 + if (secure_en) { //secure + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x1, 1, 20); //[20]secure_en=1 + } else { //non-secure + printk(KERN_INFO "IN %s not support this mode: non_mmu:non_secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_BPD_MMU_CFG, 0x0, 1, 20); //[20]secure_en=0 + } + } +} + +/** + *function: set scd mmu cfg register + */ +static void set_mmu_cfg_reg_scd(SMMU_MASTER_TYPE master_type, unsigned int secure_en, unsigned int mmu_en) +{ + if (mmu_en) { //MMU enable + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x1, 1, 9);//[9]mmu_en=1 + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x1, 1, 13);//[13]rdbuf_mmu_en=1 + if (secure_en) { //secure + printk(KERN_INFO "IN %s not support this mode: mmu_en:secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x1, 1, 7); //[7]secure_en=1 + } else { //non-secure + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x0, 1, 7); //[7]secure_en=0 + } + } else { //MMU disable + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x0, 1, 9); //[9]mmu_en=0 + if (secure_en) { //secure + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x1, 1, 7); //[7]secure_en=1 + } else { //non-secure + printk(KERN_INFO "IN %s not support this mode: non_mmu:non_secure\n", __func__); + printk(KERN_INFO "%s, secure_en:%d, mmu_en:%d\n", __func__, secure_en, mmu_en); + set_vdh_master_reg(master_type, REG_SCD_MMU_CFG, 0x0, 1, 7); //[7]secure_en=0 + } + } +} + +static int smmu_mem_alloc(unsigned int size, MEM_DESC_S *pMemDesc) +{ + void *virt_addr = NULL; + + if (pMemDesc == NULL) { + printk(KERN_ERR "%s: invalid param pMemDesc is NULL\n", __func__); + return SMMU_ERR; + } + + if (pMemDesc->VirAddr != 0L) { + printk(KERN_ERR "%s param StartVirAddr %pK is not NULL\n", __func__, (void*)pMemDesc->VirAddr); + return SMMU_ERR; + } + + if (MEM_CMA_ZERO == pMemDesc->MemType) + virt_addr = kzalloc(size, GFP_KERNEL | GFP_DMA); //restrict [0 ~ 4G] + else + virt_addr = kmalloc(size, GFP_KERNEL | GFP_DMA); //restrict [0 ~ 4G] + + if (!virt_addr) { + printk(KERN_ERR "%s Alloc virt_addr failed\n", __func__); + return SMMU_ERR; + } + + pMemDesc->VirAddr = (unsigned long long)virt_addr; + pMemDesc->PhyAddr = __pa(virt_addr);/*lint !e648*/ + + return SMMU_OK; +} + +static void smmu_mem_dealloc(MEM_DESC_S *pMemDesc) +{ + if (pMemDesc == NULL) { + printk(KERN_ERR "%s : Invalid pMemDesc is NULL\n", __func__); + return; + } + + if (pMemDesc->VirAddr == 0L) { + printk(KERN_ERR "%s : Invalid pMemDesc->VirAddr is NULL\n", __func__); + return; + } + + kfree((void *)pMemDesc->VirAddr); + pMemDesc->VirAddr = 0L; + return; +} + +/** + *function: Alloc MEM for TLB miss . + */ +#ifdef ENV_ARMLINUX_KERNEL +static int alloc_smmu_tlb_miss_addr(void) +{ + int ret = SMMU_ERR; + + gAllocMem_RD.MemType = MEM_CMA_ZERO; + ret = smmu_mem_alloc(SMMU_RWERRADDR_SIZE, &gAllocMem_RD); + if (ret != MEM_MAN_OK) { + printk(KERN_ERR "%s kzalloc mem for smmu rderr failed\n", __func__); + return SMMU_ERR; + } + + gAllocMem_WR.MemType = MEM_CMA_ZERO; + ret = smmu_mem_alloc(SMMU_RWERRADDR_SIZE, &gAllocMem_WR); + if (ret != MEM_MAN_OK) { + printk(KERN_ERR "%s kzalloc mem for smmu wrerr failed\n", __func__); + smmu_mem_dealloc(&gAllocMem_RD); + return SMMU_ERR; + } + + return SMMU_OK; +} +#endif + +/** + *function: init SMMU global registers. + */ +void SMMU_InitGlobalReg(void) +{ + unsigned int i = 0; + + if (gSmmuInitFlag != 1) { + printk(KERN_DEBUG "%s Smmu initialization failed\n", __func__); + return; + } + //0000 0000 0000 1111 0000 0000 0011 1000 --> 0x000f0038 + set_common_reg(SMMU_SCR, 0x0, 1, 0);//SMMU_SCR[0].glb_bypass + set_common_reg(SMMU_SCR, 0x3, 2, 1);//SMMU_SCR[1].rqos_en SMMU_SCR[2].wqos_en + + //SMRX_S had set default value. Only need to set SMMU_SMRx_NS secure SID bypass + //SMMU_SMRx[0]smr_bypass=0(non-bypass); SMMU_SMRx[2:3]smr_ptw_qos=0x3; + for (i = 0; i < SMRx_ID_SIZE; i += 2) { + set_common_reg(SMMU_SMRx_NS + i*0x4, 0x1C, 32, 0);//0x00000003 none secure + } + + for (i = 1; i < SMRx_ID_SIZE; i += 2) { + set_common_reg(SMMU_SMRx_NS + i*0x4, 0x1D, 32, 0);//0x00000002 secure + } + set_common_reg(SMMU_CB_TTBR0, gSmmuPageBase, 32, 0); + set_common_reg(SMMU_FAMA_CTRL1_NS, (gSmmuPageBase>>32)&0x7F, 32, 0); + set_common_reg(SMMU_CB_TTBCR, 0x1, 1, 0); + + if (gAllocMem_RD.PhyAddr != 0 && gAllocMem_WR.PhyAddr != 0) { + set_common_reg(SMMU_ERR_RDADDR, (gAllocMem_RD.PhyAddr & 0xFFFFFFFF), 32, 0); + set_common_reg(SMMU_ADDR_MSB, (gAllocMem_RD.PhyAddr>>32)&0x7F, 7, 0); + + set_common_reg(SMMU_ERR_WRADDR, (gAllocMem_WR.PhyAddr & 0xFFFFFFFF), 32, 0); + set_common_reg(SMMU_ADDR_MSB, (gAllocMem_WR.PhyAddr>>32)&0x7F, 7, 7); + } + //glb_bypass, 0x0: normal mode, 0x1: bypass mode + set_master_reg(SMMU_MSTR_GLB_BYPASS, 0x0, 32, 0); //master mmu enable +} + +/** + *function: set MFDE/SCD/BPD mmu cfg register, MMU or secure. + */ +void SMMU_SetMasterReg(SMMU_MASTER_TYPE master_type, unsigned char secure_en, unsigned char mmu_en) +{ + switch (master_type) { + case MFDE: + set_mmu_cfg_reg_mfde(master_type, secure_en, mmu_en); + gMfdeSecureFlag = secure_en; + gMfdeSmmuFlag = mmu_en; + break; + + case SCD: + set_mmu_cfg_reg_scd(master_type, secure_en, mmu_en); + gScdSecureFlag = secure_en; + gScdSmmuFlag = mmu_en; + break; + + case BPD: + set_mmu_cfg_reg_bpd(master_type, secure_en, mmu_en); + gBpdSecureFlag = secure_en; + gBpdSmmuFlag = mmu_en; + break; + + default: + printk(KERN_ERR "%s unkown master type %d\n", __func__, master_type); + break; + } +} + +void SMMU_IntServProc(void) +{ + int tmp = -1; + RD_SMMU_COMMON_VREG(SMMU_INTSTAT_NS, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_0, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_1, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_2, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_3, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_4, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_5, tmp); + RD_SMMU_MASTER_VREG(SMMU_MSTR_DBG_6, tmp); +} + +/** + *function: get registers virtual address, and alloc mem for TLB miss. + */ +int SMMU_Init(void) +{ + int ret = SMMU_ERR; + memset(&gSmmuRegVir, 0, sizeof(gSmmuRegVir)); + + gSmmuRegVir.pSMMUMFDERegVirAddr = (int *) MEM_Phy2Vir(gVdhRegBaseAddr); + if (gSmmuRegVir.pSMMUMFDERegVirAddr == NULL) { + printk(KERN_ERR "%s pSMMUMFDERegVirAddr is NULL, SMMU Init failed\n", __func__); + return SMMU_ERR; + } + + gSmmuRegVir.pSMMUSCDRegVirAddr = (int *) MEM_Phy2Vir(gScdRegBaseAddr); + if (gSmmuRegVir.pSMMUSCDRegVirAddr == NULL) { + printk(KERN_ERR "%s pSMMUSCDRegVirAddr is NULL, SMMU Init failed\n", __func__); + return SMMU_ERR; + } + + gSmmuRegVir.pSMMUBPDRegVirAddr = (int *) MEM_Phy2Vir(gBpdRegBaseAddr); + if (gSmmuRegVir.pSMMUBPDRegVirAddr == NULL) { + printk(KERN_ERR "%s pSMMUBPDRegVirAddr is NULL, SMMU Init failed\n", __func__); + return SMMU_ERR; + } + + gSmmuRegVir.pSMMUCommonBaseVirAddr = (int *) MEM_Phy2Vir(HIVDEC_SMMU_COMMON_BASE_ADDR); + if (gSmmuRegVir.pSMMUCommonBaseVirAddr == NULL) { + printk(KERN_ERR "%s pSMMUCommonBaseVirAddr is NULL, SMMU Init failed\n", __func__); + return SMMU_ERR; + } + + gSmmuRegVir.pSMMUMasterBaseVirAddr = (int *) MEM_Phy2Vir(HIVDEC_SMMU_MASTER_BASE_ADDR); + if (gSmmuRegVir.pSMMUMasterBaseVirAddr == NULL) { + printk(KERN_ERR "%s pSMMUMasterBaseVirAddr is NULL, SMMU Init failed\n", __func__); + return SMMU_ERR; + } + + memset(&gAllocMem_RD, 0, sizeof(gAllocMem_RD)); + memset(&gAllocMem_WR, 0, sizeof(gAllocMem_WR)); + +#ifdef ENV_ARMLINUX_KERNEL + ret = alloc_smmu_tlb_miss_addr(); + if (ret != SMMU_OK) { + printk(KERN_ERR "%s alloc_smmu_tlb_miss_addr failed\n", __func__); + return SMMU_ERR; + } +#endif + + gSmmuInitFlag = 1; + + return SMMU_OK; +} + +/** + *function: free mem of SMMU_ERR_RDADDR and SMMU_ERR_WRADDR. + */ +void SMMU_DeInit(void) +{ + if (gAllocMem_RD.PhyAddr != 0) + smmu_mem_dealloc(&gAllocMem_RD); + + if (gAllocMem_WR.PhyAddr != 0) + smmu_mem_dealloc(&gAllocMem_WR); +} diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.h new file mode 100755 index 000000000000..a4d38d9f1d96 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/smmu.h @@ -0,0 +1,64 @@ +#ifndef __HIVDEC_SMMU_H__ +#define __HIVDEC_SMMU_H__ + +#include "sysconfig.h" //for VDM_REG_PHY_ADDR, SCD_REG_PHY_ADDR, BPD_REG_PHY_ADDR +#include "vfmw.h" + +#define SMMU_OK 0 +#define SMMU_ERR -1 + +#define SECURE_ON 1 +#define SECURE_OFF 0 +#define SMMU_ON 1 +#define SMMU_OFF 0 +/******************************************************************************* +**SMMU COMMON registers +*/ +#define SMMU_SCR (0x0000) + +//non-secure +#define SMMU_INTSTAT_NS (0x0018) +#define SMMU_SMRx_NS (0x0020) //(0x0020+n*0x4) SMMU control register per stream for non-secure +#define SMMU_CB_TTBR0 (0x0204) //SMMU translation table base register for non-secure context bank0 +#define SMMU_FAMA_CTRL1_NS (0x0224)//SMMU Control Register for FAMA for TCU of Non-Secure Context Bank +#define SMMU_CB_TTBCR (0x020C) //SMMU Translation Table Base Control Register for Non-Secure Context Bank +#define SMMU_ADDR_MSB (0x0300) //Register for MSB of all 33-bits address configuration +#define SMMU_ERR_RDADDR (0x0304) //SMMU Error Address of TLB miss for Read transaction +#define SMMU_ERR_WRADDR (0x0308) //SMMU Error Address of TLB miss for Write transaction + +/********************************************** +**MASTER(MFDE/SCD/BPD) registers +*/ +#define REG_MFDE_MMU_CFG_SECURE (0x0008) +#define REG_MFDE_MMU_CFG_EN (0x000c) +#define REG_SCD_MMU_CFG (0x0820) +#define REG_BPD_MMU_CFG (0x0004) +/***********************************************/ + +/************************************************* +**SMMU MASTER registers +*/ +#define SMMU_MSTR_GLB_BYPASS (0x0000) + +#define SMMU_MSTR_DBG_0 (0x0010) +#define SMMU_MSTR_DBG_1 (0x0014) +#define SMMU_MSTR_DBG_2 (0x0018) +#define SMMU_MSTR_DBG_3 (0x001c) +#define SMMU_MSTR_DBG_4 (0x0020) +#define SMMU_MSTR_DBG_5 (0x0024) +#define SMMU_MSTR_DBG_6 (0x0028) +/***********************************************/ + +typedef enum { + MFDE = 0, + BPD, + SCD, +} SMMU_MASTER_TYPE; + +int SMMU_Init(void); +void SMMU_DeInit(void); +void SMMU_SetMasterReg(SMMU_MASTER_TYPE master_type, unsigned char secure_en, unsigned char mmu_en); +void SMMU_InitGlobalReg(void); +void SMMU_IntServProc(void); + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/sysconfig.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/sysconfig.h new file mode 100755 index 000000000000..6aa45c2b2475 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/sysconfig.h @@ -0,0 +1,54 @@ +/*--------------------------------------------------------------------------------------------------------------------------*/ +/*!!Warning: This is a key information asset of Huawei Tech Co.,Ltd */ +/*CODEMARK:kOyQZYzjDpyGdBAEC2GaWinjiDDUykL9e8pckESWBbMVmSWkBuyJO01cTiy3TdzKxGk0oBQa +mSMf7J4FkTpfvzHyMxSEsfcbL/G0fFswaAZ8tsS4we+PBWC6a/UNlzCWIaw+Ujkv9NAY+as0 +fg7WZIRvw27AjvRqJbkRJvqFUORSa6KPQaSBMxCxJTGTTf//sQbjPOyYldN0OVR9ut4HFO4U +ZguGQVqcOAJQbE96v6175DqhuprKgQB8R+2fu7VD3qtX+ZJh/t0512oqv+e8YA==*/ +/*--------------------------------------------------------------------------------------------------------------------------*/ +#ifndef __VFMW_SYSCONFIG_HEADER__ +#define __VFMW_SYSCONFIG_HEADER__ + +#include "vfmw.h" + +/* valid vdh num */ +#define MAX_VDH_NUM (1) +/* register offset */ +#define SCD_REG_OFFSET (0xc000) +#define BPD_REG_OFFSET (0xd000) + +#define SOFTRST_REQ_OFFSET (0xcc0c)//(0xf80c) +#define SOFTRST_OK_OFFSET (0xcc10)//(0xf810) + +#define ALL_RESET_CTRL_BIT (0) +#define MFDE_RESET_CTRL_BIT (1) +#define SCD_RESET_CTRL_BIT (2) +#define BPD_RESET_CTRL_BIT (3) + +#define ALL_RESET_OK_BIT (0) +#define MFDE_RESET_OK_BIT (1) +#define SCD_RESET_OK_BIT (2) +#define BPD_RESET_OK_BIT (3) + +/* FPGA flag */ +extern unsigned int gIsFPGA; + +/* register base addr & range */ +extern unsigned int gVdhRegBaseAddr; +extern unsigned int gScdRegBaseAddr; +extern unsigned int gBpdRegBaseAddr; +extern unsigned int gVdhRegRange; +extern unsigned int gSOFTRST_REQ_Addr; +extern unsigned int gSOFTRST_OK_ADDR; + +/* smmu page table base addr */ +extern unsigned long long gSmmuPageBase; + +/* peri crg base addr */ +extern unsigned int gPERICRG_RegBaseAddr; + +/* irq num */ +extern unsigned int gVdecIrqNumNorm; +extern unsigned int gVdecIrqNumProt; +extern unsigned int gVdecIrqNumSafe; + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw.h new file mode 100755 index 000000000000..9d2c2132dca4 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw.h @@ -0,0 +1,66 @@ +#ifndef __VDEC_FIRMWARE_H__ +#define __VDEC_FIRMWARE_H__ + +#define VFMW_VERSION_NUM (2017032400) +#define TVP_CHAN_NUM (0) +#define MAX_CHAN_NUM (32) +#define MAX_FRAME_NUM (32) + +#define VDEC_OK (0) +#define VDEC_ERR (-1) +#define VF_ERR_SYS (-20) + +typedef enum { + VFMW_START_RESERVED = 0, + VFMW_H264 = 0, + VFMW_VC1, + VFMW_MPEG4, + VFMW_MPEG2, + VFMW_H263, + VFMW_DIVX3, + VFMW_AVS, + VFMW_JPEG, + VFMW_REAL8 = 8, + VFMW_REAL9 = 9, + VFMW_VP6 = 10, + VFMW_VP6F, + VFMW_VP6A, + VFMW_VP8, + VFMW_VP9, + VFMW_SORENSON, + VFMW_MVC, + VFMW_HEVC, + VFMW_RAW, + VFMW_USER, /*## vfmw simply provide frame path. for external decoder, eg. mjpeg ## */ + VFMW_END_RESERVED +} VID_STD_E; + +/*memory type*/ +typedef enum { + MEM_ION = 0, // ion default + MEM_ION_CTG, // ion contigeous + MEM_CMA, // kmalloc + MEM_CMA_ZERO, // kzalloc +} MEM_TYPE_E; + +/* memroy description */ +typedef struct { + unsigned char IsSecure; + MEM_TYPE_E MemType; + unsigned long long PhyAddr; + unsigned int Length; + unsigned long long VirAddr; +} MEM_DESC_S; + +typedef struct { + unsigned int IsFPGA; + unsigned int VdecIrqNumNorm; + unsigned int VdecIrqNumProt; + unsigned int VdecIrqNumSafe; + unsigned int VdhRegBaseAddr; + unsigned int VdhRegRange; + unsigned long long SmmuPageBaseAddr; + unsigned int PERICRG_RegBaseAddr; +} VFMW_DTS_CONFIG_S; + +#endif // __VDEC_FIRMWARE_H__ diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_config.cfg b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_config.cfg new file mode 100755 index 000000000000..bb75aafd3695 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_config.cfg @@ -0,0 +1,73 @@ +############################################################## +# vfmw support config # +############################################################## + +################# vfmw_h264 ################################# +VFMW_H264_SUPPORT = YES +#VFMW_H264_SUPPORT = NO + +################# vfmw_hevc ################################# +VFMW_HEVC_SUPPORT = YES +#VFMW_HEVC_SUPPORT = NO + +################# vfmw_mpeg2 ################################# +VFMW_MPEG2_SUPPORT = YES +#VFMW_MPEG2_SUPPORT = NO + +################# vfmw_mpeg4 ################################# +VFMW_MPEG4_SUPPORT = YES +#VFMW_MPEG4_SUPPORT = NO + +################# vfmw_vp8 ################################# +VFMW_VP8_SUPPORT = YES +#VFMW_VP8_SUPPORT = NO + +################# vfmw_vp9 ################################# +VFMW_VP9_SUPPORT = YES +#VFMW_VP9_SUPPORT = NO + +################# vfmw_raw_num ############################# +#VFMW_RAW_NUM_SUPPORT = YES +VFMW_RAW_NUM_SUPPORT = NO +VFMW_MAX_RAW_NUM = 256 + +################# vfmw_seg_num ############################# +#VFMW_SEG_NUM_SUPPORT = YES +VFMW_SEG_NUM_SUPPORT = NO +VFMW_MAX_SEG_NUM = 256 + +################# vfmw_scd_msg_buffer ###################### +#VFMW_SCD_MSG_SUPPORT = YES +VFMW_SCD_MSG_SUPPORT = NO +VFMW_SCD_MSG_BUF = 64*1024 + +################# product_recpos ########################### +#VFMW_RECPOS_SUPPORT = YES +VFMW_RECPOS_SUPPORT = NO + +################# SCD_SUPPORT ############################## +VFMW_SCD_SUPPORT = YES +#VFMW_SCD_SUPPORT = NO + +################# VDH_SUPPORT ############################## +VFMW_VDH_SUPPORT = YES +#VFMW_VDH_SUPPORT = NO + +################# VFMW SYSTEM REG DISABLE ################## +VFMW_SYSTEM_REG_DISABLE = YES +#VFMW_SYSTEM_REG_DISABLE = NO + +################# VFMW SMMU ################################ +HIVDEC_SMMU_SUPPORT = YES +#HIVDEC_SMMU_SUPPORT = NO + +################# VFMW TVP ################################# +ifeq ($(TARGET_BOARD_PLATFORM), kirin970) +VFMW_TVP_SUPPORT = YES +#VFMW_TVP_SUPPORT = NO +endif + + +################# CONSTRAINT_VDH_PERFORMANCE ################################# +CONSTRAINT_VDH_PERFORMANCE = NO +#CONSTRAINT_VDH_PERFORMANCE = YES diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.c new file mode 100755 index 000000000000..988191bc3807 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.c @@ -0,0 +1,82 @@ +#include "vfmw_dts.h" +#include "sysconfig.h" +//#include "public.h" +#include "omxvdec.h" +#include + +unsigned int gIsFPGA = 0; +unsigned int gVdhRegBaseAddr = 0; +unsigned int gScdRegBaseAddr = 0; +unsigned int gBpdRegBaseAddr = 0; +unsigned int gVdhRegRange = 0; +unsigned int gSOFTRST_REQ_Addr = 0; +unsigned int gSOFTRST_OK_ADDR = 0; +unsigned long long gSmmuPageBase = 0; +unsigned int gPERICRG_RegBaseAddr = 0; + +/* irq num */ +unsigned int gVdecIrqNumNorm = 0; +unsigned int gVdecIrqNumProt = 0; +unsigned int gVdecIrqNumSafe = 0; + +int VFMW_SetDtsConfig(VFMW_DTS_CONFIG_S *pDtsConfig) +{ + if (pDtsConfig == NULL) { + printk(KERN_ERR "%s : pDtsConfig is NULL\n", __func__); + return VDEC_ERR; + } + + if (pDtsConfig->VdecIrqNumNorm == 0 || pDtsConfig->VdecIrqNumProt == 0 || pDtsConfig->VdecIrqNumSafe == 0 || + pDtsConfig->VdhRegBaseAddr == 0 || pDtsConfig->VdhRegRange == 0 || pDtsConfig->SmmuPageBaseAddr == 0 || + pDtsConfig->PERICRG_RegBaseAddr == 0) { + printk(KERN_ERR "%s invalid param: IsFPGA : %d, VdecIrqNumNorm : %d, VdecIrqNumProt : %d, VdecIrqNumSafe : %d, VdhRegBaseAddr : %pK, VdhRegSize : %d, SmmuPageBaseAddr : %pK, PERICRG_RegBaseAddr : %pK\n", __func__, + pDtsConfig->IsFPGA, pDtsConfig->VdecIrqNumNorm, pDtsConfig->VdecIrqNumProt, pDtsConfig->VdecIrqNumSafe, (void *)(uintptr_t)(pDtsConfig->VdhRegBaseAddr), pDtsConfig->VdhRegRange, (void *)(uintptr_t)(pDtsConfig->SmmuPageBaseAddr), (void *)(uintptr_t)(pDtsConfig->PERICRG_RegBaseAddr)); + return VDEC_ERR; + } + + gIsFPGA = pDtsConfig->IsFPGA; + gVdecIrqNumNorm = pDtsConfig->VdecIrqNumNorm; + gVdecIrqNumProt = pDtsConfig->VdecIrqNumProt; + gVdecIrqNumSafe = pDtsConfig->VdecIrqNumSafe; + + gVdhRegBaseAddr = pDtsConfig->VdhRegBaseAddr; + gVdhRegRange = pDtsConfig->VdhRegRange; + gSmmuPageBase = pDtsConfig->SmmuPageBaseAddr; + gPERICRG_RegBaseAddr = pDtsConfig->PERICRG_RegBaseAddr; + + gScdRegBaseAddr = gVdhRegBaseAddr + SCD_REG_OFFSET; + gBpdRegBaseAddr = gVdhRegBaseAddr + BPD_REG_OFFSET; + gSOFTRST_REQ_Addr = gVdhRegBaseAddr + SOFTRST_REQ_OFFSET; + gSOFTRST_OK_ADDR = gVdhRegBaseAddr + SOFTRST_OK_OFFSET; +#if 0 + printk(KERN_ERR "%s invalid param: IsFPGA : %d, VdecIrqNumNorm : %d, VdecIrqNumProt : %d, VdecIrqNumSafe : %d, VdhRegBaseAddr : 0x%x, VdhRegSize : %d, SmmuPageBaseAddr : 0x%x, PERICRG_RegBaseAddr : 0x%x,range = 0x%x\n", __func__, + pDtsConfig->IsFPGA, pDtsConfig->VdecIrqNumNorm, pDtsConfig->VdecIrqNumProt, pDtsConfig->VdecIrqNumSafe, (pDtsConfig->VdhRegBaseAddr), pDtsConfig->VdhRegRange, (pDtsConfig->SmmuPageBaseAddr),(uintptr_t)(pDtsConfig->PERICRG_RegBaseAddr),pDtsConfig->VdhRegRange); + +#endif + return VDEC_OK; +} + +int VFMW_GetDtsConfig(VFMW_DTS_CONFIG_S *pDtsConfig) +{ + if (pDtsConfig == NULL) { + printk(KERN_ERR "%s FATAL: pDtsConfig is NULL\n", __func__); + return VDEC_ERR; + } + + pDtsConfig->IsFPGA = gIsFPGA; + pDtsConfig->VdecIrqNumNorm = gVdecIrqNumNorm; + pDtsConfig->VdecIrqNumProt = gVdecIrqNumProt; + pDtsConfig->VdecIrqNumSafe = gVdecIrqNumSafe; + + pDtsConfig->VdhRegBaseAddr = gVdhRegBaseAddr; + pDtsConfig->VdhRegRange = gVdhRegRange; + pDtsConfig->SmmuPageBaseAddr = gSmmuPageBase; + + pDtsConfig->PERICRG_RegBaseAddr = gPERICRG_RegBaseAddr; + + return VDEC_OK; +} + +#ifdef ENV_ARMLINUX_KERNEL +EXPORT_SYMBOL(VFMW_SetDtsConfig); +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.h new file mode 100755 index 000000000000..31ddb183542d --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_dts.h @@ -0,0 +1,8 @@ +#ifndef __VFMW_DTS_H__ +#define __VFMW_DTS_H__ +#include "vfmw.h" + +int VFMW_SetDtsConfig(VFMW_DTS_CONFIG_S *pDtsConfig); +int VFMW_GetDtsConfig(VFMW_DTS_CONFIG_S *pDtsConfig); + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.c b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.c new file mode 100755 index 000000000000..910dc67fef5d --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.c @@ -0,0 +1,376 @@ +/* + * vfmw interface + * + * Copyright (c) 2017 Hisilicon Limited + * + * Author: gaoyajun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation. + * + */ +#include +#include +#include + +//#include "public.h" +#include "vfmw_intf.h" + +#include "../omxvdec/omxvdec.h" +#ifdef HIVDEC_SMMU_SUPPORT +#include "smmu.h" +#endif +#include "./format/vdm_hal_api.h" +#include "vfmw_osal_ext.h" +#include "linux_kernel_osal.h" +#ifndef IRQF_DISABLED +#define IRQF_DISABLED (0x00000020) +#endif +#define VDM_TIMEOUT (400)//ms +#define VDM_FPGA_TIMEOUT (500000)//ms +#define SCD_TIMEOUT (400)//ms +#define SCD_FPGA_TIMEOUT (200000)//ms +#define SCEN_IDENT (0x828) +#define MAP_SIZE (256 * 1024) + +#define TIME_PERIOD(begin, end) ((end >= begin)? (end-begin):(0xffffffff - begin + end)) + +// cppcheck-suppress * +#define VCTRL_ASSERT_RET(cond, else_print) \ +do { \ + if (!(cond)) { \ + printk(KERN_ERR "%s %d %s\n", __func__, __LINE__, else_print ); \ + return VCTRL_ERR; \ + } \ +}while(0) + +static DRV_MEM_S g_RegsBaseAddr; + +Vfmw_Osal_Func_Ptr g_vfmw_osal_fun_ptr; + +void VCTRL_Suspend(void) +{ + unsigned char isScdSleep = 0; + unsigned char isVdmSleep = 0; + unsigned int SleepCount = 0; + unsigned int BeginTime, EntrTime, CurTime; + + EntrTime = VFMW_OSAL_GetTimeInMs(); + + SCDDRV_PrepareSleep(); + + VDMHAL_PrepareSleep(); + + BeginTime = VFMW_OSAL_GetTimeInMs(); + do { + if (SCDDRV_SLEEP_STAGE_SLEEP == SCDDRV_GetSleepStage()) + isScdSleep = 1; + + if (VDMHAL_GetSleepStage() == VDMDRV_SLEEP_STAGE_SLEEP) + isVdmSleep = 1; + + if ((isScdSleep == 1) && (isVdmSleep == 1)) { + break; + } else { + if (SleepCount > 30) { + if (isScdSleep != 1) { + printk(KERN_ERR "Force scd sleep\n"); + SCDDRV_ForceSleep(); + } + if (isVdmSleep != 1) { + printk(KERN_ERR "Force vdm sleep\n"); + VDMHAL_ForceSleep(); + } + break; + } + + VFMW_OSAL_mSleep(10); + SleepCount++; + } + } while ((isScdSleep != 1) || (isVdmSleep != 1)); + + CurTime = VFMW_OSAL_GetTimeInMs(); + printk(KERN_INFO "Vfmw suspend totally take %d ms\n", TIME_PERIOD(EntrTime, CurTime)); + + return; +} + +void VCTRL_Resume(void) +{ + unsigned int EntrTime, CurTime; + + EntrTime = VFMW_OSAL_GetTimeInMs(); + + SMMU_InitGlobalReg(); + + SCDDRV_ExitSleep(); + + VDMHAL_ExitSleep(); + + CurTime = VFMW_OSAL_GetTimeInMs(); + printk(KERN_INFO "Vfmw resume totally take %d ms\n", TIME_PERIOD(EntrTime, CurTime)); + + return; +} + +static int VCTRL_ISR(int irq, void *dev_id) +{ + unsigned int D32; + D32 = RD_SCDREG(REG_SCD_INI_CLR)&0x1; + if (D32 == 1) + SCDDRV_ISR(); + + RD_VREG(VREG_INT_STATE, D32, 0); + if (D32 == 1) + VDMHAL_ISR(0); + + return IRQ_HANDLED; +} + +static int VCTRL_RequestIrq(unsigned int IrqNumNorm, unsigned int IrqNumProt, unsigned int IrqNumSafe) +{ +#if !defined(VDM_BUSY_WAITTING) + if (VFMW_OSAL_RequestIrq(IrqNumNorm, VCTRL_ISR, IRQF_DISABLED, "vdec_norm_irq", NULL) != 0) { //for 2.6.24ÒÔºó + printk(KERN_ERR "Request vdec norm irq %d failed\n", IrqNumNorm); + return VCTRL_ERR; + } +#endif + return VCTRL_OK; +} + +static void VCTRL_FreeIrq(unsigned int IrqNumNorm, unsigned int IrqNumProt, unsigned int IrqNumSafe) +{ +#if !defined(VDM_BUSY_WAITTING) + VFMW_OSAL_FreeIrq(IrqNumNorm, NULL); +#endif +} + +static int VCTRL_HalInit(void) +{ +#ifdef HIVDEC_SMMU_SUPPORT + if (SMMU_Init() != SMMU_OK) { + printk(KERN_ERR "SMMU_Init failed\n"); + return VCTRL_ERR; + } +#endif + + SCDDRV_init(); + VDMHAL_IMP_Init(); + SMMU_InitGlobalReg(); + + return VCTRL_OK; +} + +static void VCTRL_HalDeInit(void) +{ +#ifdef HIVDEC_SMMU_SUPPORT + SMMU_DeInit(); +#endif + VDMHAL_IMP_DeInit(); + SCDDRV_DeInit(); +} + +int VCTRL_OpenDrivers(void) +{ + MEM_RECORD_S *pstMem; + int ret = VCTRL_ERR; + + pstMem = &g_RegsBaseAddr.stVdhReg; + if (MEM_MapRegisterAddr(gVdhRegBaseAddr, MAP_SIZE, pstMem) == MEM_MAN_OK) { + if (MEM_AddMemRecord(pstMem->PhyAddr, pstMem->VirAddr, pstMem->Length) != MEM_MAN_OK) { + printk(KERN_ERR "%s %d MEM_AddMemRecord failed\n", __func__, __LINE__); + goto exit; + } + } else { + printk(KERN_ERR "Map vdh register failed! gVdhRegBaseAddr : %pK, gVdhRegRange : %d\n", + (void *)(uintptr_t)gVdhRegBaseAddr, gVdhRegRange); + goto exit; + } + + ret = VCTRL_RequestIrq(gVdecIrqNumNorm, gVdecIrqNumProt, gVdecIrqNumSafe); + if (ret != VCTRL_OK) { + printk(KERN_ERR "VCTRL_RequestIrq failed\n"); + goto exit; + } + + if (VCTRL_HalInit() != VCTRL_OK) { + printk(KERN_ERR "VCTRL_HalInit failed\n"); + goto exit; + } + + VFMW_OSAL_InitEvent(G_SCDHWDONEEVENT, 0); + VFMW_OSAL_InitEvent(G_VDMHWDONEEVENT, 0); + + return VCTRL_OK; + +exit: + VCTRL_CloseVfmw(); + return VCTRL_ERR; +} + +int VCTRL_OpenVfmw(void) +{ + memset(&g_RegsBaseAddr, 0, sizeof(g_RegsBaseAddr)); /* unsafe_function_ignore: m +emset */ + + MEM_InitMemManager(); + if (VCTRL_OpenDrivers() != VCTRL_OK) { + printk(KERN_ERR "OpenDrivers fail\n"); + return VCTRL_ERR; + } + + return VCTRL_OK; +} + +int VCTRL_CloseVfmw(void) +{ + MEM_RECORD_S *pstMem; + + VCTRL_HalDeInit(); + + pstMem = &g_RegsBaseAddr.stVdhReg; + if (pstMem->Length != 0) { + MEM_UnmapRegisterAddr(pstMem->PhyAddr, pstMem->VirAddr, pstMem->Length); + MEM_DelMemRecord(pstMem->PhyAddr, pstMem->VirAddr, pstMem->Length); + memset(&g_RegsBaseAddr.stVdhReg, 0, sizeof(g_RegsBaseAddr.stVdhReg)); /* unsafe_function_ignore: m +emset */ + } + + VCTRL_FreeIrq(gVdecIrqNumNorm, gVdecIrqNumProt, gVdecIrqNumSafe); + + return VCTRL_OK; +} + +int VCTRL_VDMHal_Process(OMXVDH_REG_CFG_S *pVdmRegCfg, VDMHAL_BACKUP_S *pVdmRegState) +{ + int ret = HI_SUCCESS; + VDMDRV_SLEEP_STAGE_E sleepState; + + sleepState = VDMHAL_GetSleepStage(); + if (VDMDRV_SLEEP_STAGE_SLEEP == sleepState) { + printk(KERN_INFO "vdm sleep state\n"); + return HI_FAILURE; + } + + if (pVdmRegCfg->vdh_reset_flag) + VDMHAL_IMP_ResetVdm(0); + + VFMW_OSAL_InitEvent(G_VDMHWDONEEVENT, 0); + ret = VDMHAL_HwDecProc(pVdmRegCfg); + + if (ret) { + printk(KERN_ERR "%s config error\n", __func__); + } else { + ret = VFMW_OSAL_WaitEvent(G_VDMHWDONEEVENT, VDM_TIMEOUT); + if (ret == HI_SUCCESS) { + VDMHAL_GetRegState(pVdmRegState); + } else { + printk(KERN_ERR "VFMW_OSAL_WaitEvent wait time out\n"); + VDMHAL_IMP_ResetVdm(0); + } + } + + sleepState = VDMHAL_GetSleepStage(); + if (sleepState == VDMDRV_SLEEP_STAGE_PREPARE) + VDMHAL_SetSleepStage(VDMDRV_SLEEP_STAGE_SLEEP); + + return ret; +} + +int VCTRL_SCDHal_Process(OMXSCD_REG_CFG_S *pScdRegCfg,SCD_STATE_REG_S *pScdStateReg) +{ + int ret = HI_SUCCESS; + SCDDRV_SLEEP_STAGE_E sleepState; + CONFIG_SCD_CMD cmd = pScdRegCfg->cmd; + + sleepState = SCDDRV_GetSleepStage(); + if (SCDDRV_SLEEP_STAGE_SLEEP == sleepState) { + printk(KERN_INFO "SCD sleep state\n"); + return HI_FAILURE; + } + + if (pScdRegCfg->SResetFlag) { + if (SCDDRV_ResetSCD() != HI_SUCCESS) { + printk(KERN_ERR "VDEC_IOCTL_SCD_WAIT_HW_DONE Reset SCD failed\n"); + return HI_FAILURE; + } + } + + switch (cmd) { + case CONFIG_SCD_REG_CMD: + VFMW_OSAL_InitEvent(G_SCDHWDONEEVENT, 0); + ret = SCDDRV_WriteReg(&pScdRegCfg->SmCtrlReg ); + if (ret != HI_SUCCESS) { + printk(KERN_ERR "SCD busy\n"); + return HI_FAILURE; + } + + ret = VFMW_OSAL_WaitEvent(G_SCDHWDONEEVENT,SCD_TIMEOUT); + if (ret == HI_SUCCESS) { + SCDDRV_GetRegState(pScdStateReg); + } else { + printk(KERN_INFO "VDEC_IOCTL_SCD_WAIT_HW_DONE wait time out\n"); + SCDDRV_ResetSCD(); + } + + sleepState = SCDDRV_GetSleepStage(); + if (sleepState == SCDDRV_SLEEP_STAGE_PREPARE) { + SCDDRV_SetSleepStage(SCDDRV_SLEEP_STAGE_SLEEP); + } + break; + + default: + printk(KERN_ERR " cmd type unknown:%d\n", cmd); + return HI_FAILURE; + } + + return ret; +} + +int VCTRL_VDMHAL_IsRun(void) +{ + return VDMHAL_IsVdmRun(0); +} + +int VCTRL_Scen_Ident(unsigned int cmd) +{ + if ((RD_SCDREG(SCEN_IDENT) == 1) && (cmd != VDEC_IOCTL_SET_CLK_RATE)) + return 1; + + return 0; +} + +int VFMW_DRV_ModInit(void) +{ + OSAL_InitInterface(); + VFMW_OSAL_SemaInit(G_SCD_SEM); + VFMW_OSAL_SemaInit(G_VDH_SEM); + VFMW_OSAL_SemaInit(G_BPD_SEM); + + VFMW_OSAL_SpinLockInit(G_SPINLOCK_SCD); + VFMW_OSAL_SpinLockInit(G_SPINLOCK_VDH); + VFMW_OSAL_SpinLockInit(G_SPINLOCK_RECORD); + VFMW_OSAL_InitEvent(G_SCDHWDONEEVENT, 0); + VFMW_OSAL_InitEvent(G_VDMHWDONEEVENT, 0); + +#ifdef MODULE + printk(KERN_INFO "%s : Load hi_vfmw.ko (%d) success\n", __func__, VFMW_VERSION_NUM); +#endif + + return 0; +} + +void VFMW_DRV_ModExit(void) +{ +#ifdef MODULE + printk(KERN_INFO "%s : Unload hi_vfmw.ko (%d) success\n",__func__, VFMW_VERSION_NUM); +#endif + + return; +} + +module_init(VFMW_DRV_ModInit); +module_exit(VFMW_DRV_ModExit); + +MODULE_AUTHOR("gaoyajun"); +MODULE_LICENSE("GPL"); diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.h new file mode 100755 index 000000000000..2d5c24ef2495 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_intf.h @@ -0,0 +1,33 @@ +#ifndef __VFMW_INTF_H__ +#define __VFMW_INTF_H__ +//#include "../omxvdec/memory.h" +#include "./format/vdm_drv.h" +#include "scd_drv.h" + +#define VCTRL_OK 0 +#define VCTRL_ERR -1 +#define MSG_POOL_ADDR_CHECK + +typedef struct hiDRV_MEM_S { + MEM_RECORD_S stVdhReg; +} DRV_MEM_S; + +int VCTRL_OpenDrivers(void); + +int VCTRL_OpenVfmw(void); + +int VCTRL_CloseVfmw(void); + +int VCTRL_VDMHal_Process(OMXVDH_REG_CFG_S *pVdmRegCfg, VDMHAL_BACKUP_S *pVdmRegStatei); + +int VCTRL_SCDHal_Process(OMXSCD_REG_CFG_S *pScdRegCfg, SCD_STATE_REG_S *pScdStateReg); + +int VCTRL_VDMHAL_IsRun(void); + +void VCTRL_Suspend(void); + +void VCTRL_Resume(void); + +int VCTRL_Scen_Ident(unsigned int cmd); + +#endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_make.cfg b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_make.cfg new file mode 100755 index 000000000000..d4f0b52be146 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_make.cfg @@ -0,0 +1,147 @@ +################################################################################################ +# purpose: +# This file provide two vars: VFMW_CFLAGS, VFMW_CFILES +# VFMW_CFLAGS --- compile options for vfmw +# VFMW_CFILES --- specify the files to be compiled +############################################################################################### +VFMW_DIR := drivers/vcodec/vdec_hivna/vfmw_v4.0 + +VFMW_INC_DIR := $(VFMW_DIR) + +SCENE_DIR := kirin + +include $(VFMW_DIR)/vfmw_config.cfg + +#=============================================================================== +# options +#=============================================================================== +VFMW_CFLAGS := -DENV_ARMLINUX_KERNEL +VFMW_CFLAGS += -DSCD_MP4_SLICE_ENABLE +VFMW_CFLAGS += -DVFMW_EXTRA_TYPE_DEFINE +VFMW_CFLAGS += -DPRODUCT_KIRIN +VFMW_CFLAGS += -DQ_MATRIX_FIXED +VFMW_CFLAGS += -DPLATFORM_KIRIN970 + +ifneq ($(TARGET_BUILD_VARIANT),user) +VFMW_CFLAGS += -DUSER_DISABLE_VDEC_PROC +endif + +################ VDH_VERSION ############# +ifeq ($(VFMW_VDH_SUPPORT),YES) +VDH_DIR := format +VFMW_CFLAGS += -DVFMW_VDH_SUPPORT +endif +########################################## + +################ TEST OPTION ############ +#VFMW_CFLAGS += -DKTEST_VFMW_SLEEP +ifeq ($(VFMW_TEST),YES) +VFMW_CFLAGS += -DVFMW_KTEST +endif +########################################## + +################ SMMU VERSION ############ +ifeq ($(HIVDEC_SMMU_SUPPORT),YES) +VFMW_CFLAGS += -DHIVDEC_SMMU_SUPPORT +endif +########################################## + +#=============================================================================== +# include path +#=============================================================================== +VFMW_CFLAGS += -I$(VFMW_INC_DIR) + +#=============================================================================== +# VFMW_CFILES +#=============================================================================== +VFMW_CFILES := vfmw_dts.o +VFMW_CFILES += linux_kernel_osal.o \ + mem_manage.o \ + vfmw_intf.o \ + scd_drv.o + +#=============================================================================== +# vdh hal seclect +#=============================================================================== +VFMW_CFILES += $(VDH_DIR)/vdm_hal.o + +#=============================================================================== +# SMMU hal seclect +#=============================================================================== +ifeq ($(HIVDEC_SMMU_SUPPORT),YES) +VFMW_CFILES += smmu.o +endif + +#=============================================================================== +# vfmw video type support +#=============================================================================== +################# vfmw_h264 ################# +ifeq ($(VFMW_H264_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_H264_SUPPORT +VFMW_CFILES += $(VDH_DIR)/vdm_hal_h264.o +endif + +################# vfmw_hevc ################# +ifeq ($(VFMW_HEVC_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_HEVC_SUPPORT +VFMW_CFILES += /$(VDH_DIR)/vdm_hal_hevc.o +endif + +################# vfmw_mpeg2 ################# +ifeq ($(VFMW_MPEG2_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_MPEG2_SUPPORT +VFMW_CFILES += $(VDH_DIR)/vdm_hal_mpeg2.o +endif + +################# vfmw_mpeg4 ################# +ifeq ($(VFMW_MPEG4_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_MPEG4_SUPPORT +VFMW_CFILES += $(VDH_DIR)/vdm_hal_mpeg4.o +endif + +################# vfmw_bpd ################# +ifeq ($(VFMW_BPD_H_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_BPD_H_SUPPORT +endif + +################# vfmw_vp8 ################# +ifeq ($(VFMW_VP8_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_VP8_SUPPORT +VFMW_CFILES += $(VDH_DIR)/vdm_hal_vp8.o +endif + +################# vfmw_vp9 ################# +ifeq ($(VFMW_VP9_SUPPORT),YES) +VFMW_CFLAGS += -DVFMW_VP9_SUPPORT +VFMW_CFILES += $(VDH_DIR)/vdm_hal_vp9.o +endif + +################# vfmw_raw_num ################# +ifeq ($(VFMW_RAW_NUM_SUPPORT),YES) +VFMW_CFLAGS += -DCFG_MAX_RAW_NUM=$(VFMW_MAX_RAW_NUM) +endif + +################# vfmw_seg_num ################# +ifeq ($(VFMW_SEG_NUM_SUPPORT),YES) +VFMW_CFLAGS += -DCFG_MAX_SEG_NUM=$(VFMW_MAX_SEG_NUM) +endif + +################# vfmw_scd_msg_buffer ########## +ifeq ($(VFMW_SCD_MSG_SUPPORT),YES) +VFMW_CFLAGS += -DCFG_SCD_BUF=$(VFMW_SCD_MSG_BUF) +endif + +################# VFMW_SYSTEM_REG_DISABLE ####### +ifeq ($(VFMW_SYSTEM_REG_DISABLE),YES) +VFMW_CFLAGS += -DVFMW_SYSTEM_REG_DISABLE +endif + +################# CONSTRAINT_VDH_PERFORMANCE ####### +ifeq ($(CONSTRAINT_VDH_PERFORMANCE),YES) +VFMW_CFLAGS += -DCONSTRAINT_VDH_PERFORMANCE +endif + +################# TARGET_BOARD_PLATFORM############ +ifeq ($(TARGET_BOARD_PLATFORM), hi3660) +VFMW_CFLAGS +=-DPLATFORM_HI3660 +endif diff --git a/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_osal_ext.h b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_osal_ext.h new file mode 100755 index 000000000000..bfdd05928259 --- /dev/null +++ b/drivers/vcodec/vdec_hivna/vfmw_v4.0/vfmw_osal_ext.h @@ -0,0 +1,121 @@ + +#ifndef __VFMW_OSAL_EXT_HEADER__ +#define __VFMW_OSAL_EXT_HEADER__ + +#include "vfmw.h" +#include "mem_manage.h" + +#define OSAL_OK 0 +#define OSAL_ERR -1 + +typedef int(*OSAL_IRQ_HANDLER_t) (int, void *); + +typedef enum SpinLockType { + G_SPINLOCK_SCD = 0, + G_SPINLOCK_VDH, + G_SPINLOCK_RECORD, +} SpinLockType; + +typedef enum MutexType { + G_SCDHWDONEEVENT = 0, + G_VDMHWDONEEVENT, +} MutexType; + +typedef enum SemType { + G_SCD_SEM = 0, + G_VDH_SEM, + G_BPD_SEM, +} SemType; + +typedef unsigned int (*FN_OSAL_GetTimeInMs) (void); +typedef unsigned int (*FN_OSAL_GetTimeInUs) (void); +typedef void (*FN_OSAL_SpinLockInit) (SpinLockType); +typedef int (*FN_OSAL_SpinLock) (SpinLockType); +typedef int (*FN_OSAL_SpinUnlock) (SpinLockType); +typedef void (*FN_OSAL_SemaInit) (SemType); +typedef int (*FN_OSAL_SemaDown) (SemType); +typedef void (*FN_OSAL_SemaUp) (SemType); +typedef int (*FN_OSAL_Print) (const char *, ...); +typedef void (*FN_OSAL_Mb) (void); +typedef void (*FN_OSAL_uDelay) (unsigned long); +typedef void (*FN_OSAL_mSleep) (unsigned int); +typedef int (*FN_OSAL_InitEvent) (MutexType, int); +typedef int (*FN_OSAL_GiveEvent) (MutexType); +typedef int (*FN_OSAL_WaitEvent) (MutexType, int); +typedef int (*FN_OSAL_MemAlloc) (unsigned char *, unsigned int, unsigned int, unsigned int, MEM_DESC_S *); +typedef int (*FN_OSAL_MemFree) (MEM_DESC_S *); +typedef unsigned char *(*FN_OSAL_RegisterMap) (unsigned int, unsigned int); +typedef void (*FN_OSAL_RegisterUnMap) (unsigned char *, unsigned int); +typedef unsigned char *(*FN_OSAL_Mmap) (unsigned int, unsigned int); +typedef unsigned char *(*FN_OSAL_MmapCache) (unsigned int, unsigned int); +typedef void (*FN_OSAL_MunMap) (unsigned char *); +typedef int (*FN_OSAL_RequestIrq) (unsigned int, OSAL_IRQ_HANDLER_t, unsigned long, const char *, void *); +typedef void (*FN_OSAL_FreeIrq) (unsigned int, void *); +typedef void *(*FN_OSAL_AllocVirMem) (int); +typedef void (*FN_OSAL_FreeVirMem) (void *); +typedef int (*FN_OSAL_ProcInit) (void); +typedef void (*FN_OSAL_ProcExit) (void); + +typedef struct Vfmw_Osal_Func_Ptr { + FN_OSAL_GetTimeInMs pfun_Osal_GetTimeInMs; + FN_OSAL_GetTimeInUs pfun_Osal_GetTimeInUs; + FN_OSAL_SpinLockInit pfun_Osal_SpinLockInit; + FN_OSAL_SpinLock pfun_Osal_SpinLock; + FN_OSAL_SpinUnlock pfun_Osal_SpinUnLock; + FN_OSAL_SemaInit pfun_Osal_SemaInit; + FN_OSAL_SemaDown pfun_Osal_SemaDown; + FN_OSAL_SemaUp pfun_Osal_SemaUp; + FN_OSAL_Print pfun_Osal_Print; + FN_OSAL_Mb pfun_Osal_Mb; + FN_OSAL_uDelay pfun_Osal_uDelay; + FN_OSAL_mSleep pfun_Osal_mSleep; + FN_OSAL_InitEvent pfun_Osal_InitEvent; + FN_OSAL_GiveEvent pfun_Osal_GiveEvent; + FN_OSAL_WaitEvent pfun_Osal_WaitEvent; + FN_OSAL_RequestIrq pfun_Osal_RequestIrq; + FN_OSAL_FreeIrq pfun_Osal_FreeIrq; + FN_OSAL_MemAlloc pfun_Osal_MemAlloc; + FN_OSAL_MemFree pfun_Osal_MemFree; + FN_OSAL_RegisterMap pfun_Osal_RegisterMap; + FN_OSAL_RegisterUnMap pfun_Osal_RegisterUnMap; + FN_OSAL_Mmap pfun_Osal_Mmap; + FN_OSAL_MmapCache pfun_Osal_MmapCache; + FN_OSAL_MunMap pfun_Osal_MunMap; + FN_OSAL_AllocVirMem pfun_Osal_AllocVirMem; + FN_OSAL_FreeVirMem pfun_Osal_FreeVirMem; + FN_OSAL_ProcInit pfun_Osal_ProcInit; + FN_OSAL_ProcExit pfun_Osal_ProcExit; +} Vfmw_Osal_Func_Ptr; + +extern Vfmw_Osal_Func_Ptr g_vfmw_osal_fun_ptr; + +#define VFMW_OSAL_GetTimeInMs g_vfmw_osal_fun_ptr.pfun_Osal_GetTimeInMs +#define VFMW_OSAL_GetTimeInUs g_vfmw_osal_fun_ptr.pfun_Osal_GetTimeInUs +#define VFMW_OSAL_SpinLockInit g_vfmw_osal_fun_ptr.pfun_Osal_SpinLockInit +#define VFMW_OSAL_SpinLock g_vfmw_osal_fun_ptr.pfun_Osal_SpinLock +#define VFMW_OSAL_SpinUnLock g_vfmw_osal_fun_ptr.pfun_Osal_SpinUnLock +#define VFMW_OSAL_SemaInit g_vfmw_osal_fun_ptr.pfun_Osal_SemaInit +#define VFMW_OSAL_SemaDown g_vfmw_osal_fun_ptr.pfun_Osal_SemaDown +#define VFMW_OSAL_SemaUp g_vfmw_osal_fun_ptr.pfun_Osal_SemaUp +#define VFMW_OSAL_Print g_vfmw_osal_fun_ptr.pfun_Osal_Print +#define VFMW_OSAL_Mb g_vfmw_osal_fun_ptr.pfun_Osal_Mb +#define VFMW_OSAL_uDelay g_vfmw_osal_fun_ptr.pfun_Osal_uDelay +#define VFMW_OSAL_mSleep g_vfmw_osal_fun_ptr.pfun_Osal_mSleep +#define VFMW_OSAL_InitEvent g_vfmw_osal_fun_ptr.pfun_Osal_InitEvent +#define VFMW_OSAL_GiveEvent g_vfmw_osal_fun_ptr.pfun_Osal_GiveEvent +#define VFMW_OSAL_WaitEvent g_vfmw_osal_fun_ptr.pfun_Osal_WaitEvent +#define VFMW_OSAL_RequestIrq g_vfmw_osal_fun_ptr.pfun_Osal_RequestIrq +#define VFMW_OSAL_FreeIrq g_vfmw_osal_fun_ptr.pfun_Osal_FreeIrq +#define VFMW_OSAL_MemAlloc g_vfmw_osal_fun_ptr.pfun_Osal_MemAlloc +#define VFMW_OSAL_MemFree g_vfmw_osal_fun_ptr.pfun_Osal_MemFree +#define VFMW_OSAL_RegisterMap g_vfmw_osal_fun_ptr.pfun_Osal_RegisterMap +#define VFMW_OSAL_RegisterUnMap g_vfmw_osal_fun_ptr.pfun_Osal_RegisterUnMap +#define VFMW_OSAL_Mmap g_vfmw_osal_fun_ptr.pfun_Osal_Mmap +#define VFMW_OSAL_MmapCache g_vfmw_osal_fun_ptr.pfun_Osal_MmapCache +#define VFMW_OSAL_MunMap g_vfmw_osal_fun_ptr.pfun_Osal_MunMap +#define VFMW_OSAL_AllocVirMem g_vfmw_osal_fun_ptr.pfun_Osal_AllocVirMem +#define VFMW_OSAL_FreeVirMem g_vfmw_osal_fun_ptr.pfun_Osal_FreeVirMem +#define VFMW_OSAL_ProcInit g_vfmw_osal_fun_ptr.pfun_Osal_ProcInit +#define VFMW_OSAL_ProcExit g_vfmw_osal_fun_ptr.pfun_Osal_ProcExit + +#endif diff --git a/drivers/vcodec/venc_hivna/Kconfig b/drivers/vcodec/venc_hivna/Kconfig new file mode 100755 index 000000000000..4cf97c48ddf3 --- /dev/null +++ b/drivers/vcodec/venc_hivna/Kconfig @@ -0,0 +1,8 @@ +menu "Hisilicon video venc support" +config HI_VCODEC_VENC + #depends on ANDROID_PMEM + tristate "Support for venc" + default n + help + The decode device provides venc function +endmenu diff --git a/drivers/vcodec/venc_hivna/Makefile b/drivers/vcodec/venc_hivna/Makefile new file mode 100755 index 000000000000..1bd6edbd8c50 --- /dev/null +++ b/drivers/vcodec/venc_hivna/Makefile @@ -0,0 +1,16 @@ +# Add your debugging flag (or not) to CFLAGS +include drivers/vcodec/venc_hivna/drv_venc_make.cfg + +EXTRA_CFLAGS += $(VENC_CFLAGS) -fno-pic +EXTRA_CFLAGS += -Idrivers/vcodec/venc_hivna +EXTRA_CFLAGS += -DPLATFORM_KIRIN970 + +obj-$(CONFIG_HI_VCODEC_VENC) += hi_omxvenc.o +hi_omxvenc-objs := venc_regulator.o \ + drv_venc_intf.o \ + drv_venc_efl.o \ + drv_venc_osal.o \ + drv_venc.o \ + hal_venc.o \ + hi_drv_mem.o + diff --git a/drivers/vcodec/venc_hivna/Vedu_RegAll_Kirin970.h b/drivers/vcodec/venc_hivna/Vedu_RegAll_Kirin970.h new file mode 100755 index 000000000000..daf793d41243 --- /dev/null +++ b/drivers/vcodec/venc_hivna/Vedu_RegAll_Kirin970.h @@ -0,0 +1,12728 @@ +//****************************************************************************** +// Copyright (C), 2007-2016, Hisilicon Technologies Co., Ltd. +// +//****************************************************************************** +// File name : c_union_define.h +// Version : 2.0 +// Author : m00198177 +// Created : 2016-10-31 +// Last Modified : +// Description : ±àÂëÆ÷¼Ä´æÆ÷½á¹¹Ìå +// Function List : +// History : +// 1 Date : +// Author : m00198177 +// Modification : Create file +//****************************************************************************** +#ifndef __C_UNION_DEFINE_VEDU_REG_KIRIN970_H__ +#define __C_UNION_DEFINE_VEDU_REG_KIRIN970_H__ + + +typedef enum { + YUV420_SEMIPLANAR = 0, + YUV420_PLANAR = 3, + YUV422_PLANAR = 4, + YUV422_PACKAGE = 6, + RGB_32BIT = 8, + YUV420_SEMIPLANAR_CMP = 10, +} COLOR_FMT_TYPE; + + +/* Define the union U_VEDU_VCPI_INTMASK */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_enable_ve_eop : 1 ; /* [0] */ + unsigned int vcpi_enable_vedu_slice_end : 1 ; /* [1] */ + unsigned int vcpi_enable_ve_buffull : 1 ; /* [2] */ + unsigned int vcpi_enable_ve_pbitsover : 1 ; /* [3] */ + unsigned int vcpi_enable_vedu_brkpt : 1 ; /* [4] */ + unsigned int vcpi_enable_vedu_step : 1 ; /* [5] */ + unsigned int vcpi_enable_vedu_timeout : 1 ; /* [6] */ + unsigned int vcpi_enable_cfg_err : 1 ; /* [7] */ + unsigned int Reserved_0 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTMASK; + +/* Define the union U_VEDU_VCPI_INTCLR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_clr_ve_eop : 1 ; /* [0] */ + unsigned int vcpi_clr_vedu_slice_end : 1 ; /* [1] */ + unsigned int vcpi_clr_ve_buffull : 1 ; /* [2] */ + unsigned int vcpi_clr_ve_pbitsover : 1 ; /* [3] */ + unsigned int vcpi_clr_vedu_brkpt : 1 ; /* [4] */ + unsigned int vcpi_clr_vedu_step : 1 ; /* [5] */ + unsigned int vcpi_clr_vedu_timeout : 1 ; /* [6] */ + unsigned int vcpi_clr_cfg_err : 1 ; /* [7] */ + unsigned int Reserved_1 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTCLR; + +/* Define the union U_VEDU_VCPI_START */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_vstart : 1 ; /* [0] */ + unsigned int Reserved_3 : 15 ; /* [15..1] */ + unsigned int vcpi_vstep : 1 ; /* [16] */ + unsigned int Reserved_2 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_START; + +/* Define the union U_VEDU_VCPI_CNTCLR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_cnt_clr : 1 ; /* [0] */ + unsigned int vctrl_cnt_clr : 1 ; /* [1] */ + unsigned int curld_cnt_clr : 1 ; /* [2] */ + unsigned int pme_cnt_clr : 1 ; /* [3] */ + unsigned int refld_cnt_clr : 1 ; /* [4] */ + unsigned int ime_cnt_clr : 1 ; /* [5] */ + unsigned int pintra_cnt_clr : 1 ; /* [6] */ + unsigned int mrg_cnt_clr : 1 ; /* [7] */ + unsigned int fme_cnt_clr : 1 ; /* [8] */ + unsigned int intra_cnt_clr : 1 ; /* [9] */ + unsigned int pmv_cnt_clr : 1 ; /* [10] */ + unsigned int tqitq_cnt_clr : 1 ; /* [11] */ + unsigned int sel_cnt_clr : 1 ; /* [12] */ + unsigned int dblk_cnt_clr : 1 ; /* [13] */ + unsigned int sao_cnt_clr : 1 ; /* [14] */ + unsigned int pack_cnt_clr : 1 ; /* [15] */ + unsigned int cabac_cnt_clr : 1 ; /* [16] */ + unsigned int pmeld_cnt_clr : 1 ; /* [17] */ + unsigned int pmest_cnt_clr : 1 ; /* [18] */ + unsigned int nbi_cnt_clr : 1 ; /* [19] */ + unsigned int lfldst_cnt_clr : 1 ; /* [20] */ + unsigned int recst_cnt_clr : 1 ; /* [21] */ + unsigned int csst_cnt_clr : 1 ; /* [22] */ + unsigned int qpg_cnt_clr : 1 ; /* [23] */ + unsigned int Reserved_4 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_CNTCLR; + +/* Define the union U_VEDU_VCPI_BP_POS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bp_lcu_x : 9 ; /* [8..0] */ + unsigned int Reserved_6 : 7 ; /* [15..9] */ + unsigned int vcpi_bp_lcu_y : 9 ; /* [24..16] */ + unsigned int Reserved_5 : 5 ; /* [29..25] */ + unsigned int vcpi_bkp_en : 1 ; /* [30] */ + unsigned int vcpi_dbgmod : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BP_POS; + +/* Define the union U_VEDU_VCPI_MODE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_vedsel : 1 ; /* [0] */ + unsigned int vcpi_lcu_time_sel : 1 ; /* [1] */ + unsigned int vcpi_protocol : 2 ; /* [3..2] */ + unsigned int vcpi_cfg_mode : 1 ; /* [4] */ + unsigned int vcpi_slice_int_en : 1 ; /* [5] */ + unsigned int vcpi_sao_luma : 1 ; /* [6] */ + unsigned int vcpi_sao_chroma : 1 ; /* [7] */ + unsigned int vcpi_rec_cmp_en : 1 ; /* [8] */ + unsigned int vcpi_img_improve_en : 1 ; /* [9] */ + unsigned int vcpi_frame_type : 2 ; /* [11..10] */ + unsigned int vcpi_entropy_mode : 1 ; /* [12] */ + unsigned int vcpi_long_term_refpic : 1 ; /* [13] */ + unsigned int vcpi_ref_num : 1 ; /* [14] */ + unsigned int vcpi_2line_paral_enc : 1 ; /* [15] */ + unsigned int vcpi_idr_pic : 1 ; /* [16] */ + unsigned int vcpi_pskip_en : 1 ; /* [17] */ + unsigned int vcpi_trans_mode : 2 ; /* [19..18] */ + unsigned int vcpi_blk8_inter : 1 ; /* [20] */ + unsigned int vcpi_sobel_weight_en : 1 ; /* [21] */ + unsigned int vcpi_high_speed_en : 1 ; /* [22] */ + unsigned int vcpi_tiles_en : 1 ; /* [23] */ + unsigned int vcpi_10bit_mode : 2 ; /* [25..24] */ + unsigned int vcpi_lcu_size : 2 ; /* [27..26] */ + unsigned int vcpi_time_en : 2 ; /* [29..28] */ + unsigned int vcpi_ref_cmp_en : 1 ; /* [30] */ + unsigned int vcpi_refc_nload : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_MODE; + +/* Define the union U_VEDU_VCPI_TILE_SIZE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_tile_width : 9 ; /* [8..0] */ + unsigned int Reserved_8 : 7 ; /* [15..9] */ + unsigned int vcpi_tile_height : 9 ; /* [24..16] */ + unsigned int Reserved_7 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_TILE_SIZE; + +/* Define the union U_VEDU_VCPI_PICSIZE_PIX */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_imgwidth_pix : 13 ; /* [12..0] */ + unsigned int Reserved_10 : 3 ; /* [15..13] */ + unsigned int vcpi_imgheight_pix : 13 ; /* [28..16] */ + unsigned int Reserved_9 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PICSIZE_PIX; + +/* Define the union U_VEDU_VCPI_MULTISLC */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_slice_size : 16 ; /* [15..0] */ + unsigned int vcpi_slcspilt_mod : 1 ; /* [16] */ + unsigned int vcpi_multislc_en : 1 ; /* [17] */ + unsigned int Reserved_11 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_MULTISLC; + +/* Define the union U_VEDU_VCPI_QPCFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_cr_qp_offset : 5 ; /* [4..0] */ + unsigned int vcpi_cb_qp_offset : 5 ; /* [9..5] */ + unsigned int vcpi_frm_qp : 6 ; /* [15..10] */ + unsigned int Reserved_14 : 1 ; /* [16] */ + unsigned int Reserved_13 : 1 ; /* [17] */ + unsigned int vcpi_intra_det_qp_en : 1 ; /* [18] */ + unsigned int vcpi_rc_cu_madi_en : 1 ; /* [19] */ + unsigned int Reserved_12 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_QPCFG; + +/* Define the union U_VEDU_VCPI_DBLKCFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_dblk_beta : 4 ; /* [3..0] */ + unsigned int vcpi_dblk_alpha : 4 ; /* [7..4] */ + unsigned int vcpi_dblk_filter_flag : 2 ; /* [9..8] */ + unsigned int Reserved_15 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_DBLKCFG; + +/* Define the union U_VEDU_VCPI_LOW_POWER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_intra_lowpow_en : 1 ; /* [0] */ + unsigned int vcpi_fme_lowpow_en : 1 ; /* [1] */ + unsigned int vcpi_ime_lowpow_en : 1 ; /* [2] */ + unsigned int Reserved_18 : 1 ; /* [3] */ + unsigned int vcpi_ddr_cross_idx : 11 ; /* [14..4] */ + unsigned int Reserved_17 : 1 ; /* [15] */ + unsigned int vcpi_tqitq_gtck_en : 1 ; /* [16] */ + unsigned int vcpi_mrg_gtck_en : 1 ; /* [17] */ + unsigned int vcpi_fme_gtck_en : 1 ; /* [18] */ + unsigned int vcpi_clkgate_en : 2 ; /* [20..19] */ + unsigned int vcpi_mem_clkgate_en : 1 ; /* [21] */ + unsigned int vcpi_hfbc_clkgate_en : 1 ; /* [22] */ + unsigned int vcpi_ddr_cross_en : 1 ; /* [23] */ + unsigned int vcpi_10bit_addr_mode : 2 ; /* [25..24] */ + unsigned int Reserved_16 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_LOW_POWER; + +/* Define the union U_VEDU_VCPI_OUTSTD */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_r_outstanding : 5 ; /* [4..0] */ + unsigned int Reserved_20 : 3 ; /* [7..5] */ + unsigned int vcpi_w_outstanding : 5 ; /* [12..8] */ + unsigned int Reserved_19 : 19 ; /* [31..13] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OUTSTD; + +/* Define the union U_VEDU_VCPI_TMV_LOAD */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_tmv_wr_rd_avail : 2 ; /* [1..0] */ + unsigned int Reserved_21 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_TMV_LOAD; + +/* Define the union U_VEDU_VCPI_CROSS_TILE_SLC */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_cross_slice : 1 ; /* [0] */ + unsigned int vcpi_cross_tile : 1 ; /* [1] */ + unsigned int Reserved_22 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_CROSS_TILE_SLC; + +/* Define the union U_VEDU_VCPI_MEM_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ema : 3 ; /* [2..0] */ + unsigned int vcpi_emaw : 2 ; /* [4..3] */ + unsigned int vcpi_emaa : 3 ; /* [7..5] */ + unsigned int vcpi_emab : 3 ; /* [10..8] */ + unsigned int Reserved_23 : 21 ; /* [31..11] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_MEM_CTRL; + +/* Define the union U_VEDU_VCPI_INTRA_INTER_CU_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_intra_cu_en : 4 ; /* [3..0] */ + unsigned int vcpi_ipcm_en : 1 ; /* [4] */ + unsigned int vcpi_intra_h264_cutdiag : 1 ; /* [5] */ + unsigned int Reserved_25 : 2 ; /* [7..6] */ + unsigned int vcpi_fme_cu_en : 4 ; /* [11..8] */ + unsigned int vcpi_mrg_cu_en : 4 ; /* [15..12] */ + unsigned int Reserved_24 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTRA_INTER_CU_EN; + +/* Define the union U_VEDU_VCPI_VLC_CONFIG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ref_idc : 2 ; /* [1..0] */ + unsigned int Reserved_28 : 2 ; /* [3..2] */ + unsigned int vcpi_cabac_init_idc : 2 ; /* [5..4] */ + unsigned int Reserved_27 : 6 ; /* [11..6] */ + unsigned int vcpi_byte_stuffing : 1 ; /* [12] */ + unsigned int Reserved_26 : 19 ; /* [31..13] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_VLC_CONFIG; + +/* Define the union U_VEDU_VCPI_PRE_JUDGE_EXT_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_iblk_pre_en : 1 ; /* [0] */ + unsigned int vcpi_pblk_pre_en : 1 ; /* [1] */ + unsigned int vcpi_force_inter : 1 ; /* [2] */ + unsigned int vcpi_pintra_inter_flag_disable : 1 ; /* [3] */ + unsigned int vcpi_ext_edge_en : 1 ; /* [4] */ + unsigned int Reserved_29 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PRE_JUDGE_EXT_EN; + +/* Define the union U_VEDU_VCPI_PRE_JUDGE_COST_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_iblk_pre_cost_thr : 16 ; /* [15..0] */ + unsigned int vcpi_pblk_pre_cost_thr : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PRE_JUDGE_COST_THR; + +/* Define the union U_VEDU_VCPI_IBLK_PRE_MV_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_iblk_pre_mv_dif_thr0 : 8 ; /* [7..0] */ + unsigned int vcpi_iblk_pre_mv_dif_thr1 : 8 ; /* [15..8] */ + unsigned int vcpi_iblk_pre_mvx_thr : 8 ; /* [23..16] */ + unsigned int vcpi_iblk_pre_mvy_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_IBLK_PRE_MV_THR; + +/* Define the union U_VEDU_VCPI_PME_PARAM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_31 : 1 ; /* [0] */ + unsigned int vcpi_move_sad_en : 1 ; /* [1] */ + unsigned int Reserved_30 : 14 ; /* [15..2] */ + unsigned int vcpi_pblk_pre_mvx_thr : 8 ; /* [23..16] */ + unsigned int vcpi_pblk_pre_mvy_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PME_PARAM; + +/* Define the union U_VEDU_VCPI_PIC_STRONG_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_skin_en : 1 ; /* [0] */ + unsigned int vcpi_strong_edge_en : 1 ; /* [1] */ + unsigned int vcpi_still_en : 1 ; /* [2] */ + unsigned int vcpi_skin_close_angle : 1 ; /* [3] */ + unsigned int vcpi_rounding_sobel_en : 1 ; /* [4] */ + unsigned int Reserved_32 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PIC_STRONG_EN; + +/* Define the union U_VEDU_VCPI_REF_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_34 : 1 ; /* [0] */ + unsigned int vcpi_col_from_l0_flag : 1 ; /* [1] */ + unsigned int vcpi_curr_ref_long_flag : 2 ; /* [3..2] */ + unsigned int vcpi_col_long_flag : 2 ; /* [5..4] */ + unsigned int vcpi_predflag_sel : 2 ; /* [7..6] */ + unsigned int Reserved_33 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REF_FLAG; + +/* Define the union U_VEDU_VCPI_RC_ENABLE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rc_cu_qp_en : 1 ; /* [0] */ + unsigned int vcpi_rc_row_qp_en : 1 ; /* [1] */ + unsigned int vcpi_move_scene_en : 1 ; /* [2] */ + unsigned int Reserved_38 : 1 ; /* [3] */ + unsigned int vcpi_strong_edge_move_en : 1 ; /* [4] */ + unsigned int Reserved_37 : 1 ; /* [5] */ + unsigned int Reserved_36 : 2 ; /* [7..6] */ + unsigned int vcpi_rc_low_luma_en : 1 ; /* [8] */ + unsigned int vcpi_rc_h264_smooth_mb_en : 1 ; /* [9] */ + unsigned int vcpi_rd_smooth_mb_en : 1 ; /* [10] */ + unsigned int vcpi_rd_min_sad_flag_en : 1 ; /* [11] */ + unsigned int vcpi_wr_min_sad_flag_en : 1 ; /* [12] */ + unsigned int vcpi_high_min_sad_en : 1 ; /* [13] */ + unsigned int vcpi_low_min_sad_en : 1 ; /* [14] */ + unsigned int vcpi_prev_min_sad_en : 1 ; /* [15] */ + unsigned int vcpi_qpgld_en : 1 ; /* [16] */ + unsigned int vcpi_map_roikeep_en : 1 ; /* [17] */ + unsigned int vcpi_flat_region_en : 1 ; /* [18] */ + unsigned int vcpi_qp_restrain_large_sad : 1 ; /* [19] */ + unsigned int Reserved_35 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_RC_ENABLE; + +/* Define the union U_VEDU_VCPI_PINTRA_THRESH0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_pintra_pu16_amp_th : 8 ; /* [7..0] */ + unsigned int vcpi_pintra_pu32_amp_th : 8 ; /* [15..8] */ + unsigned int vcpi_pintra_pu64_amp_th : 8 ; /* [23..16] */ + unsigned int Reserved_39 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PINTRA_THRESH0; + +/* Define the union U_VEDU_VCPI_PINTRA_THRESH1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_pintra_pu16_std_th : 8 ; /* [7..0] */ + unsigned int vcpi_pintra_pu32_std_th : 8 ; /* [15..8] */ + unsigned int Reserved_40 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PINTRA_THRESH1; + +/* Define the union U_VEDU_VCPI_PINTRA_THRESH2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_pintra_pu16_angel_cost_th : 10 ; /* [9..0] */ + unsigned int vcpi_pintra_pu32_angel_cost_th : 10 ; /* [19..10] */ + unsigned int Reserved_41 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_PINTRA_THRESH2; + +/* Define the union U_VEDU_VCPI_I_SLC_INSERT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_insert_i_slc_idx : 8 ; /* [7..0] */ + unsigned int vcpi_insert_i_slc_en : 1 ; /* [8] */ + unsigned int Reserved_42 : 23 ; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_I_SLC_INSERT; + +/* Define the union U_VEDU_VCPI_CLKDIV_ENABLE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_clkdiv_en : 1 ; /* [0] */ + unsigned int Reserved_44 : 15 ; /* [15..1] */ + unsigned int vcpi_down_freq_en : 1 ; /* [16] */ + unsigned int Reserved_43 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_CLKDIV_ENABLE; + +/* Define the union U_VEDU_VCPI_OSD_ENABLE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd0_en : 1 ; /* [0] */ + unsigned int vcpi_osd1_en : 1 ; /* [1] */ + unsigned int vcpi_osd2_en : 1 ; /* [2] */ + unsigned int vcpi_osd3_en : 1 ; /* [3] */ + unsigned int vcpi_osd4_en : 1 ; /* [4] */ + unsigned int vcpi_osd5_en : 1 ; /* [5] */ + unsigned int vcpi_osd6_en : 1 ; /* [6] */ + unsigned int vcpi_osd7_en : 1 ; /* [7] */ + unsigned int vcpi_osd0_absqp : 1 ; /* [8] */ + unsigned int vcpi_osd1_absqp : 1 ; /* [9] */ + unsigned int vcpi_osd2_absqp : 1 ; /* [10] */ + unsigned int vcpi_osd3_absqp : 1 ; /* [11] */ + unsigned int vcpi_osd4_absqp : 1 ; /* [12] */ + unsigned int vcpi_osd5_absqp : 1 ; /* [13] */ + unsigned int vcpi_osd6_absqp : 1 ; /* [14] */ + unsigned int vcpi_osd7_absqp : 1 ; /* [15] */ + unsigned int vcpi_roi_osd_sel_0 : 1 ; /* [16] */ + unsigned int vcpi_roi_osd_sel_1 : 1 ; /* [17] */ + unsigned int vcpi_roi_osd_sel_2 : 1 ; /* [18] */ + unsigned int vcpi_roi_osd_sel_3 : 1 ; /* [19] */ + unsigned int vcpi_roi_osd_sel_4 : 1 ; /* [20] */ + unsigned int vcpi_roi_osd_sel_5 : 1 ; /* [21] */ + unsigned int vcpi_roi_osd_sel_6 : 1 ; /* [22] */ + unsigned int vcpi_roi_osd_sel_7 : 1 ; /* [23] */ + unsigned int vcpi_osd_en : 1 ; /* [24] */ + unsigned int Reserved_45 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_ENABLE; + +/* Define the union U_VEDU_VCPI_OSD_POS_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd0_x : 13 ; /* [12..0] */ + unsigned int Reserved_47 : 3 ; /* [15..13] */ + unsigned int vcpi_osd0_y : 13 ; /* [28..16] */ + unsigned int Reserved_46 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_0; + +/* Define the union U_VEDU_VCPI_OSD_POS_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd1_x : 13 ; /* [12..0] */ + unsigned int Reserved_49 : 3 ; /* [15..13] */ + unsigned int vcpi_osd1_y : 13 ; /* [28..16] */ + unsigned int Reserved_48 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_1; + +/* Define the union U_VEDU_VCPI_OSD_POS_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd2_x : 13 ; /* [12..0] */ + unsigned int Reserved_51 : 3 ; /* [15..13] */ + unsigned int vcpi_osd2_y : 13 ; /* [28..16] */ + unsigned int Reserved_50 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_2; + +/* Define the union U_VEDU_VCPI_OSD_POS_3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd3_x : 13 ; /* [12..0] */ + unsigned int Reserved_53 : 3 ; /* [15..13] */ + unsigned int vcpi_osd3_y : 13 ; /* [28..16] */ + unsigned int Reserved_52 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_3; + +/* Define the union U_VEDU_VCPI_OSD_POS_4 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd4_x : 13 ; /* [12..0] */ + unsigned int Reserved_55 : 3 ; /* [15..13] */ + unsigned int vcpi_osd4_y : 13 ; /* [28..16] */ + unsigned int Reserved_54 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_4; + +/* Define the union U_VEDU_VCPI_OSD_POS_5 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd5_x : 13 ; /* [12..0] */ + unsigned int Reserved_57 : 3 ; /* [15..13] */ + unsigned int vcpi_osd5_y : 13 ; /* [28..16] */ + unsigned int Reserved_56 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_5; + +/* Define the union U_VEDU_VCPI_OSD_POS_6 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd6_x : 13 ; /* [12..0] */ + unsigned int Reserved_59 : 3 ; /* [15..13] */ + unsigned int vcpi_osd6_y : 13 ; /* [28..16] */ + unsigned int Reserved_58 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_6; + +/* Define the union U_VEDU_VCPI_OSD_POS_7 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd7_x : 13 ; /* [12..0] */ + unsigned int Reserved_61 : 3 ; /* [15..13] */ + unsigned int vcpi_osd7_y : 13 ; /* [28..16] */ + unsigned int Reserved_60 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_POS_7; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd0_w : 13 ; /* [12..0] */ + unsigned int Reserved_63 : 3 ; /* [15..13] */ + unsigned int vcpi_osd0_h : 13 ; /* [28..16] */ + unsigned int Reserved_62 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_0; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd1_w : 13 ; /* [12..0] */ + unsigned int Reserved_65 : 3 ; /* [15..13] */ + unsigned int vcpi_osd1_h : 13 ; /* [28..16] */ + unsigned int Reserved_64 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_1; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd2_w : 13 ; /* [12..0] */ + unsigned int Reserved_67 : 3 ; /* [15..13] */ + unsigned int vcpi_osd2_h : 13 ; /* [28..16] */ + unsigned int Reserved_66 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_2; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd3_w : 13 ; /* [12..0] */ + unsigned int Reserved_69 : 3 ; /* [15..13] */ + unsigned int vcpi_osd3_h : 13 ; /* [28..16] */ + unsigned int Reserved_68 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_3; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_4 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd4_w : 13 ; /* [12..0] */ + unsigned int Reserved_71 : 3 ; /* [15..13] */ + unsigned int vcpi_osd4_h : 13 ; /* [28..16] */ + unsigned int Reserved_70 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_4; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_5 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd5_w : 13 ; /* [12..0] */ + unsigned int Reserved_73 : 3 ; /* [15..13] */ + unsigned int vcpi_osd5_h : 13 ; /* [28..16] */ + unsigned int Reserved_72 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_5; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_6 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd6_w : 13 ; /* [12..0] */ + unsigned int Reserved_75 : 3 ; /* [15..13] */ + unsigned int vcpi_osd6_h : 13 ; /* [28..16] */ + unsigned int Reserved_74 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_6; + +/* Define the union U_VEDU_VCPI_OSD_SIZE_7 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd7_w : 13 ; /* [12..0] */ + unsigned int Reserved_77 : 3 ; /* [15..13] */ + unsigned int vcpi_osd7_h : 13 ; /* [28..16] */ + unsigned int Reserved_76 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_SIZE_7; + +/* Define the union U_VEDU_VCPI_OSD_LAYERID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd0_layer_id : 3 ; /* [2..0] */ + unsigned int Reserved_85 : 1 ; /* [3] */ + unsigned int vcpi_osd1_layer_id : 3 ; /* [6..4] */ + unsigned int Reserved_84 : 1 ; /* [7] */ + unsigned int vcpi_osd2_layer_id : 3 ; /* [10..8] */ + unsigned int Reserved_83 : 1 ; /* [11] */ + unsigned int vcpi_osd3_layer_id : 3 ; /* [14..12] */ + unsigned int Reserved_82 : 1 ; /* [15] */ + unsigned int vcpi_osd4_layer_id : 3 ; /* [18..16] */ + unsigned int Reserved_81 : 1 ; /* [19] */ + unsigned int vcpi_osd5_layer_id : 3 ; /* [22..20] */ + unsigned int Reserved_80 : 1 ; /* [23] */ + unsigned int vcpi_osd6_layer_id : 3 ; /* [26..24] */ + unsigned int Reserved_79 : 1 ; /* [27] */ + unsigned int vcpi_osd7_layer_id : 3 ; /* [30..28] */ + unsigned int Reserved_78 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_LAYERID; + +/* Define the union U_VEDU_VCPI_OSD_QP0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd0_qp : 7 ; /* [6..0] */ + unsigned int Reserved_89 : 1 ; /* [7] */ + unsigned int vcpi_osd1_qp : 7 ; /* [14..8] */ + unsigned int Reserved_88 : 1 ; /* [15] */ + unsigned int vcpi_osd2_qp : 7 ; /* [22..16] */ + unsigned int Reserved_87 : 1 ; /* [23] */ + unsigned int vcpi_osd3_qp : 7 ; /* [30..24] */ + unsigned int Reserved_86 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_QP0; + +/* Define the union U_VEDU_VCPI_OSD_QP1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_osd4_qp : 7 ; /* [6..0] */ + unsigned int Reserved_93 : 1 ; /* [7] */ + unsigned int vcpi_osd5_qp : 7 ; /* [14..8] */ + unsigned int Reserved_92 : 1 ; /* [15] */ + unsigned int vcpi_osd6_qp : 7 ; /* [22..16] */ + unsigned int Reserved_91 : 1 ; /* [23] */ + unsigned int vcpi_osd7_qp : 7 ; /* [30..24] */ + unsigned int Reserved_90 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_OSD_QP1; + +/* Define the union U_VEDU_VCPI_SW_L0_SIZE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_sw_l0_width : 7 ; /* [6..0] */ + unsigned int Reserved_95 : 9 ; /* [15..7] */ + unsigned int vcpi_sw_l0_height : 6 ; /* [21..16] */ + unsigned int Reserved_94 : 10 ; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_SW_L0_SIZE; + +/* Define the union U_VEDU_VCPI_SW_L1_SIZE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_sw_l1_width : 7 ; /* [6..0] */ + unsigned int Reserved_97 : 9 ; /* [15..7] */ + unsigned int vcpi_sw_l1_height : 6 ; /* [21..16] */ + unsigned int Reserved_96 : 10 ; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_SW_L1_SIZE; + +/* Define the union U_VEDU_VCPI_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_curld_c_stride : 16 ; /* [15..0] */ + unsigned int vcpi_curld_y_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_STRIDE; + +/* Define the union U_VEDU_VCPI_REC_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_recst_ystride : 16 ; /* [15..0] */ + unsigned int vcpi_recst_cstride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REC_STRIDE; + +/* Define the union U_VEDU_VCPI_REC_HEAD_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_recst_ch_stride : 16 ; /* [15..0] */ + unsigned int vcpi_recst_yh_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REC_HEAD_STRIDE; + +/* Define the union U_VEDU_VCPI_REF_L0_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_refc_l0_stride : 16 ; /* [15..0] */ + unsigned int vcpi_refy_l0_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REF_L0_STRIDE; + +/* Define the union U_VEDU_VCPI_REFH_L0_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_refch_l0_stride : 16 ; /* [15..0] */ + unsigned int vcpi_refyh_l0_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REFH_L0_STRIDE; + +/* Define the union U_VEDU_VCPI_REF_L1_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_refc_l1_stride : 16 ; /* [15..0] */ + unsigned int vcpi_refy_l1_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REF_L1_STRIDE; + +/* Define the union U_VEDU_VCPI_REFH_L1_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_refch_l1_stride : 16 ; /* [15..0] */ + unsigned int vcpi_refyh_l1_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_REFH_L1_STRIDE; + +/* Define the union U_VEDU_VCPI_STRFMT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_crop_en : 1 ; /* [0] */ + unsigned int vcpi_scale_en : 1 ; /* [1] */ + unsigned int vcpi_store_mode : 1 ; /* [2] */ + unsigned int vcpi_blk_type : 3 ; /* [5..3] */ + unsigned int vcpi_str_fmt : 4 ; /* [9..6] */ + unsigned int vcpi_package_sel : 4 ; /* [13..10] */ + unsigned int vcpi_recst_disable : 1 ; /* [14] */ + unsigned int Reserved_98 : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_STRFMT; + +/* Define the union U_VEDU_VCPI_CROP_START */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_crop_xstart : 13 ; /* [12..0] */ + unsigned int Reserved_100 : 3 ; /* [15..13] */ + unsigned int vcpi_crop_ystart : 13 ; /* [28..16] */ + unsigned int Reserved_99 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_CROP_START; + +/* Define the union U_VEDU_VCPI_CROP_END */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_crop_xend : 13 ; /* [12..0] */ + unsigned int Reserved_102 : 3 ; /* [15..13] */ + unsigned int vcpi_crop_yend : 13 ; /* [28..16] */ + unsigned int Reserved_101 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_CROP_END; + +/* Define the union U_VEDU_VCPI_SCALE_PARA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_xscale : 16 ; /* [15..0] */ + unsigned int vcpi_yscale : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_SCALE_PARA; + +/* Define the union U_VEDU_VCPI_ORI_PICSIZE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_oriwidth_pix : 13 ; /* [12..0] */ + unsigned int Reserved_104 : 3 ; /* [15..13] */ + unsigned int vcpi_oriheight_pix : 13 ; /* [28..16] */ + unsigned int Reserved_103 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_ORI_PICSIZE; + +/* Define the union U_VEDU_VCPI_BG_ENABLE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_info_st_en : 1 ; /* [0] */ + unsigned int vcpi_bg_refresh_st_en : 1 ; /* [1] */ + unsigned int vcpi_bg_ld_en : 1 ; /* [2] */ + unsigned int vcpi_bg_en : 1 ; /* [3] */ + unsigned int vcpi_bg_stat_frame : 1 ; /* [4] */ + unsigned int vcpi_bg_th_frame : 1 ; /* [5] */ + unsigned int vcpi_bg_percentage_en : 1 ; /* [6] */ + unsigned int vcpi_bg_start_idc : 1 ; /* [7] */ + unsigned int vcpi_bg_start_frame : 1 ; /* [8] */ + unsigned int vcpi_bg_reset_diff_en : 1 ; /* [9] */ + unsigned int Reserved_105 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_ENABLE; + +/* Define the union U_VEDU_VCPI_BG_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bgl_stride : 16 ; /* [15..0] */ + unsigned int vcpi_bgc_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_STRIDE; + +/* Define the union U_VEDU_VCPI_BG_FLT_PARA0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_alpha_fix_0 : 11 ; /* [10..0] */ + unsigned int Reserved_107 : 5 ; /* [15..11] */ + unsigned int vcpi_bg_alpha_fix_1 : 11 ; /* [26..16] */ + unsigned int Reserved_106 : 5 ; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_FLT_PARA0; + +/* Define the union U_VEDU_VCPI_BG_FLT_PARA1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_belta_fix_0 : 11 ; /* [10..0] */ + unsigned int Reserved_109 : 5 ; /* [15..11] */ + unsigned int vcpi_bg_belta_fix_1 : 11 ; /* [26..16] */ + unsigned int Reserved_108 : 5 ; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_FLT_PARA1; + +/* Define the union U_VEDU_VCPI_BG_FLT_PARA2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_delta_fix_0 : 11 ; /* [10..0] */ + unsigned int Reserved_111 : 5 ; /* [15..11] */ + unsigned int vcpi_bg_delta_fix_1 : 11 ; /* [26..16] */ + unsigned int Reserved_110 : 5 ; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_FLT_PARA2; + +/* Define the union U_VEDU_VCPI_BG_THR0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_th_ave : 8 ; /* [7..0] */ + unsigned int vcpi_bg_stat_th : 13 ; /* [20..8] */ + unsigned int vcpi_bg_ave_update_th : 8 ; /* [28..21] */ + unsigned int Reserved_112 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_THR0; + +/* Define the union U_VEDU_VCPI_BG_THR1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bg_dist_th : 8 ; /* [7..0] */ + unsigned int vcpi_bg_frame_num : 8 ; /* [15..8] */ + unsigned int vcpi_bg_min_diff : 8 ; /* [23..16] */ + unsigned int Reserved_113 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_BG_THR1; + +/* Define the union U_VEDU_VCPI_MEM_CTRL_T16 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mem_ctrl_s : 16 ; /* [15..0] */ + unsigned int mem_ctrl_d1w2r : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_MEM_CTRL_T16; + +/* Define the union U_VEDU_VCPI_INTRA32_LOW_POWER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_intra32_low_power_thr : 16 ; /* [15..0] */ + unsigned int vcpi_intra32_low_power_en : 1 ; /* [16] */ + unsigned int Reserved_114 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTRA32_LOW_POWER; + +/* Define the union U_VEDU_VCPI_INTRA16_LOW_POWER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_intra16_low_power_thr : 16 ; /* [15..0] */ + unsigned int vcpi_intra16_low_power_en : 1 ; /* [16] */ + unsigned int Reserved_115 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTRA16_LOW_POWER; + +/* Define the union U_VEDU_VCPI_INTRA_REDUCE_RDO_NUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_intra_reduce_rdo_num_thr : 12 ; /* [11..0] */ + unsigned int Reserved_117 : 4 ; /* [15..12] */ + unsigned int vcpi_intra_reduce_rdo_num_en : 1 ; /* [16] */ + unsigned int Reserved_116 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTRA_REDUCE_RDO_NUM; + +/* Define the union U_VEDU_VCPI_NOFORCEZERO */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bislayer0flag : 1 ; /* [0] */ + unsigned int vcpi_bnoforcezero_flag : 1 ; /* [1] */ + unsigned int vcpi_bnoforcezero_posx : 4 ; /* [5..2] */ + unsigned int vcpi_bnoforcezero_posy : 4 ; /* [9..6] */ + unsigned int Reserved_118 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_NOFORCEZERO; + +/* Define the union U_VEDU_VCPI_INTMASK_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_enable_ve_eop_s : 1 ; /* [0] */ + unsigned int vcpi_enable_vedu_slice_end_s : 1 ; /* [1] */ + unsigned int vcpi_enable_ve_buffull_s : 1 ; /* [2] */ + unsigned int vcpi_enable_ve_pbitsover_s : 1 ; /* [3] */ + unsigned int vcpi_enable_vedu_brkpt_s : 1 ; /* [4] */ + unsigned int vcpi_enable_vedu_step_s : 1 ; /* [5] */ + unsigned int vcpi_enable_vedu_timeout_s : 1 ; /* [6] */ + unsigned int vcpi_enable_cfg_err_s : 1 ; /* [7] */ + unsigned int Reserved_119 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTMASK_S; + +/* Define the union U_VEDU_VCPI_INTCLR_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_clr_ve_eop_s : 1 ; /* [0] */ + unsigned int vcpi_clr_vedu_slice_end_s : 1 ; /* [1] */ + unsigned int vcpi_clr_ve_buffull_s : 1 ; /* [2] */ + unsigned int vcpi_clr_ve_pbitsover_s : 1 ; /* [3] */ + unsigned int vcpi_clr_vedu_brkpt_s : 1 ; /* [4] */ + unsigned int vcpi_clr_vedu_step_s : 1 ; /* [5] */ + unsigned int vcpi_clr_vedu_timeout_s : 1 ; /* [6] */ + unsigned int vcpi_clr_cfg_err_s : 1 ; /* [7] */ + unsigned int Reserved_120 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCPI_INTCLR_S; + +/* Define the union U_VEDU_VCTRL_ROI_CFG0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_region0en : 1 ; /* [0] */ + unsigned int vctrl_region1en : 1 ; /* [1] */ + unsigned int vctrl_region2en : 1 ; /* [2] */ + unsigned int vctrl_region3en : 1 ; /* [3] */ + unsigned int vctrl_region4en : 1 ; /* [4] */ + unsigned int vctrl_region5en : 1 ; /* [5] */ + unsigned int vctrl_region6en : 1 ; /* [6] */ + unsigned int vctrl_region7en : 1 ; /* [7] */ + unsigned int vctrl_absqp0 : 1 ; /* [8] */ + unsigned int vctrl_absqp1 : 1 ; /* [9] */ + unsigned int vctrl_absqp2 : 1 ; /* [10] */ + unsigned int vctrl_absqp3 : 1 ; /* [11] */ + unsigned int vctrl_absqp4 : 1 ; /* [12] */ + unsigned int vctrl_absqp5 : 1 ; /* [13] */ + unsigned int vctrl_absqp6 : 1 ; /* [14] */ + unsigned int vctrl_absqp7 : 1 ; /* [15] */ + unsigned int vctrl_region0keep : 1 ; /* [16] */ + unsigned int vctrl_region1keep : 1 ; /* [17] */ + unsigned int vctrl_region2keep : 1 ; /* [18] */ + unsigned int vctrl_region3keep : 1 ; /* [19] */ + unsigned int vctrl_region4keep : 1 ; /* [20] */ + unsigned int vctrl_region5keep : 1 ; /* [21] */ + unsigned int vctrl_region6keep : 1 ; /* [22] */ + unsigned int vctrl_region7keep : 1 ; /* [23] */ + unsigned int vctrl_roi_en : 1 ; /* [24] */ + unsigned int Reserved_122 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_CFG0; + +/* Define the union U_VEDU_VCTRL_ROI_CFG1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roiqp0 : 7 ; /* [6..0] */ + unsigned int Reserved_126 : 1 ; /* [7] */ + unsigned int vctrl_roiqp1 : 7 ; /* [14..8] */ + unsigned int Reserved_125 : 1 ; /* [15] */ + unsigned int vctrl_roiqp2 : 7 ; /* [22..16] */ + unsigned int Reserved_124 : 1 ; /* [23] */ + unsigned int vctrl_roiqp3 : 7 ; /* [30..24] */ + unsigned int Reserved_123 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_CFG1; + +/* Define the union U_VEDU_VCTRL_ROI_CFG2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roiqp4 : 7 ; /* [6..0] */ + unsigned int Reserved_130 : 1 ; /* [7] */ + unsigned int vctrl_roiqp5 : 7 ; /* [14..8] */ + unsigned int Reserved_129 : 1 ; /* [15] */ + unsigned int vctrl_roiqp6 : 7 ; /* [22..16] */ + unsigned int Reserved_128 : 1 ; /* [23] */ + unsigned int vctrl_roiqp7 : 7 ; /* [30..24] */ + unsigned int Reserved_127 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_CFG2; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size0_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_132 : 6 ; /* [15..10] */ + unsigned int vctrl_size0_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_131 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_0; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size1_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_134 : 6 ; /* [15..10] */ + unsigned int vctrl_size1_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_133 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_1; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size2_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_136 : 6 ; /* [15..10] */ + unsigned int vctrl_size2_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_135 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_2; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size3_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_138 : 6 ; /* [15..10] */ + unsigned int vctrl_size3_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_137 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_3; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_4 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size4_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_140 : 6 ; /* [15..10] */ + unsigned int vctrl_size4_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_139 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_4; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_5 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size5_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_142 : 6 ; /* [15..10] */ + unsigned int vctrl_size5_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_141 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_5; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_6 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size6_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_144 : 6 ; /* [15..10] */ + unsigned int vctrl_size6_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_143 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_6; + +/* Define the union U_VEDU_VCTRL_ROI_SIZE_7 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_size7_roiwidth : 10 ; /* [9..0] */ + unsigned int Reserved_146 : 6 ; /* [15..10] */ + unsigned int vctrl_size7_roiheight : 10 ; /* [25..16] */ + unsigned int Reserved_145 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_SIZE_7; + +/* Define the union U_VEDU_VCTRL_ROI_START_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start0_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_148 : 7 ; /* [15..9] */ + unsigned int vctrl_start0_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_147 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_0; + +/* Define the union U_VEDU_VCTRL_ROI_START_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start1_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_150 : 7 ; /* [15..9] */ + unsigned int vctrl_start1_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_149 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_1; + +/* Define the union U_VEDU_VCTRL_ROI_START_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start2_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_152 : 7 ; /* [15..9] */ + unsigned int vctrl_start2_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_151 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_2; + +/* Define the union U_VEDU_VCTRL_ROI_START_3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start3_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_154 : 7 ; /* [15..9] */ + unsigned int vctrl_start3_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_153 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_3; + +/* Define the union U_VEDU_VCTRL_ROI_START_4 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start4_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_156 : 7 ; /* [15..9] */ + unsigned int vctrl_start4_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_155 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_4; + +/* Define the union U_VEDU_VCTRL_ROI_START_5 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start5_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_158 : 7 ; /* [15..9] */ + unsigned int vctrl_start5_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_157 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_5; + +/* Define the union U_VEDU_VCTRL_ROI_START_6 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start6_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_160 : 7 ; /* [15..9] */ + unsigned int vctrl_start6_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_159 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_6; + +/* Define the union U_VEDU_VCTRL_ROI_START_7 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_start7_roistartx : 9 ; /* [8..0] */ + unsigned int Reserved_162 : 7 ; /* [15..9] */ + unsigned int vctrl_start7_roistarty : 9 ; /* [24..16] */ + unsigned int Reserved_161 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_ROI_START_7; + +/* Define the union U_VEDU_VCTRL_LCU_TARGET_BIT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_lcu_target_bit : 20 ; /* [19..0] */ + unsigned int Reserved_163 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_LCU_TARGET_BIT; + +/* Define the union U_VEDU_VCTRL_NARROW_THRESHOLD */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_narrow_tile_width : 4 ; /* [3..0] */ + unsigned int Reserved_164 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_NARROW_THRESHOLD; + +/* Define the union U_VEDU_VCTRL_LCU_BASELINE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_lcu_performance_baseline : 16 ; /* [15..0] */ + unsigned int Reserved_165 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_LCU_BASELINE; + +/* Define the union U_VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_168 : 6 ; /* [15..10] */ + unsigned int vctrl_norm32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_167 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingoffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_166 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_171 : 8 ; /* [15..8] */ + unsigned int vctrl_norm16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_170 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingoffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_169 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_NORM_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingdegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundinglowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundinglowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_172 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_NORM_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_NORM_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_norm_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_norm_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_norm_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_norm_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_norm_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_173 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_NORM_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_176 : 6 ; /* [15..10] */ + unsigned int vctrl_skin32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_175 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingskinoffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_174 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_179 : 8 ; /* [15..8] */ + unsigned int vctrl_skin16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_178 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingskinoffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_177 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SKIN_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingskinmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingskindegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingskinforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingskinac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingskinac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingskinlowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingskinlowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_180 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SKIN_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SKIN_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_skin_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_skin_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_skin_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_skin_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_skin_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_181 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SKIN_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_hedge32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_184 : 6 ; /* [15..10] */ + unsigned int vctrl_hedge32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_183 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingedgeoffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_182 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_hedge16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_187 : 8 ; /* [15..8] */ + unsigned int vctrl_hedge16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_186 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingedgeoffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_185 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGE_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingedgemechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingedgedegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingedgeforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingedgeac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingedgeac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingedgelowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingedgelowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_188 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGE_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGE_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_stredge_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_stredge_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_stredge_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_stredge_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_stredge_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_stredge_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_189 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGE_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_edgemov32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_192 : 6 ; /* [15..10] */ + unsigned int vctrl_edgemov32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_191 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingedgemovoffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_190 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_edgemov16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_195 : 8 ; /* [15..8] */ + unsigned int vctrl_edgemov16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_194 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingedgemovoffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_193 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingedgemovmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingedgemovdegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingedgemovforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingedgemovac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingedgemovac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingedgemovlowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingedgemovlowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_196 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_HEDGEMOV_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_edgemov_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_edgemov_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_edgemov_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_edgemov_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_edgemov_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_edgemov_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_197 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_HEDGEMOV_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_static32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_200 : 6 ; /* [15..10] */ + unsigned int vctrl_static32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_199 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingstilloffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_198 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_static16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_203 : 8 ; /* [15..8] */ + unsigned int vctrl_static16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_202 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingstilloffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_201 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_STATIC_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingstillmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingstilldegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingstillforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingstillac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingstillac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingstilllowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingstilllowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_204 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_STATIC_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_STATIC_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_still_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_still_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_still_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_still_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_still_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_still_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_205 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_STATIC_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelstr32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_208 : 6 ; /* [15..10] */ + unsigned int vctrl_sobelstr32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_207 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingsobelstroffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_206 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelstr16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_211 : 8 ; /* [15..8] */ + unsigned int vctrl_sobelstr16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_210 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingsobelstroffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_209 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELSTR_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingsobelstrmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingsobelstrdegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingsobelstrforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingsobelstrac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingsobelstrac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingsobelstrlowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingsobelstrlowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_212 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELSTR_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELSTR_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelstr_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_sobelstr_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_sobelstr_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_sobelstr_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_sobelstr_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_sobelstr_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_213 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELSTR_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelweak32_coeff_protect_num : 10 ; /* [9..0] */ + unsigned int Reserved_216 : 6 ; /* [15..10] */ + unsigned int vctrl_sobelweak32_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_215 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingsobelweakoffset32x32 : 4 ; /* [27..24] */ + unsigned int Reserved_214 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelweak16_coeff_protect_num : 8 ; /* [7..0] */ + unsigned int Reserved_219 : 8 ; /* [15..8] */ + unsigned int vctrl_sobelweak16_tr1_denois_max_num : 5 ; /* [20..16] */ + unsigned int Reserved_218 : 3 ; /* [23..21] */ + unsigned int vctrl_roundingsobelweakoffset16x16 : 4 ; /* [27..24] */ + unsigned int Reserved_217 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_roundingsobelweakmechanism : 3 ; /* [2..0] */ + unsigned int vctrl_roundingsobelweakdegreethresh : 7 ; /* [9..3] */ + unsigned int vctrl_roundingsobelweakforcezeroresidthresh : 3 ; /* [12..10] */ + unsigned int vctrl_roundingsobelweakac32sum : 5 ; /* [17..13] */ + unsigned int vctrl_roundingsobelweakac16sum : 4 ; /* [21..18] */ + unsigned int vctrl_roundingsobelweaklowfreqacblk32 : 4 ; /* [25..22] */ + unsigned int vctrl_roundingsobelweaklowfreqacblk16 : 4 ; /* [29..26] */ + unsigned int Reserved_220 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE; + +/* Define the union U_VEDU_VCTRL_SOBELWEAK_ENG_DENOISE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_sobelwk_isolate_ac_enable : 1 ; /* [0] */ + unsigned int vctrl_sobelwk_force_zero_cnt : 3 ; /* [3..1] */ + unsigned int vctrl_sobelwk_engsum_32 : 6 ; /* [9..4] */ + unsigned int vctrl_sobelwk_engcnt_32 : 5 ; /* [14..10] */ + unsigned int vctrl_sobelwk_engsum_16 : 6 ; /* [20..15] */ + unsigned int vctrl_sobelwk_engcnt_16 : 5 ; /* [25..21] */ + unsigned int Reserved_221 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_SOBELWEAK_ENG_DENOISE; + +/* Define the union U_VEDU_VCTRL_INTRA_RDO_FACTOR_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm_intra_cu4_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_norm_intra_cu8_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_norm_intra_cu16_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_norm_intra_cu32_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_strmov_intra_cu4_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_strmov_intra_cu8_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_strmov_intra_cu16_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_strmov_intra_cu32_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_INTRA_RDO_FACTOR_0; + +/* Define the union U_VEDU_VCTRL_INTRA_RDO_FACTOR_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin_intra_cu4_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_skin_intra_cu8_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_skin_intra_cu16_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_skin_intra_cu32_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_str_intra_cu4_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_str_intra_cu8_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_str_intra_cu16_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_str_intra_cu32_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_INTRA_RDO_FACTOR_1; + +/* Define the union U_VEDU_VCTRL_INTRA_RDO_FACTOR_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_hedge_intra_cu4_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_hedge_intra_cu8_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_hedge_intra_cu16_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_hedge_intra_cu32_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_tex_intra_cu4_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_tex_intra_cu8_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_tex_intra_cu16_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_tex_intra_cu32_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_INTRA_RDO_FACTOR_2; + +/* Define the union U_VEDU_VCTRL_MRG_RDO_FACTOR_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm_mrg_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_norm_mrg_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_norm_mrg_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_norm_mrg_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_strmov_mrg_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_strmov_mrg_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_strmov_mrg_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_strmov_mrg_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_MRG_RDO_FACTOR_0; + +/* Define the union U_VEDU_VCTRL_MRG_RDO_FACTOR_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin_mrg_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_skin_mrg_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_skin_mrg_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_skin_mrg_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_str_mrg_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_str_mrg_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_str_mrg_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_str_mrg_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_MRG_RDO_FACTOR_1; + +/* Define the union U_VEDU_VCTRL_MRG_RDO_FACTOR_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_hedge_mrg_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_hedge_mrg_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_hedge_mrg_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_hedge_mrg_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_tex_mrg_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_tex_mrg_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_tex_mrg_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_tex_mrg_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_MRG_RDO_FACTOR_2; + +/* Define the union U_VEDU_VCTRL_FME_RDO_FACTOR_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_norm_fme_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_norm_fme_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_norm_fme_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_norm_fme_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_strmov_fme_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_strmov_fme_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_strmov_fme_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_strmov_fme_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_FME_RDO_FACTOR_0; + +/* Define the union U_VEDU_VCTRL_FME_RDO_FACTOR_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_skin_fme_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_skin_fme_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_skin_fme_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_skin_fme_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_str_fme_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_str_fme_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_str_fme_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_str_fme_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_FME_RDO_FACTOR_1; + +/* Define the union U_VEDU_VCTRL_FME_RDO_FACTOR_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vctrl_hedge_fme_cu8_rdcost_offset : 4 ; /* [3..0] */ + unsigned int vctrl_hedge_fme_cu16_rdcost_offset : 4 ; /* [7..4] */ + unsigned int vctrl_hedge_fme_cu32_rdcost_offset : 4 ; /* [11..8] */ + unsigned int vctrl_hedge_fme_cu64_rdcost_offset : 4 ; /* [15..12] */ + unsigned int vctrl_sobel_tex_fme_cu8_rdcost_offset : 4 ; /* [19..16] */ + unsigned int vctrl_sobel_tex_fme_cu16_rdcost_offset : 4 ; /* [23..20] */ + unsigned int vctrl_sobel_tex_fme_cu32_rdcost_offset : 4 ; /* [27..24] */ + unsigned int vctrl_sobel_tex_fme_cu64_rdcost_offset : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VCTRL_FME_RDO_FACTOR_2; + +/* Define the union U_VEDU_CURLD_GCFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd0_global_en : 1 ; /* [0] */ + unsigned int curld_osd1_global_en : 1 ; /* [1] */ + unsigned int curld_osd2_global_en : 1 ; /* [2] */ + unsigned int curld_osd3_global_en : 1 ; /* [3] */ + unsigned int curld_osd4_global_en : 1 ; /* [4] */ + unsigned int curld_osd5_global_en : 1 ; /* [5] */ + unsigned int curld_osd6_global_en : 1 ; /* [6] */ + unsigned int curld_osd7_global_en : 1 ; /* [7] */ + unsigned int Reserved_226 : 6 ; /* [13..8] */ + unsigned int curld_col2gray_en : 1 ; /* [14] */ + unsigned int curld_clip_en : 1 ; /* [15] */ + unsigned int Reserved_225 : 4 ; /* [19..16] */ + unsigned int curld_read_interval : 8 ; /* [27..20] */ + unsigned int curld_lowdly_en : 1 ; /* [28] */ + unsigned int Reserved_224 : 1 ; /* [29] */ + unsigned int curld_osd_rgbfmt : 1 ; /* [30] */ + unsigned int Reserved_223 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_GCFG; + +/* Define the union U_VEDU_CURLD_OSD01_ALPHA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd0_alpha0 : 8 ; /* [7..0] */ + unsigned int curld_osd0_alpha1 : 8 ; /* [15..8] */ + unsigned int curld_osd1_alpha0 : 8 ; /* [23..16] */ + unsigned int curld_osd1_alpha1 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD01_ALPHA; + +/* Define the union U_VEDU_CURLD_OSD23_ALPHA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd2_alpha0 : 8 ; /* [7..0] */ + unsigned int curld_osd2_alpha1 : 8 ; /* [15..8] */ + unsigned int curld_osd3_alpha0 : 8 ; /* [23..16] */ + unsigned int curld_osd3_alpha1 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD23_ALPHA; + +/* Define the union U_VEDU_CURLD_OSD45_ALPHA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd4_alpha0 : 8 ; /* [7..0] */ + unsigned int curld_osd4_alpha1 : 8 ; /* [15..8] */ + unsigned int curld_osd5_alpha0 : 8 ; /* [23..16] */ + unsigned int curld_osd5_alpha1 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD45_ALPHA; + +/* Define the union U_VEDU_CURLD_OSD67_ALPHA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd6_alpha0 : 8 ; /* [7..0] */ + unsigned int curld_osd6_alpha1 : 8 ; /* [15..8] */ + unsigned int curld_osd7_alpha0 : 8 ; /* [23..16] */ + unsigned int curld_osd7_alpha1 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD67_ALPHA; + +/* Define the union U_VEDU_CURLD_OSD_GALPHA0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd0_global_alpha : 8 ; /* [7..0] */ + unsigned int curld_osd1_global_alpha : 8 ; /* [15..8] */ + unsigned int curld_osd2_global_alpha : 8 ; /* [23..16] */ + unsigned int curld_osd3_global_alpha : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD_GALPHA0; + +/* Define the union U_VEDU_CURLD_OSD_GALPHA1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd4_global_alpha : 8 ; /* [7..0] */ + unsigned int curld_osd5_global_alpha : 8 ; /* [15..8] */ + unsigned int curld_osd6_global_alpha : 8 ; /* [23..16] */ + unsigned int curld_osd7_global_alpha : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD_GALPHA1; + +/* Define the union U_VEDU_CURLD_OSD01_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd0_stride : 16 ; /* [15..0] */ + unsigned int curld_osd1_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD01_STRIDE; + +/* Define the union U_VEDU_CURLD_OSD23_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd2_stride : 16 ; /* [15..0] */ + unsigned int curld_osd3_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD23_STRIDE; + +/* Define the union U_VEDU_CURLD_OSD45_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd4_stride : 16 ; /* [15..0] */ + unsigned int curld_osd5_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD45_STRIDE; + +/* Define the union U_VEDU_CURLD_OSD67_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_osd6_stride : 16 ; /* [15..0] */ + unsigned int curld_osd7_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_OSD67_STRIDE; + +/* Define the union U_VEDU_CURLD_CLIP_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_clip_luma_min : 8 ; /* [7..0] */ + unsigned int curld_clip_luma_max : 8 ; /* [15..8] */ + unsigned int curld_clip_chrm_min : 8 ; /* [23..16] */ + unsigned int curld_clip_chrm_max : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_CLIP_THR; + +/* Define the union U_VEDU_CURLD_HOR_FILTER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_filter_h0 : 4 ; /* [3..0] */ + unsigned int curld_filter_h1 : 4 ; /* [7..4] */ + unsigned int curld_filter_h2 : 4 ; /* [11..8] */ + unsigned int curld_filter_h3 : 4 ; /* [15..12] */ + unsigned int curld_filter_hrnd : 4 ; /* [19..16] */ + unsigned int curld_filter_hshift : 3 ; /* [22..20] */ + unsigned int Reserved_227 : 9 ; /* [31..23] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_HOR_FILTER; + +/* Define the union U_VEDU_CURLD_VER_FILTER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_filter_v0 : 4 ; /* [3..0] */ + unsigned int curld_filter_v1 : 4 ; /* [7..4] */ + unsigned int curld_filter_v2 : 4 ; /* [11..8] */ + unsigned int curld_filter_v3 : 4 ; /* [15..12] */ + unsigned int curld_filter_vrnd : 4 ; /* [19..16] */ + unsigned int curld_filter_vshift : 3 ; /* [22..20] */ + unsigned int Reserved_228 : 9 ; /* [31..23] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_VER_FILTER; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_0COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_coeff_gy : 15 ; /* [14..0] */ + unsigned int Reserved_230 : 1 ; /* [15] */ + unsigned int vcpi_coeff_ry : 15 ; /* [30..16] */ + unsigned int Reserved_229 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_0COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_1COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_coeff_rcb : 15 ; /* [14..0] */ + unsigned int Reserved_232 : 1 ; /* [15] */ + unsigned int vcpi_coeff_by : 15 ; /* [30..16] */ + unsigned int Reserved_231 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_1COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_2COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_coeff_bcb : 15 ; /* [14..0] */ + unsigned int Reserved_234 : 1 ; /* [15] */ + unsigned int vcpi_coeff_gcb : 15 ; /* [30..16] */ + unsigned int Reserved_233 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_2COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_3COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_coeff_gcr : 15 ; /* [14..0] */ + unsigned int Reserved_236 : 1 ; /* [15] */ + unsigned int vcpi_coeff_rcr : 15 ; /* [30..16] */ + unsigned int Reserved_235 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_3COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_4COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_coeff_bcr : 15 ; /* [14..0] */ + unsigned int Reserved_237 : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_4COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_5COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rgb_rndy : 16 ; /* [15..0] */ + unsigned int vcpi_rgb_shift : 4 ; /* [19..16] */ + unsigned int Reserved_238 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_5COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_YUV_6COEFF */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rgb_rndcr : 16 ; /* [15..0] */ + unsigned int vcpi_rgb_rndcb : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_YUV_6COEFF; + +/* Define the union U_VEDU_CURLD_ARGB_CLIP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rgb_clpmin : 8 ; /* [7..0] */ + unsigned int vcpi_rgb_clpmax : 8 ; /* [15..8] */ + unsigned int vcpi_rgb_clip_en : 1 ; /* [16] */ + unsigned int Reserved_239 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_ARGB_CLIP; + +/* Define the union U_VEDU_CURLD_NARROW_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int curld_y_wide_narrow_en : 1 ; /* [0] */ + unsigned int curld_c_wide_narrow_en : 1 ; /* [1] */ + unsigned int Reserved_240 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_NARROW_EN; + +/* Define the union U_VEDU_CURLD_SRCH_STRIDE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_curld_srcch_stride : 16 ; /* [15..0] */ + unsigned int vcpi_curld_srcyh_stride : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_SRCH_STRIDE; + +/* Define the union U_VEDU_CURLD_HFBCD */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_curld_hfbcd_bypass_en : 1 ; /* [0] */ + unsigned int vcpi_curld_hfbcd_raw_en : 1 ; /* [1] */ + unsigned int Reserved_241 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CURLD_HFBCD; + +/* Define the union U_VEDU_PME_SW_ADAPT_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_psw_adapt_en : 1 ; /* [0] */ + unsigned int pme_l1_psw_adapt_en : 1 ; /* [1] */ + unsigned int Reserved_244 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SW_ADAPT_EN; + +/* Define the union U_VEDU_PME_SW_THR0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_psw_thr0 : 16 ; /* [15..0] */ + unsigned int pme_l1_psw_thr0 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SW_THR0; + +/* Define the union U_VEDU_PME_SW_THR1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_psw_thr1 : 16 ; /* [15..0] */ + unsigned int pme_l1_psw_thr1 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SW_THR1; + +/* Define the union U_VEDU_PME_SW_THR2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_psw_thr2 : 16 ; /* [15..0] */ + unsigned int pme_l1_psw_thr2 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SW_THR2; + +/* Define the union U_VEDU_PME_SKIP_PRE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_skipblk_pre_cost_thr : 16 ; /* [15..0] */ + unsigned int pme_skipblk_pre_en : 1 ; /* [16] */ + unsigned int Reserved_245 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SKIP_PRE; + +/* Define the union U_VEDU_PME_TR_WEIGHTX */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_tr_weightx_0 : 9 ; /* [8..0] */ + unsigned int pme_tr_weightx_1 : 9 ; /* [17..9] */ + unsigned int pme_tr_weightx_2 : 9 ; /* [26..18] */ + unsigned int Reserved_246 : 5 ; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_TR_WEIGHTX; + +/* Define the union U_VEDU_PME_TR_WEIGHTY */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_tr_weighty_0 : 8 ; /* [7..0] */ + unsigned int pme_tr_weighty_1 : 8 ; /* [15..8] */ + unsigned int pme_tr_weighty_2 : 8 ; /* [23..16] */ + unsigned int Reserved_247 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_TR_WEIGHTY; + +/* Define the union U_VEDU_PME_SR_WEIGHT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_sr_weight_0 : 4 ; /* [3..0] */ + unsigned int pme_sr_weight_1 : 4 ; /* [7..4] */ + unsigned int pme_sr_weight_2 : 4 ; /* [11..8] */ + unsigned int pme_pskip_strongedge_madi_thr : 8 ; /* [19..12] */ + unsigned int pme_pskip_strongedge_madi_times : 8 ; /* [27..20] */ + unsigned int Reserved_248 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SR_WEIGHT; + +/* Define the union U_VEDU_PME_INTRABLK_DET */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_intrablk_det_cost_thr0 : 16 ; /* [15..0] */ + unsigned int pme_pskip_mvy_consistency_thr : 8 ; /* [23..16] */ + unsigned int pme_pskip_mvx_consistency_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_INTRABLK_DET; + +/* Define the union U_VEDU_PME_INTRABLK_DET_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_intrablk_det_mv_dif_thr1 : 8 ; /* [7..0] */ + unsigned int pme_intrablk_det_mv_dif_thr0 : 8 ; /* [15..8] */ + unsigned int pme_intrablk_det_mvy_thr : 8 ; /* [23..16] */ + unsigned int pme_intrablk_det_mvx_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_INTRABLK_DET_THR; + +/* Define the union U_VEDU_PME_SKIN_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_skin_u_max_thr : 8 ; /* [7..0] */ + unsigned int pme_skin_u_min_thr : 8 ; /* [15..8] */ + unsigned int pme_skin_v_max_thr : 8 ; /* [23..16] */ + unsigned int pme_skin_v_min_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SKIN_THR; + +/* Define the union U_VEDU_PME_INTRA_LOWPOW */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_intra16_madi_thr : 8 ; /* [7..0] */ + unsigned int pme_intra32_madi_thr : 8 ; /* [15..8] */ + unsigned int pme_intra_lowpow_en : 1 ; /* [16] */ + unsigned int pme_inter_first : 1 ; /* [17] */ + unsigned int Reserved_249 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_INTRA_LOWPOW; + +/* Define the union U_VEDU_PME_IBLK_COST_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_iblk_pre_cost_thr_h264 : 16 ; /* [15..0] */ + unsigned int pme_intrablk_det_cost_thr1 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_IBLK_COST_THR; + +/* Define the union U_VEDU_PME_STRONG_EDGE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_skin_num : 9 ; /* [8..0] */ + unsigned int pme_strong_edge_thr : 8 ; /* [16..9] */ + unsigned int pme_strong_edge_cnt : 5 ; /* [21..17] */ + unsigned int pme_still_scene_thr : 9 ; /* [30..22] */ + unsigned int Reserved_250 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_STRONG_EDGE; + +/* Define the union U_VEDU_PME_LARGE_MOVE_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_move_scene_thr : 8 ; /* [7..0] */ + unsigned int pme_move_sad_thr : 14 ; /* [21..8] */ + unsigned int Reserved_251 : 10 ; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_LARGE_MOVE_THR; + +/* Define the union U_VEDU_PME_INTER_STRONG_EDGE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_interdiff_max_min_madi_abs : 8 ; /* [7..0] */ + unsigned int pme_interdiff_max_min_madi_times : 8 ; /* [15..8] */ + unsigned int pme_interstrongedge_madi_thr : 8 ; /* [23..16] */ + unsigned int Reserved_252 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_INTER_STRONG_EDGE; + +/* Define the union U_VEDU_PME_NEW_COST */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_cost_lamda0 : 4 ; /* [3..0] */ + unsigned int pme_cost_lamda1 : 4 ; /* [7..4] */ + unsigned int pme_cost_lamda2 : 4 ; /* [11..8] */ + unsigned int pme_new_cost_en : 2 ; /* [13..12] */ + unsigned int Reserved_254 : 2 ; /* [15..14] */ + unsigned int pme_cost_lamda_en : 2 ; /* [17..16] */ + unsigned int pme_mvp3median_en : 1 ; /* [18] */ + unsigned int Reserved_253 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_NEW_COST; + +/* Define the union U_VEDU_PME_WINDOW_SIZE0_L0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_win0_width : 10 ; /* [9..0] */ + unsigned int Reserved_256 : 6 ; /* [15..10] */ + unsigned int pme_l0_win0_height : 9 ; /* [24..16] */ + unsigned int Reserved_255 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE0_L0; + +/* Define the union U_VEDU_PME_WINDOW_SIZE1_L0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_win1_width : 10 ; /* [9..0] */ + unsigned int Reserved_258 : 6 ; /* [15..10] */ + unsigned int pme_l0_win1_height : 9 ; /* [24..16] */ + unsigned int Reserved_257 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE1_L0; + +/* Define the union U_VEDU_PME_WINDOW_SIZE2_L0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_win2_width : 10 ; /* [9..0] */ + unsigned int Reserved_260 : 6 ; /* [15..10] */ + unsigned int pme_l0_win2_height : 9 ; /* [24..16] */ + unsigned int Reserved_259 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE2_L0; + +/* Define the union U_VEDU_PME_WINDOW_SIZE3_L0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_win3_width : 10 ; /* [9..0] */ + unsigned int Reserved_262 : 6 ; /* [15..10] */ + unsigned int pme_l0_win3_height : 9 ; /* [24..16] */ + unsigned int Reserved_261 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE3_L0; + +/* Define the union U_VEDU_PME_WINDOW_SIZE0_L1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l1_win0_width : 10 ; /* [9..0] */ + unsigned int Reserved_264 : 6 ; /* [15..10] */ + unsigned int pme_l1_win0_height : 9 ; /* [24..16] */ + unsigned int Reserved_263 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE0_L1; + +/* Define the union U_VEDU_PME_WINDOW_SIZE1_L1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l1_win1_width : 10 ; /* [9..0] */ + unsigned int Reserved_266 : 6 ; /* [15..10] */ + unsigned int pme_l1_win1_height : 9 ; /* [24..16] */ + unsigned int Reserved_265 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE1_L1; + +/* Define the union U_VEDU_PME_WINDOW_SIZE2_L1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l1_win2_width : 10 ; /* [9..0] */ + unsigned int Reserved_268 : 6 ; /* [15..10] */ + unsigned int pme_l1_win2_height : 9 ; /* [24..16] */ + unsigned int Reserved_267 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE2_L1; + +/* Define the union U_VEDU_PME_WINDOW_SIZE3_L1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l1_win3_width : 10 ; /* [9..0] */ + unsigned int Reserved_270 : 6 ; /* [15..10] */ + unsigned int pme_l1_win3_height : 9 ; /* [24..16] */ + unsigned int Reserved_269 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_WINDOW_SIZE3_L1; + +/* Define the union U_VEDU_PME_COST_OFFSET */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_l0_cost_offset : 16 ; /* [15..0] */ + unsigned int pme_l1_cost_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_COST_OFFSET; + +/* Define the union U_VEDU_PME_SAFE_CFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_safe_line : 13 ; /* [12..0] */ + unsigned int pme_safe_line_val : 1 ; /* [13] */ + unsigned int Reserved_271 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SAFE_CFG; + +/* Define the union U_VEDU_PME_IBLK_REFRESH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_iblk_refresh_start_num : 18 ; /* [17..0] */ + unsigned int Reserved_272 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_IBLK_REFRESH; + +/* Define the union U_VEDU_PME_IBLK_REFRESH_NUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_iblk_refresh_num : 18 ; /* [17..0] */ + unsigned int Reserved_273 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_IBLK_REFRESH_NUM; + +/* Define the union U_VEDU_PME_QPG_RC_THR0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_275 : 16 ; /* [15..0] */ + unsigned int pme_madi_dif_thr : 7 ; /* [22..16] */ + unsigned int pme_cur_madi_dif_thr : 7 ; /* [29..23] */ + unsigned int Reserved_274 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_QPG_RC_THR0; + +/* Define the union U_VEDU_PME_QPG_RC_THR1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_min_sad_thr_offset : 8 ; /* [7..0] */ + unsigned int pme_min_sad_thr_gain : 4 ; /* [11..8] */ + unsigned int pme_smooth_madi_thr : 8 ; /* [19..12] */ + unsigned int pme_min_sad_thr_offset_cur : 8 ; /* [27..20] */ + unsigned int pme_min_sad_thr_gain_cur : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_QPG_RC_THR1; + +/* Define the union U_VEDU_PME_LOW_LUMA_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_low_luma_thr : 8 ; /* [7..0] */ + unsigned int pme_low_luma_madi_thr : 8 ; /* [15..8] */ + unsigned int pme_high_luma_thr : 8 ; /* [23..16] */ + unsigned int Reserved_276 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_LOW_LUMA_THR; + +/* Define the union U_VEDU_PME_PBLK_PRE1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_pblk_pre_mv_dif_thr1 : 8 ; /* [7..0] */ + unsigned int pme_pblk_pre_mv_dif_thr0 : 8 ; /* [15..8] */ + unsigned int pme_pblk_pre_mv_dif_cost_thr : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_PBLK_PRE1; + +/* Define the union U_VEDU_PME_CHROMA_FLAT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_flat_v_thr_high : 8 ; /* [7..0] */ + unsigned int pme_flat_v_thr_low : 8 ; /* [15..8] */ + unsigned int pme_flat_u_thr_high : 8 ; /* [23..16] */ + unsigned int pme_flat_u_thr_low : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_CHROMA_FLAT; + +/* Define the union U_VEDU_PME_LUMA_FLAT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_flat_pmemv_thr : 8 ; /* [7..0] */ + unsigned int pme_flat_luma_madi_thr : 8 ; /* [15..8] */ + unsigned int pme_flat_low_luma_thr : 8 ; /* [23..16] */ + unsigned int pme_flat_high_luma_thr : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_LUMA_FLAT; + +/* Define the union U_VEDU_PME_MADI_FLAT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_flat_pmesad_thr : 14 ; /* [13..0] */ + unsigned int pme_flat_icount_thr : 9 ; /* [22..14] */ + unsigned int pme_flat_region_cnt : 5 ; /* [27..23] */ + unsigned int pme_flat_madi_times : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_MADI_FLAT; + +/* Define the union U_VEDU_PME_SKIP_LARGE_RES */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_skip_sad_thr_offset : 8 ; /* [7..0] */ + unsigned int pme_skip_sad_thr_gain : 4 ; /* [11..8] */ + unsigned int pme_skip_large_res_det : 1 ; /* [12] */ + unsigned int Reserved_277 : 19 ; /* [31..13] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PME_SKIP_LARGE_RES; + +/* Define the union U_VEDU_QPG_MAX_MIN_QP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_282 : 2 ; /* [7..6] */ + unsigned int qpg_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_281 : 2 ; /* [15..14] */ + unsigned int qpg_cu_qp_delta_enable_flag : 1 ; /* [16] */ + unsigned int Reserved_280 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_MAX_MIN_QP; + +/* Define the union U_VEDU_QPG_ROW_TARGET_BITS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_qp_delta : 6 ; /* [5..0] */ + unsigned int qpg_row_target_bits : 25 ; /* [30..6] */ + unsigned int Reserved_283 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_ROW_TARGET_BITS; + +/* Define the union U_VEDU_QPG_AVERAGE_LCU_BITS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_ave_lcu_bits : 16 ; /* [15..0] */ + unsigned int Reserved_284 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_AVERAGE_LCU_BITS; + +/* Define the union U_VEDU_QPG_LOWLUMA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lowluma_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_287 : 2 ; /* [7..6] */ + unsigned int qpg_lowluma_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_286 : 2 ; /* [15..14] */ + unsigned int qpg_lowluma_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_285 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_LOWLUMA; + +/* Define the union U_VEDU_QPG_HEDGE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_hedge_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_290 : 2 ; /* [7..6] */ + unsigned int qpg_hedge_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_289 : 2 ; /* [15..14] */ + unsigned int qpg_hedge_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_288 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_HEDGE; + +/* Define the union U_VEDU_QPG_HEDGE_MOVE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_hedge_move_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_293 : 2 ; /* [7..6] */ + unsigned int qpg_hedge_move_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_292 : 2 ; /* [15..14] */ + unsigned int qpg_hedge_move_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_291 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_HEDGE_MOVE; + +/* Define the union U_VEDU_QPG_LARGE_MOVE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_large_move_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_296 : 2 ; /* [7..6] */ + unsigned int qpg_large_move_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_295 : 2 ; /* [15..14] */ + unsigned int qpg_large_move_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_294 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_LARGE_MOVE; + +/* Define the union U_VEDU_QPG_SKIN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_skin_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_299 : 2 ; /* [7..6] */ + unsigned int qpg_skin_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_298 : 2 ; /* [15..14] */ + unsigned int qpg_skin_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_297 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_SKIN; + +/* Define the union U_VEDU_QPG_INTRA_DET */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_intra_det_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_302 : 2 ; /* [7..6] */ + unsigned int qpg_intra_det_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_301 : 2 ; /* [15..14] */ + unsigned int qpg_intra_det_qp_delta : 4 ; /* [19..16] */ + unsigned int Reserved_300 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_INTRA_DET; + +/* Define the union U_VEDU_QPG_H264_SMOOTH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_h264_smooth_min_qp : 6 ; /* [5..0] */ + unsigned int Reserved_305 : 2 ; /* [7..6] */ + unsigned int qpg_h264_smooth_max_qp : 6 ; /* [13..8] */ + unsigned int Reserved_304 : 2 ; /* [15..14] */ + unsigned int qpg_h264_smooth_qp_delta : 4 ; /* [19..16] */ + unsigned int qpg_h264_smooth_qp_delta1 : 4 ; /* [23..20] */ + unsigned int Reserved_303 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_H264_SMOOTH; + +/* Define the union U_VEDU_QPG_CU_QP_DELTA_THRESH_REG0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_cu_qp_delta_thresh0 : 8 ; /* [7..0] */ + unsigned int qpg_cu_qp_delta_thresh1 : 8 ; /* [15..8] */ + unsigned int qpg_cu_qp_delta_thresh2 : 8 ; /* [23..16] */ + unsigned int qpg_cu_qp_delta_thresh3 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU_QP_DELTA_THRESH_REG0; + +/* Define the union U_VEDU_QPG_CU_QP_DELTA_THRESH_REG1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_cu_qp_delta_thresh4 : 8 ; /* [7..0] */ + unsigned int qpg_cu_qp_delta_thresh5 : 8 ; /* [15..8] */ + unsigned int qpg_cu_qp_delta_thresh6 : 8 ; /* [23..16] */ + unsigned int qpg_cu_qp_delta_thresh7 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU_QP_DELTA_THRESH_REG1; + +/* Define the union U_VEDU_QPG_CU_QP_DELTA_THRESH_REG2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_cu_qp_delta_thresh8 : 8 ; /* [7..0] */ + unsigned int qpg_cu_qp_delta_thresh9 : 8 ; /* [15..8] */ + unsigned int qpg_cu_qp_delta_thresh10 : 8 ; /* [23..16] */ + unsigned int qpg_cu_qp_delta_thresh11 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU_QP_DELTA_THRESH_REG2; + +/* Define the union U_VEDU_QPG_CU_QP_DELTA_THRESH_REG3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_cu_qp_delta_thresh12 : 8 ; /* [7..0] */ + unsigned int qpg_cu_qp_delta_thresh13 : 8 ; /* [15..8] */ + unsigned int qpg_cu_qp_delta_thresh14 : 8 ; /* [23..16] */ + unsigned int qpg_cu_qp_delta_thresh15 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU_QP_DELTA_THRESH_REG3; + +/* Define the union U_VEDU_QPG_DELTA_LEVEL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_qp_delta_level_0 : 2 ; /* [1..0] */ + unsigned int qpg_qp_delta_level_1 : 2 ; /* [3..2] */ + unsigned int qpg_qp_delta_level_2 : 2 ; /* [5..4] */ + unsigned int qpg_qp_delta_level_3 : 2 ; /* [7..6] */ + unsigned int qpg_qp_delta_level_4 : 2 ; /* [9..8] */ + unsigned int qpg_qp_delta_level_5 : 2 ; /* [11..10] */ + unsigned int qpg_qp_delta_level_6 : 2 ; /* [13..12] */ + unsigned int qpg_qp_delta_level_7 : 2 ; /* [15..14] */ + unsigned int qpg_qp_delta_level_8 : 2 ; /* [17..16] */ + unsigned int qpg_qp_delta_level_9 : 2 ; /* [19..18] */ + unsigned int qpg_qp_delta_level_10 : 2 ; /* [21..20] */ + unsigned int qpg_qp_delta_level_11 : 2 ; /* [23..22] */ + unsigned int qpg_qp_delta_level_12 : 2 ; /* [25..24] */ + unsigned int qpg_qp_delta_level_13 : 2 ; /* [27..26] */ + unsigned int qpg_qp_delta_level_14 : 2 ; /* [29..28] */ + unsigned int qpg_qp_delta_level_15 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_DELTA_LEVEL; + +/* Define the union U_VEDU_QPG_MADI_SWITCH_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_qp_madi_switch_thr : 5 ; /* [4..0] */ + unsigned int Reserved_306 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_MADI_SWITCH_THR; + +/* Define the union U_VEDU_QPG_CU32_DELTA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_cu32_delta_low : 4 ; /* [3..0] */ + unsigned int qpg_cu32_delta_high : 4 ; /* [7..4] */ + unsigned int Reserved_307 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU32_DELTA; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG00 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda00 : 20 ; /* [19..0] */ + unsigned int Reserved_308 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG00; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG01 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda01 : 20 ; /* [19..0] */ + unsigned int Reserved_309 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG01; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG02 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda02 : 20 ; /* [19..0] */ + unsigned int Reserved_310 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG02; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG03 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda03 : 20 ; /* [19..0] */ + unsigned int Reserved_311 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG03; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG04 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda04 : 20 ; /* [19..0] */ + unsigned int Reserved_312 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG04; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG05 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda05 : 20 ; /* [19..0] */ + unsigned int Reserved_313 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG05; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG06 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda06 : 20 ; /* [19..0] */ + unsigned int Reserved_314 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG06; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG07 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda07 : 20 ; /* [19..0] */ + unsigned int Reserved_315 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG07; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG08 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda08 : 20 ; /* [19..0] */ + unsigned int Reserved_316 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG08; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG09 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda09 : 20 ; /* [19..0] */ + unsigned int Reserved_317 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG09; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG10 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda10 : 20 ; /* [19..0] */ + unsigned int Reserved_318 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG10; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG11 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda11 : 20 ; /* [19..0] */ + unsigned int Reserved_319 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG11; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG12 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda12 : 20 ; /* [19..0] */ + unsigned int Reserved_320 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG12; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG13 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda13 : 20 ; /* [19..0] */ + unsigned int Reserved_321 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG13; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG14 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda14 : 20 ; /* [19..0] */ + unsigned int Reserved_322 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG14; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG15 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda15 : 20 ; /* [19..0] */ + unsigned int Reserved_323 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG15; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG16 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda16 : 20 ; /* [19..0] */ + unsigned int Reserved_324 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG16; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG17 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda17 : 20 ; /* [19..0] */ + unsigned int Reserved_325 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG17; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG18 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda18 : 20 ; /* [19..0] */ + unsigned int Reserved_326 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG18; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG19 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda19 : 20 ; /* [19..0] */ + unsigned int Reserved_327 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG19; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG20 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda20 : 20 ; /* [19..0] */ + unsigned int Reserved_328 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG20; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG21 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda21 : 20 ; /* [19..0] */ + unsigned int Reserved_329 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG21; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG22 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda22 : 20 ; /* [19..0] */ + unsigned int Reserved_330 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG22; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG23 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda23 : 20 ; /* [19..0] */ + unsigned int Reserved_331 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG23; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG24 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda24 : 20 ; /* [19..0] */ + unsigned int Reserved_332 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG24; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG25 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda25 : 20 ; /* [19..0] */ + unsigned int Reserved_333 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG25; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG26 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda26 : 20 ; /* [19..0] */ + unsigned int Reserved_334 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG26; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG27 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda27 : 20 ; /* [19..0] */ + unsigned int Reserved_335 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG27; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG28 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda28 : 20 ; /* [19..0] */ + unsigned int Reserved_336 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG28; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG29 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda29 : 20 ; /* [19..0] */ + unsigned int Reserved_337 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG29; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG30 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda30 : 20 ; /* [19..0] */ + unsigned int Reserved_338 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG30; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG31 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda31 : 20 ; /* [19..0] */ + unsigned int Reserved_339 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG31; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG32 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda32 : 20 ; /* [19..0] */ + unsigned int Reserved_340 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG32; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG33 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda33 : 20 ; /* [19..0] */ + unsigned int Reserved_341 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG33; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG34 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda34 : 20 ; /* [19..0] */ + unsigned int Reserved_342 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG34; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG35 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda35 : 20 ; /* [19..0] */ + unsigned int Reserved_343 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG35; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG36 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda36 : 20 ; /* [19..0] */ + unsigned int Reserved_344 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG36; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG37 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda37 : 20 ; /* [19..0] */ + unsigned int Reserved_345 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG37; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG38 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda38 : 20 ; /* [19..0] */ + unsigned int Reserved_346 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG38; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG39 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda39 : 20 ; /* [19..0] */ + unsigned int Reserved_347 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG39; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG40 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda40 : 20 ; /* [19..0] */ + unsigned int Reserved_348 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG40; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG41 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda41 : 20 ; /* [19..0] */ + unsigned int Reserved_349 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG41; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG42 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda42 : 20 ; /* [19..0] */ + unsigned int Reserved_350 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG42; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG43 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda43 : 20 ; /* [19..0] */ + unsigned int Reserved_351 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG43; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG44 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda44 : 20 ; /* [19..0] */ + unsigned int Reserved_352 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG44; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG45 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda45 : 20 ; /* [19..0] */ + unsigned int Reserved_353 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG45; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG46 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda46 : 20 ; /* [19..0] */ + unsigned int Reserved_354 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG46; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG47 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda47 : 20 ; /* [19..0] */ + unsigned int Reserved_355 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG47; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG48 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda48 : 20 ; /* [19..0] */ + unsigned int Reserved_356 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG48; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG49 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda49 : 20 ; /* [19..0] */ + unsigned int Reserved_357 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG49; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG50 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda50 : 20 ; /* [19..0] */ + unsigned int Reserved_358 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG50; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG51 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda51 : 20 ; /* [19..0] */ + unsigned int Reserved_359 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG51; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG52 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda52 : 20 ; /* [19..0] */ + unsigned int Reserved_360 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG52; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG53 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda53 : 20 ; /* [19..0] */ + unsigned int Reserved_361 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG53; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG54 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda54 : 20 ; /* [19..0] */ + unsigned int Reserved_362 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG54; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG55 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda55 : 20 ; /* [19..0] */ + unsigned int Reserved_363 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG55; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG56 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda56 : 20 ; /* [19..0] */ + unsigned int Reserved_364 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG56; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG57 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda57 : 20 ; /* [19..0] */ + unsigned int Reserved_365 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG57; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG58 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda58 : 20 ; /* [19..0] */ + unsigned int Reserved_366 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG58; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG59 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda59 : 20 ; /* [19..0] */ + unsigned int Reserved_367 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG59; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG60 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda60 : 20 ; /* [19..0] */ + unsigned int Reserved_368 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG60; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG61 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda61 : 20 ; /* [19..0] */ + unsigned int Reserved_369 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG61; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG62 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda62 : 20 ; /* [19..0] */ + unsigned int Reserved_370 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG62; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG63 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda63 : 20 ; /* [19..0] */ + unsigned int Reserved_371 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG63; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG64 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda64 : 20 ; /* [19..0] */ + unsigned int Reserved_372 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG64; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG65 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda65 : 20 ; /* [19..0] */ + unsigned int Reserved_373 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG65; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG66 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda66 : 20 ; /* [19..0] */ + unsigned int Reserved_374 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG66; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG67 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda67 : 20 ; /* [19..0] */ + unsigned int Reserved_375 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG67; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG68 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda68 : 20 ; /* [19..0] */ + unsigned int Reserved_376 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG68; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG69 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda69 : 20 ; /* [19..0] */ + unsigned int Reserved_377 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG69; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG70 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda70 : 20 ; /* [19..0] */ + unsigned int Reserved_378 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG70; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG71 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda71 : 20 ; /* [19..0] */ + unsigned int Reserved_379 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG71; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG72 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda72 : 20 ; /* [19..0] */ + unsigned int Reserved_380 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG72; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG73 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda73 : 20 ; /* [19..0] */ + unsigned int Reserved_381 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG73; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG74 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda74 : 20 ; /* [19..0] */ + unsigned int Reserved_382 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG74; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG75 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda75 : 20 ; /* [19..0] */ + unsigned int Reserved_383 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG75; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG76 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda76 : 20 ; /* [19..0] */ + unsigned int Reserved_384 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG76; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG77 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda77 : 20 ; /* [19..0] */ + unsigned int Reserved_385 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG77; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG78 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda78 : 20 ; /* [19..0] */ + unsigned int Reserved_386 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG78; + +/* Define the union U_VEDU_QPG_QP_LAMBDA_CTRL_REG79 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda79 : 20 ; /* [19..0] */ + unsigned int Reserved_387 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_LAMBDA_CTRL_REG79; + +/* Define the union U_VEDU_QPG_LAMBDA_MODE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_lambda_qp_offset : 5 ; /* [4..0] */ + unsigned int Reserved_390 : 3 ; /* [7..5] */ + unsigned int qpg_rdo_lambda_choose_mode : 2 ; /* [9..8] */ + unsigned int Reserved_389 : 2 ; /* [11..10] */ + unsigned int qpg_lambda_inter_stredge_en : 1 ; /* [12] */ + unsigned int Reserved_388 : 19 ; /* [31..13] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_LAMBDA_MODE; + +/* Define the union U_VEDU_QPG_QP_RESTRAIN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_qp_restrain_madi_thr : 6 ; /* [5..0] */ + unsigned int Reserved_393 : 2 ; /* [7..6] */ + unsigned int qpg_qp_restrain_en : 1 ; /* [8] */ + unsigned int qpg_qp_restrain_mode : 2 ; /* [10..9] */ + unsigned int Reserved_392 : 1 ; /* [11] */ + unsigned int qpg_qp_restrain_delta_blk16 : 4 ; /* [15..12] */ + unsigned int qpg_qp_restrain_delta_blk32 : 4 ; /* [19..16] */ + unsigned int Reserved_391 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_QP_RESTRAIN; + +/* Define the union U_VEDU_QPG_CU_MIN_SAD_REG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_min_sad_level : 16 ; /* [15..0] */ + unsigned int qpg_low_min_sad_mode : 2 ; /* [17..16] */ + unsigned int qpg_high_min_sad_mode : 2 ; /* [19..18] */ + unsigned int qpg_min_sad_madi_en : 1 ; /* [20] */ + unsigned int qpg_min_sad_qp_restrain_en : 1 ; /* [21] */ + unsigned int Reserved_394 : 10 ; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_CU_MIN_SAD_REG; + +/* Define the union U_VEDU_QPG_SMART_REG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_396 : 1 ; /* [0] */ + unsigned int qpg_smart_abs_qp_mode : 1 ; /* [1] */ + unsigned int qpg_smart_get_cu32_qp_mode : 2 ; /* [3..2] */ + unsigned int qpg_smart_get_cu64_qp_mode : 2 ; /* [5..4] */ + unsigned int qpg_qp_detlta_size_cu64 : 1 ; /* [6] */ + unsigned int Reserved_395 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_SMART_REG; + +/* Define the union U_VEDU_QPG_FLAT_REGION */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int qpg_flat_region_qp_delta : 4 ; /* [3..0] */ + unsigned int qpg_flat_region_max_qp : 6 ; /* [9..4] */ + unsigned int Reserved_399 : 2 ; /* [11..10] */ + unsigned int qpg_flat_region_min_qp : 6 ; /* [17..12] */ + unsigned int Reserved_398 : 6 ; /* [23..18] */ + unsigned int vcpi_cu32_use_cu16_mean_en : 1 ; /* [24] */ + unsigned int Reserved_397 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_QPG_FLAT_REGION; + +/* Define the union U_VEDU_IME_INTER_MODE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_layer3to2_en : 1 ; /* [0] */ + unsigned int ime_inter8x8_en : 1 ; /* [1] */ + unsigned int ime_flat_region_force_low3layer : 1 ; /* [2] */ + unsigned int Reserved_404 : 1 ; /* [3] */ + unsigned int ime_high3pre_en : 2 ; /* [5..4] */ + unsigned int Reserved_403 : 2 ; /* [7..6] */ + unsigned int ime_intra4_lowpow_en : 1 ; /* [8] */ + unsigned int Reserved_402 : 23 ; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_INTER_MODE; + +/* Define the union U_VEDU_IME_RDOCFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_lambdaoff8 : 16 ; /* [15..0] */ + unsigned int ime_lambdaoff16 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_RDOCFG; + +/* Define the union U_VEDU_IME_FME_LPOW_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_lowpow_fme_thr0 : 6 ; /* [5..0] */ + unsigned int ime_lowpow_fme_thr1 : 6 ; /* [11..6] */ + unsigned int Reserved_405 : 20 ; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_FME_LPOW_THR; + +/* Define the union U_VEDU_IME_LAYER3TO2_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_layer3to2_thr0 : 10 ; /* [9..0] */ + unsigned int Reserved_407 : 6 ; /* [15..10] */ + unsigned int ime_layer3to2_thr1 : 10 ; /* [25..16] */ + unsigned int Reserved_406 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_LAYER3TO2_THR; + +/* Define the union U_VEDU_IME_LAYER3TO2_THR1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_layer3to2_cost_diff_thr : 10 ; /* [9..0] */ + unsigned int Reserved_408 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_LAYER3TO2_THR1; + +/* Define the union U_VEDU_IME_LAYER3TO1_THR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_layer3to1_en : 1 ; /* [0] */ + unsigned int Reserved_410 : 7 ; /* [7..1] */ + unsigned int ime_layer3to1_pu64_madi_thr : 7 ; /* [14..8] */ + unsigned int Reserved_409 : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_LAYER3TO1_THR; + +/* Define the union U_VEDU_IME_LAYER3TO1_THR1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ime_layer3to1_pu32_cost_thr : 16 ; /* [15..0] */ + unsigned int ime_layer3to1_pu64_cost_thr : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_IME_LAYER3TO1_THR1; + +/* Define the union U_VEDU_FME_BIAS_COST0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_pu8_bias_cost : 16 ; /* [15..0] */ + unsigned int fme_pu16_bias_cost : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_FME_BIAS_COST0; + +/* Define the union U_VEDU_FME_BIAS_COST1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_pu32_bias_cost : 16 ; /* [15..0] */ + unsigned int fme_pu64_bias_cost : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_FME_BIAS_COST1; + +/* Define the union U_VEDU_FME_PU64_LWP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_pu64_lwp_flag : 1 ; /* [0] */ + unsigned int Reserved_412 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_FME_PU64_LWP; + +/* Define the union U_VEDU_MRG_FORCE_ZERO_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_force_zero_en : 1 ; /* [0] */ + unsigned int mrg_force_y_zero_en : 1 ; /* [1] */ + unsigned int mrg_force_u_zero_en : 1 ; /* [2] */ + unsigned int mrg_force_v_zero_en : 1 ; /* [3] */ + unsigned int fme_lpw_en : 1 ; /* [4] */ + unsigned int dct4_en : 1 ; /* [5] */ + unsigned int force_adapt_en : 1 ; /* [6] */ + unsigned int Reserved_415 : 5 ; /* [11..7] */ + unsigned int rqt_bias_weight : 4 ; /* [15..12] */ + unsigned int fme_lpw_th : 10 ; /* [25..16] */ + unsigned int Reserved_414 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_FORCE_ZERO_EN; + +/* Define the union U_VEDU_MRG_FORCE_SKIP_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_417 : 4 ; /* [3..0] */ + unsigned int mrg_force_skip_en : 1 ; /* [4] */ + unsigned int Reserved_416 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_FORCE_SKIP_EN; + +/* Define the union U_VEDU_MRG_BIAS_COST0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_pu8_bias_cost : 16 ; /* [15..0] */ + unsigned int mrg_pu16_bias_cost : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_BIAS_COST0; + +/* Define the union U_VEDU_MRG_BIAS_COST1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_pu32_bias_cost : 16 ; /* [15..0] */ + unsigned int mrg_pu64_bias_cost : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_BIAS_COST1; + +/* Define the union U_VEDU_MRG_ABS_OFFSET0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_pu8_abs_offset : 16 ; /* [15..0] */ + unsigned int mrg_pu16_abs_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_ABS_OFFSET0; + +/* Define the union U_VEDU_MRG_ABS_OFFSET1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_pu32_abs_offset : 16 ; /* [15..0] */ + unsigned int mrg_pu64_abs_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_ABS_OFFSET1; + +/* Define the union U_VEDU_MRG_ADJ_WEIGHT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cu8_fz_weight : 4 ; /* [3..0] */ + unsigned int cu16_fz_weight : 4 ; /* [7..4] */ + unsigned int cu32_fz_weight : 4 ; /* [11..8] */ + unsigned int cu64_fz_weight : 4 ; /* [15..12] */ + unsigned int cu8_fz_adapt_weight : 4 ; /* [19..16] */ + unsigned int cu16_fz_adapt_weight : 4 ; /* [23..20] */ + unsigned int cu32_fz_adapt_weight : 4 ; /* [27..24] */ + unsigned int cu64_fz_adapt_weight : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_MRG_ADJ_WEIGHT; + +/* Define the union U_VEDU_INTRA_CFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int constrained_intra_pred_flag : 1 ; /* [0] */ + unsigned int Reserved_421 : 3 ; /* [3..1] */ + unsigned int vcpi_force_cu16_only_dc_pl : 1 ; /* [4] */ + unsigned int Reserved_420 : 3 ; /* [7..5] */ + unsigned int vcpi_force_cu32_only_dc_pl : 1 ; /* [8] */ + unsigned int Reserved_419 : 23 ; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CFG; + +/* Define the union U_VEDU_INTRA_SMOOTH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_smooth : 1 ; /* [0] */ + unsigned int Reserved_422 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_SMOOTH; + +/* Define the union U_VEDU_INTRA_BIT_WEIGHT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_bit_weight : 4 ; /* [3..0] */ + unsigned int Reserved_423 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_BIT_WEIGHT; + +/* Define the union U_VEDU_INTRA_RDO_COST_OFFSET_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu16_rdo_cost_offset : 16 ; /* [15..0] */ + unsigned int intra_cu32_rdo_cost_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_RDO_COST_OFFSET_0; + +/* Define the union U_VEDU_INTRA_RDO_COST_OFFSET_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu4_rdo_cost_offset : 16 ; /* [15..0] */ + unsigned int intra_cu8_rdo_cost_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_RDO_COST_OFFSET_1; + +/* Define the union U_VEDU_INTRA_NO_DC_COST_OFFSET_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu16_non_dc_mode_offset : 16 ; /* [15..0] */ + unsigned int intra_cu32_non_dc_mode_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_NO_DC_COST_OFFSET_0; + +/* Define the union U_VEDU_INTRA_NO_DC_COST_OFFSET_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu4_non_dc_mode_offset : 16 ; /* [15..0] */ + unsigned int intra_cu8_non_dc_mode_offset : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_NO_DC_COST_OFFSET_1; + +/* Define the union U_VEDU_INTRA_CHNL4_ANG_0EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu4_mode0_en : 1 ; /* [0] */ + unsigned int intra_cu4_mode1_en : 1 ; /* [1] */ + unsigned int intra_cu4_mode2_en : 1 ; /* [2] */ + unsigned int intra_cu4_mode3_en : 1 ; /* [3] */ + unsigned int intra_cu4_mode4_en : 1 ; /* [4] */ + unsigned int intra_cu4_mode5_en : 1 ; /* [5] */ + unsigned int intra_cu4_mode6_en : 1 ; /* [6] */ + unsigned int intra_cu4_mode7_en : 1 ; /* [7] */ + unsigned int intra_cu4_mode8_en : 1 ; /* [8] */ + unsigned int intra_cu4_mode9_en : 1 ; /* [9] */ + unsigned int intra_cu4_mode10_en : 1 ; /* [10] */ + unsigned int intra_cu4_mode11_en : 1 ; /* [11] */ + unsigned int intra_cu4_mode12_en : 1 ; /* [12] */ + unsigned int intra_cu4_mode13_en : 1 ; /* [13] */ + unsigned int intra_cu4_mode14_en : 1 ; /* [14] */ + unsigned int intra_cu4_mode15_en : 1 ; /* [15] */ + unsigned int intra_cu4_mode16_en : 1 ; /* [16] */ + unsigned int intra_cu4_mode17_en : 1 ; /* [17] */ + unsigned int intra_cu4_mode18_en : 1 ; /* [18] */ + unsigned int intra_cu4_mode19_en : 1 ; /* [19] */ + unsigned int intra_cu4_mode20_en : 1 ; /* [20] */ + unsigned int intra_cu4_mode21_en : 1 ; /* [21] */ + unsigned int intra_cu4_mode22_en : 1 ; /* [22] */ + unsigned int intra_cu4_mode23_en : 1 ; /* [23] */ + unsigned int intra_cu4_mode24_en : 1 ; /* [24] */ + unsigned int intra_cu4_mode25_en : 1 ; /* [25] */ + unsigned int intra_cu4_mode26_en : 1 ; /* [26] */ + unsigned int intra_cu4_mode27_en : 1 ; /* [27] */ + unsigned int intra_cu4_mode28_en : 1 ; /* [28] */ + unsigned int intra_cu4_mode29_en : 1 ; /* [29] */ + unsigned int intra_cu4_mode30_en : 1 ; /* [30] */ + unsigned int intra_cu4_mode31_en : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL4_ANG_0EN; + +/* Define the union U_VEDU_INTRA_CHNL4_ANG_1EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu4_mode32_en : 1 ; /* [0] */ + unsigned int intra_cu4_mode33_en : 1 ; /* [1] */ + unsigned int intra_cu4_mode34_en : 1 ; /* [2] */ + unsigned int Reserved_424 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL4_ANG_1EN; + +/* Define the union U_VEDU_INTRA_CHNL8_ANG_0EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu8_mode0_en : 1 ; /* [0] */ + unsigned int intra_cu8_mode1_en : 1 ; /* [1] */ + unsigned int intra_cu8_mode2_en : 1 ; /* [2] */ + unsigned int intra_cu8_mode3_en : 1 ; /* [3] */ + unsigned int intra_cu8_mode4_en : 1 ; /* [4] */ + unsigned int intra_cu8_mode5_en : 1 ; /* [5] */ + unsigned int intra_cu8_mode6_en : 1 ; /* [6] */ + unsigned int intra_cu8_mode7_en : 1 ; /* [7] */ + unsigned int intra_cu8_mode8_en : 1 ; /* [8] */ + unsigned int intra_cu8_mode9_en : 1 ; /* [9] */ + unsigned int intra_cu8_mode10_en : 1 ; /* [10] */ + unsigned int intra_cu8_mode11_en : 1 ; /* [11] */ + unsigned int intra_cu8_mode12_en : 1 ; /* [12] */ + unsigned int intra_cu8_mode13_en : 1 ; /* [13] */ + unsigned int intra_cu8_mode14_en : 1 ; /* [14] */ + unsigned int intra_cu8_mode15_en : 1 ; /* [15] */ + unsigned int intra_cu8_mode16_en : 1 ; /* [16] */ + unsigned int intra_cu8_mode17_en : 1 ; /* [17] */ + unsigned int intra_cu8_mode18_en : 1 ; /* [18] */ + unsigned int intra_cu8_mode19_en : 1 ; /* [19] */ + unsigned int intra_cu8_mode20_en : 1 ; /* [20] */ + unsigned int intra_cu8_mode21_en : 1 ; /* [21] */ + unsigned int intra_cu8_mode22_en : 1 ; /* [22] */ + unsigned int intra_cu8_mode23_en : 1 ; /* [23] */ + unsigned int intra_cu8_mode24_en : 1 ; /* [24] */ + unsigned int intra_cu8_mode25_en : 1 ; /* [25] */ + unsigned int intra_cu8_mode26_en : 1 ; /* [26] */ + unsigned int intra_cu8_mode27_en : 1 ; /* [27] */ + unsigned int intra_cu8_mode28_en : 1 ; /* [28] */ + unsigned int intra_cu8_mode29_en : 1 ; /* [29] */ + unsigned int intra_cu8_mode30_en : 1 ; /* [30] */ + unsigned int intra_cu8_mode31_en : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL8_ANG_0EN; + +/* Define the union U_VEDU_INTRA_CHNL8_ANG_1EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu8_mode32_en : 1 ; /* [0] */ + unsigned int intra_cu8_mode33_en : 1 ; /* [1] */ + unsigned int intra_cu8_mode34_en : 1 ; /* [2] */ + unsigned int Reserved_425 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL8_ANG_1EN; + +/* Define the union U_VEDU_INTRA_CHNL16_ANG_0EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu16_mode0_en : 1 ; /* [0] */ + unsigned int intra_cu16_mode1_en : 1 ; /* [1] */ + unsigned int intra_cu16_mode2_en : 1 ; /* [2] */ + unsigned int intra_cu16_mode3_en : 1 ; /* [3] */ + unsigned int intra_cu16_mode4_en : 1 ; /* [4] */ + unsigned int intra_cu16_mode5_en : 1 ; /* [5] */ + unsigned int intra_cu16_mode6_en : 1 ; /* [6] */ + unsigned int intra_cu16_mode7_en : 1 ; /* [7] */ + unsigned int intra_cu16_mode8_en : 1 ; /* [8] */ + unsigned int intra_cu16_mode9_en : 1 ; /* [9] */ + unsigned int intra_cu16_mode10_en : 1 ; /* [10] */ + unsigned int intra_cu16_mode11_en : 1 ; /* [11] */ + unsigned int intra_cu16_mode12_en : 1 ; /* [12] */ + unsigned int intra_cu16_mode13_en : 1 ; /* [13] */ + unsigned int intra_cu16_mode14_en : 1 ; /* [14] */ + unsigned int intra_cu16_mode15_en : 1 ; /* [15] */ + unsigned int intra_cu16_mode16_en : 1 ; /* [16] */ + unsigned int intra_cu16_mode17_en : 1 ; /* [17] */ + unsigned int intra_cu16_mode18_en : 1 ; /* [18] */ + unsigned int intra_cu16_mode19_en : 1 ; /* [19] */ + unsigned int intra_cu16_mode20_en : 1 ; /* [20] */ + unsigned int intra_cu16_mode21_en : 1 ; /* [21] */ + unsigned int intra_cu16_mode22_en : 1 ; /* [22] */ + unsigned int intra_cu16_mode23_en : 1 ; /* [23] */ + unsigned int intra_cu16_mode24_en : 1 ; /* [24] */ + unsigned int intra_cu16_mode25_en : 1 ; /* [25] */ + unsigned int intra_cu16_mode26_en : 1 ; /* [26] */ + unsigned int intra_cu16_mode27_en : 1 ; /* [27] */ + unsigned int intra_cu16_mode28_en : 1 ; /* [28] */ + unsigned int intra_cu16_mode29_en : 1 ; /* [29] */ + unsigned int intra_cu16_mode30_en : 1 ; /* [30] */ + unsigned int intra_cu16_mode31_en : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL16_ANG_0EN; + +/* Define the union U_VEDU_INTRA_CHNL16_ANG_1EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu16_mode32_en : 1 ; /* [0] */ + unsigned int intra_cu16_mode33_en : 1 ; /* [1] */ + unsigned int intra_cu16_mode34_en : 1 ; /* [2] */ + unsigned int Reserved_426 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL16_ANG_1EN; + +/* Define the union U_VEDU_INTRA_CHNL32_ANG_0EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu32_mode0_en : 1 ; /* [0] */ + unsigned int intra_cu32_mode1_en : 1 ; /* [1] */ + unsigned int intra_cu32_mode2_en : 1 ; /* [2] */ + unsigned int intra_cu32_mode3_en : 1 ; /* [3] */ + unsigned int intra_cu32_mode4_en : 1 ; /* [4] */ + unsigned int intra_cu32_mode5_en : 1 ; /* [5] */ + unsigned int intra_cu32_mode6_en : 1 ; /* [6] */ + unsigned int intra_cu32_mode7_en : 1 ; /* [7] */ + unsigned int intra_cu32_mode8_en : 1 ; /* [8] */ + unsigned int intra_cu32_mode9_en : 1 ; /* [9] */ + unsigned int intra_cu32_mode10_en : 1 ; /* [10] */ + unsigned int intra_cu32_mode11_en : 1 ; /* [11] */ + unsigned int intra_cu32_mode12_en : 1 ; /* [12] */ + unsigned int intra_cu32_mode13_en : 1 ; /* [13] */ + unsigned int intra_cu32_mode14_en : 1 ; /* [14] */ + unsigned int intra_cu32_mode15_en : 1 ; /* [15] */ + unsigned int intra_cu32_mode16_en : 1 ; /* [16] */ + unsigned int intra_cu32_mode17_en : 1 ; /* [17] */ + unsigned int intra_cu32_mode18_en : 1 ; /* [18] */ + unsigned int intra_cu32_mode19_en : 1 ; /* [19] */ + unsigned int intra_cu32_mode20_en : 1 ; /* [20] */ + unsigned int intra_cu32_mode21_en : 1 ; /* [21] */ + unsigned int intra_cu32_mode22_en : 1 ; /* [22] */ + unsigned int intra_cu32_mode23_en : 1 ; /* [23] */ + unsigned int intra_cu32_mode24_en : 1 ; /* [24] */ + unsigned int intra_cu32_mode25_en : 1 ; /* [25] */ + unsigned int intra_cu32_mode26_en : 1 ; /* [26] */ + unsigned int intra_cu32_mode27_en : 1 ; /* [27] */ + unsigned int intra_cu32_mode28_en : 1 ; /* [28] */ + unsigned int intra_cu32_mode29_en : 1 ; /* [29] */ + unsigned int intra_cu32_mode30_en : 1 ; /* [30] */ + unsigned int intra_cu32_mode31_en : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL32_ANG_0EN; + +/* Define the union U_VEDU_INTRA_CHNL32_ANG_1EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_cu32_mode32_en : 1 ; /* [0] */ + unsigned int intra_cu32_mode33_en : 1 ; /* [1] */ + unsigned int intra_cu32_mode34_en : 1 ; /* [2] */ + unsigned int Reserved_427 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_CHNL32_ANG_1EN; + +/* Define the union U_VEDU_INTRA_RDO_COST_OFFSET_3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_h264_rdo_cost_offset : 16 ; /* [15..0] */ + unsigned int Reserved_428 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_INTRA_RDO_COST_OFFSET_3; + +/* Define the union U_VEDU_PMV_TMV_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pmv_tmv_en : 1 ; /* [0] */ + unsigned int Reserved_430 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PMV_TMV_EN; + +/* Define the union U_VEDU_TQITQ_DEADZONE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int tqitq_deadzone_intra_slice : 8 ; /* [7..0] */ + unsigned int tqitq_deadzone_inter_slice : 8 ; /* [15..8] */ + unsigned int Reserved_432 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_TQITQ_DEADZONE; + +/* Define the union U_VEDU_SEL_OFFSET_STRENGTH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sel_offset_strength : 3 ; /* [2..0] */ + unsigned int Reserved_435 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_SEL_OFFSET_STRENGTH; + +/* Define the union U_VEDU_SEL_CU32_DC_AC_TH_OFFSET */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sel_cu32_dc_ac_th_offset : 2 ; /* [1..0] */ + unsigned int Reserved_436 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_SEL_CU32_DC_AC_TH_OFFSET; + +/* Define the union U_VEDU_SEL_CU32_QP_TH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sel_cu32_qp0_th : 6 ; /* [5..0] */ + unsigned int Reserved_438 : 2 ; /* [7..6] */ + unsigned int sel_cu32_qp1_th : 6 ; /* [13..8] */ + unsigned int Reserved_437 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_SEL_CU32_QP_TH; + +/* Define the union U_VEDU_SEL_RES_DC_AC_TH */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sel_res16_luma_dc_th : 4 ; /* [3..0] */ + unsigned int sel_res16_chroma_dc_th : 4 ; /* [7..4] */ + unsigned int sel_res16_luma_ac_th : 4 ; /* [11..8] */ + unsigned int sel_res16_chroma_ac_th : 4 ; /* [15..12] */ + unsigned int sel_res32_luma_dc_th : 4 ; /* [19..16] */ + unsigned int sel_res32_chroma_dc_th : 4 ; /* [23..20] */ + unsigned int sel_res32_luma_ac_th : 4 ; /* [27..24] */ + unsigned int sel_res32_chroma_ac_th : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_SEL_RES_DC_AC_TH; + +/* Define the union U_VEDU_EMAR_WAIT_TIM_OUT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_wtmax : 10 ; /* [9..0] */ + unsigned int vcpi_rtmax : 10 ; /* [19..10] */ + unsigned int Reserved_442 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_WAIT_TIM_OUT; + +/* Define the union U_VEDU_EMAR_RCH_RPT_TH0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch00_rrmax : 5 ; /* [4..0] */ + unsigned int vcpi_ch01_rrmax : 5 ; /* [9..5] */ + unsigned int vcpi_ch02_rrmax : 5 ; /* [14..10] */ + unsigned int vcpi_ch03_rrmax : 5 ; /* [19..15] */ + unsigned int vcpi_ch04_rrmax : 5 ; /* [24..20] */ + unsigned int vcpi_ch05_rrmax : 5 ; /* [29..25] */ + unsigned int Reserved_443 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_RCH_RPT_TH0; + +/* Define the union U_VEDU_EMAR_RCH_RPT_TH1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch06_rrmax : 5 ; /* [4..0] */ + unsigned int vcpi_ch07_rrmax : 5 ; /* [9..5] */ + unsigned int vcpi_ch08_rrmax : 5 ; /* [14..10] */ + unsigned int vcpi_ch09_rrmax : 5 ; /* [19..15] */ + unsigned int vcpi_ch10_rrmax : 5 ; /* [24..20] */ + unsigned int vcpi_ch11_rrmax : 5 ; /* [29..25] */ + unsigned int Reserved_444 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_RCH_RPT_TH1; + +/* Define the union U_VEDU_EMAR_RCH_RPT_TH2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch12_rrmax : 5 ; /* [4..0] */ + unsigned int Reserved_445 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_RCH_RPT_TH2; + +/* Define the union U_VEDU_EMAR_WCH_RPT_TH0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch00_wrmax : 5 ; /* [4..0] */ + unsigned int vcpi_ch01_wrmax : 5 ; /* [9..5] */ + unsigned int vcpi_ch02_wrmax : 5 ; /* [14..10] */ + unsigned int vcpi_ch03_wrmax : 5 ; /* [19..15] */ + unsigned int vcpi_ch04_wrmax : 5 ; /* [24..20] */ + unsigned int vcpi_ch05_wrmax : 5 ; /* [29..25] */ + unsigned int Reserved_446 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_WCH_RPT_TH0; + +/* Define the union U_VEDU_EMAR_WCH_RPT_TH1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch06_wrmax : 5 ; /* [4..0] */ + unsigned int vcpi_ch07_wrmax : 5 ; /* [9..5] */ + unsigned int vcpi_ch08_wrmax : 5 ; /* [14..10] */ + unsigned int vcpi_ch09_wrmax : 5 ; /* [19..15] */ + unsigned int vcpi_ch10_wrmax : 5 ; /* [24..20] */ + unsigned int vcpi_ch11_wrmax : 5 ; /* [29..25] */ + unsigned int Reserved_447 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_WCH_RPT_TH1; + +/* Define the union U_VEDU_EMAR_WCH_RPT_TH2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_ch12_wrmax : 5 ; /* [4..0] */ + unsigned int vcpi_ch13_wrmax : 5 ; /* [9..5] */ + unsigned int vcpi_ch14_wrmax : 5 ; /* [14..10] */ + unsigned int Reserved_448 : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_WCH_RPT_TH2; + +/* Define the union U_VEDU_EMAR_SCRAMBLE_TYPE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int emar_rec_b7_scramble : 1 ; /* [0] */ + unsigned int emar_rec_b8_scramble : 2 ; /* [2..1] */ + unsigned int emar_ori_y_b7_scramble : 1 ; /* [3] */ + unsigned int emar_ori_y_b8_scramble : 2 ; /* [5..4] */ + unsigned int emar_ori_uv_b7_scramble : 1 ; /* [6] */ + unsigned int Reserved_449 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_EMAR_SCRAMBLE_TYPE; + +/* Define the union U_VEDU_PACK_CU_PARAMETER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pack_vcpi2cu_tq_bypass_enabled_flag : 1 ; /* [0] */ + unsigned int reserved1 : 3 ; /* [3..1] */ + unsigned int pack_vcpi2cu_qp_min_cu_size : 3 ; /* [6..4] */ + unsigned int Reserved_451 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PACK_CU_PARAMETER; + +/* Define the union U_VEDU_PACK_PCM_PARAMETER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pack_vcpi2pu_log2_min_ipcm_cbsizey : 3 ; /* [2..0] */ + unsigned int Reserved_453 : 1 ; /* [3] */ + unsigned int pack_vcpi2pu_log2_max_ipcm_cbsizey : 3 ; /* [6..4] */ + unsigned int Reserved_452 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PACK_PCM_PARAMETER; + +/* Define the union U_VEDU_PACK_TF_SKIP_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pack_vcpi2res_tf_skip_enabled_flag : 1 ; /* [0] */ + unsigned int Reserved_454 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PACK_TF_SKIP_FLAG; + +/* Define the union U_VEDU_CABAC_GLB_CFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_457 : 8 ; /* [7..0] */ + unsigned int cabac_max_num_mergecand : 3 ; /* [10..8] */ + unsigned int Reserved_456 : 5 ; /* [15..11] */ + unsigned int cabac_nal_unit_head : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CABAC_GLB_CFG; + +/* Define the union U_VEDU_CABAC_SLCHDR_SIZE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cabac_slchdr_size_part1 : 5 ; /* [4..0] */ + unsigned int Reserved_458 : 11 ; /* [15..5] */ + unsigned int cabac_slchdr_size_part2 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CABAC_SLCHDR_SIZE; + +/* Define the union U_VEDU_CABAC_SLCHDR_PART1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cabac_slchdr_part1 : 16 ; /* [15..0] */ + unsigned int Reserved_459 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CABAC_SLCHDR_PART1; + +/* Define the union U_VEDU_CABAC_SLCHDR_SIZE_I */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cabac_slchdr_size_part1_i : 5 ; /* [4..0] */ + unsigned int Reserved_460 : 11 ; /* [15..5] */ + unsigned int cabac_slchdr_size_part2_i : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CABAC_SLCHDR_SIZE_I; + +/* Define the union U_VEDU_CABAC_SLCHDR_PART1_I */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cabac_slchdr_part1_i : 16 ; /* [15..0] */ + unsigned int Reserved_461 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_CABAC_SLCHDR_PART1_I; + +/* Define the union U_VEDU_VLC_SLCHDRPARA */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vlc_markingbit : 6 ; /* [5..0] */ + unsigned int reserved1 : 2 ; /* [7..6] */ + unsigned int vlc_reorderbit : 6 ; /* [13..8] */ + unsigned int reserved0 : 2 ; /* [15..14] */ + unsigned int vlc_parabit : 7 ; /* [22..16] */ + unsigned int Reserved_463 : 9 ; /* [31..23] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VLC_SLCHDRPARA; + +/* Define the union U_VEDU_VLC_SVC */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vlc_svc_en : 1 ; /* [0] */ + unsigned int vlc_svc_strm : 24 ; /* [24..1] */ + unsigned int Reserved_464 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VLC_SVC; + +/* Define the union U_VEDU_VLC_SLCHDRPARA_I */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vlc_markingbit_i : 6 ; /* [5..0] */ + unsigned int reserved1 : 2 ; /* [7..6] */ + unsigned int vlc_reorderbit_i : 6 ; /* [13..8] */ + unsigned int reserved0 : 2 ; /* [15..14] */ + unsigned int vlc_parabit_i : 7 ; /* [22..16] */ + unsigned int Reserved_465 : 9 ; /* [31..23] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VLC_SLCHDRPARA_I; + +/* Define the union U_VEDU_VLCST_PTBITS_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vlcst_ptbits_en : 1 ; /* [0] */ + unsigned int Reserved_468 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VLCST_PTBITS_EN; + +/* Define the union U_VEDU_VLCST_PARAMETER */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vlcst_para_set_len : 8 ; /* [7..0] */ + unsigned int vlcst_para_sprat_en : 1 ; /* [8] */ + unsigned int Reserved_470 : 7 ; /* [15..9] */ + unsigned int vlcst_para_set_en : 1 ; /* [16] */ + unsigned int Reserved_469 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_VLCST_PARAMETER; + +/* Define the union U_VEDU_PPFD_ST_CFG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ppfd_st_cmp_en : 1 ; /* [0] */ + unsigned int Reserved_473 : 3 ; /* [3..1] */ + unsigned int ppfd_st_bypass_en : 1 ; /* [4] */ + unsigned int Reserved_472 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_PPFD_ST_CFG; + +/* Define the union U_VEDU_ENV_CHN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int env_chn_curr_id : 4 ; /* [3..0] */ + unsigned int env_chn_goptype : 4 ; /* [7..4] */ + unsigned int env_chn_bfrm_num : 8 ; /* [15..8] */ + unsigned int Reserved_475 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_VEDU_ENV_CHN; + +/* Define the union U_FUNC_VCPI_INTSTAT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_int_ve_eop : 1 ; /* [0] */ + unsigned int vcpi_int_vedu_slice_end : 1 ; /* [1] */ + unsigned int vcpi_int_ve_buffull : 1 ; /* [2] */ + unsigned int vcpi_int_ve_pbitsover : 1 ; /* [3] */ + unsigned int vcpi_int_vedu_brkpt : 1 ; /* [4] */ + unsigned int vcpi_int_vedu_step : 1 ; /* [5] */ + unsigned int vcpi_int_vedu_timeout : 1 ; /* [6] */ + unsigned int vcpi_int_cfg_err : 1 ; /* [7] */ + unsigned int Reserved_477 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VCPI_INTSTAT; + +/* Define the union U_FUNC_VCPI_RAWINT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rint_ve_eop : 1 ; /* [0] */ + unsigned int vcpi_rint_vedu_slice_end : 1 ; /* [1] */ + unsigned int vcpi_rint_ve_buffull : 1 ; /* [2] */ + unsigned int vcpi_rint_ve_pbitsover : 1 ; /* [3] */ + unsigned int vcpi_rint_vedu_brkpt : 1 ; /* [4] */ + unsigned int vcpi_rint_vedu_step : 1 ; /* [5] */ + unsigned int vcpi_rint_vedu_timeout : 1 ; /* [6] */ + unsigned int vcpi_rint_cfg_err : 1 ; /* [7] */ + unsigned int Reserved_478 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VCPI_RAWINT; + +/* Define the union U_FUNC_VCPI_INTSTAT_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_int_ve_eop_s : 1 ; /* [0] */ + unsigned int vcpi_int_vedu_slice_end_s : 1 ; /* [1] */ + unsigned int vcpi_int_ve_buffull_s : 1 ; /* [2] */ + unsigned int vcpi_int_ve_pbitsover_s : 1 ; /* [3] */ + unsigned int vcpi_int_vedu_brkpt_s : 1 ; /* [4] */ + unsigned int vcpi_int_vedu_step_s : 1 ; /* [5] */ + unsigned int vcpi_int_vedu_timeout_s : 1 ; /* [6] */ + unsigned int vcpi_int_cfg_err_s : 1 ; /* [7] */ + unsigned int Reserved_479 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VCPI_INTSTAT_S; + +/* Define the union U_FUNC_VCPI_RAWINT_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_rint_ve_eop_s : 1 ; /* [0] */ + unsigned int vcpi_rint_vedu_slice_end_s : 1 ; /* [1] */ + unsigned int vcpi_rint_ve_buffull_s : 1 ; /* [2] */ + unsigned int vcpi_rint_ve_pbitsover_s : 1 ; /* [3] */ + unsigned int vcpi_rint_vedu_brkpt_s : 1 ; /* [4] */ + unsigned int vcpi_rint_vedu_step_s : 1 ; /* [5] */ + unsigned int vcpi_rint_vedu_timeout_s : 1 ; /* [6] */ + unsigned int vcpi_rint_cfg_err_s : 1 ; /* [7] */ + unsigned int Reserved_480 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VCPI_RAWINT_S; + +/* Define the union U_FUNC_PME_MADI_SUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_madi_sum : 25 ; /* [24..0] */ + unsigned int Reserved_488 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_PME_MADI_SUM; + +/* Define the union U_FUNC_PME_MADP_SUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_madp_sum : 25 ; /* [24..0] */ + unsigned int Reserved_489 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_PME_MADP_SUM; + +/* Define the union U_FUNC_PME_MADI_NUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_madi_num : 17 ; /* [16..0] */ + unsigned int Reserved_490 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_PME_MADI_NUM; + +/* Define the union U_FUNC_PME_MADP_NUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pme_madp_num : 17 ; /* [16..0] */ + unsigned int Reserved_491 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_PME_MADP_NUM; + +/* Define the union U_FUNC_BGGEN_BLOCK_COUNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_bggen_block_count : 18 ; /* [17..0] */ + unsigned int Reserved_495 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_BGGEN_BLOCK_COUNT; + +/* Define the union U_FUNC_BGGEN_FRAME_BGM_DIST */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int vcpi_frame_bgm_dist : 31 ; /* [30..0] */ + unsigned int Reserved_496 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_BGGEN_FRAME_BGM_DIST; + +/* Define the union U_FUNC_VLCST_DSRPTR00 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len0 : 29 ; /* [28..0] */ + unsigned int Reserved_520 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR00; + +/* Define the union U_FUNC_VLCST_DSRPTR01 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum0 : 7 ; /* [6..0] */ + unsigned int Reserved_521 : 24 ; /* [30..7] */ + unsigned int islastslc0 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR01; + +/* Define the union U_FUNC_VLCST_DSRPTR10 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len1 : 29 ; /* [28..0] */ + unsigned int Reserved_522 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR10; + +/* Define the union U_FUNC_VLCST_DSRPTR11 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum1 : 7 ; /* [6..0] */ + unsigned int Reserved_523 : 24 ; /* [30..7] */ + unsigned int islastslc1 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR11; + +/* Define the union U_FUNC_VLCST_DSRPTR20 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len2 : 29 ; /* [28..0] */ + unsigned int Reserved_524 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR20; + +/* Define the union U_FUNC_VLCST_DSRPTR21 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum2 : 7 ; /* [6..0] */ + unsigned int Reserved_525 : 24 ; /* [30..7] */ + unsigned int islastslc2 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR21; + +/* Define the union U_FUNC_VLCST_DSRPTR30 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len3 : 29 ; /* [28..0] */ + unsigned int Reserved_526 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR30; + +/* Define the union U_FUNC_VLCST_DSRPTR31 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum3 : 7 ; /* [6..0] */ + unsigned int Reserved_527 : 24 ; /* [30..7] */ + unsigned int islastslc3 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR31; + +/* Define the union U_FUNC_VLCST_DSRPTR40 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len4 : 29 ; /* [28..0] */ + unsigned int Reserved_528 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR40; + +/* Define the union U_FUNC_VLCST_DSRPTR41 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum4 : 7 ; /* [6..0] */ + unsigned int Reserved_529 : 24 ; /* [30..7] */ + unsigned int islastslc4 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR41; + +/* Define the union U_FUNC_VLCST_DSRPTR50 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len5 : 29 ; /* [28..0] */ + unsigned int Reserved_530 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR50; + +/* Define the union U_FUNC_VLCST_DSRPTR51 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum5 : 7 ; /* [6..0] */ + unsigned int Reserved_531 : 24 ; /* [30..7] */ + unsigned int islastslc5 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR51; + +/* Define the union U_FUNC_VLCST_DSRPTR60 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len6 : 29 ; /* [28..0] */ + unsigned int Reserved_532 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR60; + +/* Define the union U_FUNC_VLCST_DSRPTR61 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum6 : 7 ; /* [6..0] */ + unsigned int Reserved_533 : 24 ; /* [30..7] */ + unsigned int islastslc6 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR61; + +/* Define the union U_FUNC_VLCST_DSRPTR70 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len7 : 29 ; /* [28..0] */ + unsigned int Reserved_534 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR70; + +/* Define the union U_FUNC_VLCST_DSRPTR71 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum7 : 7 ; /* [6..0] */ + unsigned int Reserved_535 : 24 ; /* [30..7] */ + unsigned int islastslc7 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR71; + +/* Define the union U_FUNC_VLCST_DSRPTR80 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len8 : 29 ; /* [28..0] */ + unsigned int Reserved_536 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR80; + +/* Define the union U_FUNC_VLCST_DSRPTR81 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum8 : 7 ; /* [6..0] */ + unsigned int Reserved_537 : 24 ; /* [30..7] */ + unsigned int islastslc8 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR81; + +/* Define the union U_FUNC_VLCST_DSRPTR90 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len9 : 29 ; /* [28..0] */ + unsigned int Reserved_538 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR90; + +/* Define the union U_FUNC_VLCST_DSRPTR91 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum9 : 7 ; /* [6..0] */ + unsigned int Reserved_539 : 24 ; /* [30..7] */ + unsigned int islastslc9 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR91; + +/* Define the union U_FUNC_VLCST_DSRPTR100 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len10 : 29 ; /* [28..0] */ + unsigned int Reserved_540 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR100; + +/* Define the union U_FUNC_VLCST_DSRPTR101 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum10 : 7 ; /* [6..0] */ + unsigned int Reserved_541 : 24 ; /* [30..7] */ + unsigned int islastslc10 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR101; + +/* Define the union U_FUNC_VLCST_DSRPTR110 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len11 : 29 ; /* [28..0] */ + unsigned int Reserved_542 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR110; + +/* Define the union U_FUNC_VLCST_DSRPTR111 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum11 : 7 ; /* [6..0] */ + unsigned int Reserved_543 : 24 ; /* [30..7] */ + unsigned int islastslc11 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR111; + +/* Define the union U_FUNC_VLCST_DSRPTR120 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len12 : 29 ; /* [28..0] */ + unsigned int Reserved_544 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR120; + +/* Define the union U_FUNC_VLCST_DSRPTR121 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum12 : 7 ; /* [6..0] */ + unsigned int Reserved_545 : 24 ; /* [30..7] */ + unsigned int islastslc12 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR121; + +/* Define the union U_FUNC_VLCST_DSRPTR130 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len13 : 29 ; /* [28..0] */ + unsigned int Reserved_546 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR130; + +/* Define the union U_FUNC_VLCST_DSRPTR131 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum13 : 7 ; /* [6..0] */ + unsigned int Reserved_547 : 24 ; /* [30..7] */ + unsigned int islastslc13 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR131; + +/* Define the union U_FUNC_VLCST_DSRPTR140 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len14 : 29 ; /* [28..0] */ + unsigned int Reserved_548 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR140; + +/* Define the union U_FUNC_VLCST_DSRPTR141 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum14 : 7 ; /* [6..0] */ + unsigned int Reserved_549 : 24 ; /* [30..7] */ + unsigned int islastslc14 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR141; + +/* Define the union U_FUNC_VLCST_DSRPTR150 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int slc_len15 : 29 ; /* [28..0] */ + unsigned int Reserved_550 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR150; + +/* Define the union U_FUNC_VLCST_DSRPTR151 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int invalidnum15 : 7 ; /* [6..0] */ + unsigned int Reserved_551 : 24 ; /* [30..7] */ + unsigned int islastslc15 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_VLCST_DSRPTR151; + +/* Define the union U_FUNC_SEL_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_555 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTRA_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_556 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTRA_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_normal_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_557 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTRA_PCM_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pcm_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_558 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTRA_PCM_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTER_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int inter_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_559 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTER_FME_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_560 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_FME_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTER_MERGE_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_561 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_MERGE_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_INTER_SKIP_OPT_8X8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_skip_opt_8x8_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_562 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_SKIP_OPT_8X8_CNT; + +/* Define the union U_FUNC_SEL_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_563 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_INTRA_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_564 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTRA_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_OPT_4X4_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int opt_4x4_cnt : 19 ; /* [18..0] */ + unsigned int Reserved_565 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_OPT_4X4_CNT; + +/* Define the union U_FUNC_SEL_INTER_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int inter_opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_567 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_INTER_FME_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_568 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_FME_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_INTER_MERGE_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_569 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_MERGE_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_INTER_SKIP_OPT_16X16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_skip_opt_16x16_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_570 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_SKIP_OPT_16X16_CNT; + +/* Define the union U_FUNC_SEL_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_571 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_INTRA_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intra_opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_572 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTRA_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_INTER_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int inter_opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_574 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_INTER_FME_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_575 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_FME_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_INTER_MERGE_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_576 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_MERGE_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_INTER_SKIP_OPT_32X32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_skip_opt_32x32_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_577 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_SKIP_OPT_32X32_CNT; + +/* Define the union U_FUNC_SEL_OPT_64X64_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int opt_64x64_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_578 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_OPT_64X64_CNT; + +/* Define the union U_FUNC_SEL_INTER_FME_OPT_64X64_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fme_opt_64x64_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_579 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_FME_OPT_64X64_CNT; + +/* Define the union U_FUNC_SEL_INTER_MERGE_OPT_64X64_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_opt_64x64_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_580 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_MERGE_OPT_64X64_CNT; + +/* Define the union U_FUNC_SEL_INTER_SKIP_OPT_64X64_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mrg_skip_opt_64x64_cnt : 16 ; /* [15..0] */ + unsigned int Reserved_581 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_INTER_SKIP_OPT_64X64_CNT; + +/* Define the union U_FUNC_SEL_TOTAL_LUMA_QP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int total_luma_qp : 26 ; /* [25..0] */ + unsigned int Reserved_582 : 6 ; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_TOTAL_LUMA_QP; + +/* Define the union U_FUNC_SEL_MAX_MIN_LUMA_QP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int min_luma_qp : 6 ; /* [5..0] */ + unsigned int Reserved_584 : 2 ; /* [7..6] */ + unsigned int max_luma_qp : 6 ; /* [13..8] */ + unsigned int Reserved_583 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_MAX_MIN_LUMA_QP; + +/* Define the union U_FUNC_SEL_LUMA_QP0_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp0_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_586 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP0_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP1_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp1_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_587 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP1_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP2_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp2_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_588 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP2_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP3_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp3_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_589 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP3_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP4_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp4_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_590 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP4_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP5_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp5_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_591 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP5_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP6_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp6_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_592 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP6_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP7_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp7_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_593 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP7_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP8_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp8_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_594 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP8_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP9_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp9_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_595 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP9_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP10_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp10_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_596 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP10_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP11_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp11_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_597 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP11_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP12_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp12_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_598 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP12_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP13_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp13_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_599 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP13_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP14_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp14_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_600 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP14_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP15_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp15_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_601 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP15_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP16_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp16_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_602 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP16_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP17_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp17_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_603 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP17_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP18_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp18_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_604 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP18_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP19_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp19_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_605 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP19_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP20_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp20_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_606 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP20_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP21_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp21_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_607 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP21_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP22_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp22_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_608 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP22_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP23_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp23_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_609 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP23_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP24_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp24_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_610 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP24_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP25_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp25_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_611 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP25_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP26_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp26_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_612 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP26_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP27_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp27_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_613 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP27_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP28_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp28_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_614 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP28_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP29_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp29_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_615 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP29_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP30_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp30_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_616 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP30_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP31_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp31_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_617 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP31_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP32_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp32_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_618 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP32_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP33_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp33_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_619 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP33_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP34_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp34_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_620 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP34_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP35_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp35_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_621 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP35_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP36_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp36_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_622 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP36_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP37_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp37_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_623 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP37_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP38_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp38_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_624 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP38_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP39_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp39_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_625 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP39_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP40_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp40_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_626 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP40_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP41_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp41_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_627 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP41_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP42_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp42_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_628 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP42_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP43_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp43_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_629 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP43_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP44_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp44_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_630 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP44_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP45_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp45_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_631 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP45_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP46_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp46_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_632 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP46_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP47_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp47_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_633 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP47_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP48_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp48_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_634 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP48_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP49_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp49_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_635 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP49_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP50_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp50_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_636 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP50_CNT; + +/* Define the union U_FUNC_SEL_LUMA_QP51_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int luma_qp51_cnt : 21 ; /* [20..0] */ + unsigned int Reserved_637 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SEL_LUMA_QP51_CNT; + +/* Define the union U_FUNC_SAO_MSE_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sao2vcpi_mse_cnt : 17 ; /* [16..0] */ + unsigned int Reserved_639 : 15 ; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SAO_MSE_CNT; + +/* Define the union U_FUNC_SAO_MSE_MAX */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sao2vcpi_mse_max : 28 ; /* [27..0] */ + unsigned int Reserved_640 : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SAO_MSE_MAX; + +/* Define the union U_FUNC_SAO_OFF_NUM */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int saooff_luma_num : 14 ; /* [13..0] */ + unsigned int Reserved_643 : 2 ; /* [15..14] */ + unsigned int saooff_chroma_num : 14 ; /* [29..16] */ + unsigned int Reserved_642 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SAO_OFF_NUM; + +/* Define the union U_FUNC_SAO_LCU_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int sao_lcu_cnt : 18 ; /* [17..0] */ + unsigned int Reserved_644 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_FUNC_SAO_LCU_CNT; + +/* Define the union U_MMU_PRE_GLB_SCR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int glb_scr : 1 ; /* [0] */ + unsigned int Reserved_647 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_MMU_PRE_GLB_SCR; + +/* Define the union U_MMU_PRE_DFX_ARERR_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arerr_ar_flag : 1 ; /* [0] */ + unsigned int Reserved_650 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_MMU_PRE_DFX_ARERR_FLAG; + +/* Define the union U_MMU_PRE_DFX_ARERR_ID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_ar_id : 5 ; /* [4..0] */ + unsigned int Reserved_651 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_MMU_PRE_DFX_ARERR_ID; + +/* Define the union U_MMU_PRE_DFX_AWERR_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arerr_aw_flag : 1 ; /* [0] */ + unsigned int Reserved_653 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_MMU_PRE_DFX_AWERR_FLAG; + +/* Define the union U_MMU_PRE_DFX_AWERR_ID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_aw_id : 5 ; /* [4..0] */ + unsigned int Reserved_654 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_MMU_PRE_DFX_AWERR_ID; + +/* Define the union U_AXIDFX_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_ar_r_err : 1 ; /* [0] */ + unsigned int dfx_aw_w_err : 1 ; /* [1] */ + unsigned int dfx_aw_b_err : 1 ; /* [2] */ + unsigned int dfx_arid_err : 1 ; /* [3] */ + unsigned int dfx_rid_err : 1 ; /* [4] */ + unsigned int dfx_awid_err : 1 ; /* [5] */ + unsigned int dfx_wid_err : 1 ; /* [6] */ + unsigned int dfx_bid_err : 1 ; /* [7] */ + unsigned int dfx_arid_tx_err : 1 ; /* [8] */ + unsigned int dfx_rid_rx_err : 1 ; /* [9] */ + unsigned int dfx_awid_tx_err : 1 ; /* [10] */ + unsigned int dfx_bid_rx_err : 1 ; /* [11] */ + unsigned int dfx_arid_len_err : 1 ; /* [12] */ + unsigned int dfx_awid_len : 1 ; /* [13] */ + unsigned int dfx_rresp_err : 1 ; /* [14] */ + unsigned int dfx_bresp_err : 1 ; /* [15] */ + unsigned int dfx_ar_ovr_err : 1 ; /* [16] */ + unsigned int dfx_r_ovr_err : 1 ; /* [17] */ + unsigned int dfx_aw_ovr_err : 1 ; /* [18] */ + unsigned int dfx_w_ovr_err : 1 ; /* [19] */ + unsigned int dfx_b_ovr_err : 1 ; /* [20] */ + unsigned int dfx_ar_outstanding_err : 1 ; /* [21] */ + unsigned int dfx_aw_outstanding_err : 1 ; /* [22] */ + unsigned int dfx_arlen_err : 1 ; /* [23] */ + unsigned int dfx_awlen_err : 1 ; /* [24] */ + unsigned int Reserved_656 : 7 ; /* [31..25] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR; + +/* Define the union U_AXIDFX_AR_R_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ar_r_cnt : 7 ; /* [6..0] */ + unsigned int Reserved_658 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AR_R_CNT; + +/* Define the union U_AXIDFX_AW_W_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int aw_w_cnt : 6 ; /* [5..0] */ + unsigned int Reserved_659 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AW_W_CNT; + +/* Define the union U_AXIDFX_AW_B_CNT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int aw_b_cnt : 6 ; /* [5..0] */ + unsigned int Reserved_660 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AW_B_CNT; + +/* Define the union U_AXIDFX_AR_R_ID_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid_err : 1 ; /* [0] */ + unsigned int Reserved_663 : 3 ; /* [3..1] */ + unsigned int dfx_rid_err : 1 ; /* [4] */ + unsigned int Reserved_662 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AR_R_ID_ERR; + +/* Define the union U_AXIDFX_ERR_ARID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_arid : 7 ; /* [6..0] */ + unsigned int Reserved_664 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_ARID; + +/* Define the union U_AXIDFX_ERR_RID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_rid : 7 ; /* [6..0] */ + unsigned int Reserved_665 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_RID; + +/* Define the union U_AXIDFX_AW_W_B_ID_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_awid_err : 1 ; /* [0] */ + unsigned int Reserved_669 : 3 ; /* [3..1] */ + unsigned int dfx_wid_err : 1 ; /* [4] */ + unsigned int Reserved_668 : 3 ; /* [7..5] */ + unsigned int dfx_bid_err : 1 ; /* [8] */ + unsigned int Reserved_667 : 23 ; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AW_W_B_ID_ERR; + +/* Define the union U_AXIDFX_ERR_AWID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_awid : 6 ; /* [5..0] */ + unsigned int Reserved_670 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_AWID; + +/* Define the union U_AXIDFX_ERR_WID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_wid : 6 ; /* [5..0] */ + unsigned int Reserved_671 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_WID; + +/* Define the union U_AXIDFX_ERR_BID */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_bid : 6 ; /* [5..0] */ + unsigned int Reserved_672 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_BID; + +/* Define the union U_AXIDFX_ARID_TX_0ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid0_tx_err : 1 ; /* [0] */ + unsigned int dfx_arid1_tx_err : 1 ; /* [1] */ + unsigned int dfx_arid2_tx_err : 1 ; /* [2] */ + unsigned int dfx_arid3_tx_err : 1 ; /* [3] */ + unsigned int dfx_arid4_tx_err : 1 ; /* [4] */ + unsigned int dfx_arid5_tx_err : 1 ; /* [5] */ + unsigned int dfx_arid6_tx_err : 1 ; /* [6] */ + unsigned int dfx_arid7_tx_err : 1 ; /* [7] */ + unsigned int dfx_arid8_tx_err : 1 ; /* [8] */ + unsigned int dfx_arid9_tx_err : 1 ; /* [9] */ + unsigned int dfx_arid10_tx_err : 1 ; /* [10] */ + unsigned int dfx_arid11_tx_err : 1 ; /* [11] */ + unsigned int dfx_arid12_tx_err : 1 ; /* [12] */ + unsigned int dfx_arid13_tx_err : 1 ; /* [13] */ + unsigned int dfx_arid14_tx_err : 1 ; /* [14] */ + unsigned int dfx_arid15_tx_err : 1 ; /* [15] */ + unsigned int dfx_arid16_tx_err : 1 ; /* [16] */ + unsigned int dfx_arid17_tx_err : 1 ; /* [17] */ + unsigned int dfx_arid18_tx_err : 1 ; /* [18] */ + unsigned int dfx_arid19_tx_err : 1 ; /* [19] */ + unsigned int dfx_arid20_tx_err : 1 ; /* [20] */ + unsigned int dfx_arid21_tx_err : 1 ; /* [21] */ + unsigned int dfx_arid22_tx_err : 1 ; /* [22] */ + unsigned int dfx_arid23_tx_err : 1 ; /* [23] */ + unsigned int dfx_arid24_tx_err : 1 ; /* [24] */ + unsigned int dfx_arid25_tx_err : 1 ; /* [25] */ + unsigned int dfx_arid26_tx_err : 1 ; /* [26] */ + unsigned int dfx_arid27_tx_err : 1 ; /* [27] */ + unsigned int dfx_arid28_tx_err : 1 ; /* [28] */ + unsigned int dfx_arid29_tx_err : 1 ; /* [29] */ + unsigned int dfx_arid30_tx_err : 1 ; /* [30] */ + unsigned int dfx_arid31_tx_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_TX_0ERR; + +/* Define the union U_AXIDFX_ARID_TX_1ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid32_tx_err : 1 ; /* [0] */ + unsigned int dfx_arid33_tx_err : 1 ; /* [1] */ + unsigned int dfx_arid34_tx_err : 1 ; /* [2] */ + unsigned int dfx_arid35_tx_err : 1 ; /* [3] */ + unsigned int dfx_arid36_tx_err : 1 ; /* [4] */ + unsigned int dfx_arid37_tx_err : 1 ; /* [5] */ + unsigned int dfx_arid38_tx_err : 1 ; /* [6] */ + unsigned int dfx_arid39_tx_err : 1 ; /* [7] */ + unsigned int dfx_arid40_tx_err : 1 ; /* [8] */ + unsigned int dfx_arid41_tx_err : 1 ; /* [9] */ + unsigned int dfx_arid42_tx_err : 1 ; /* [10] */ + unsigned int dfx_arid43_tx_err : 1 ; /* [11] */ + unsigned int dfx_arid44_tx_err : 1 ; /* [12] */ + unsigned int dfx_arid45_tx_err : 1 ; /* [13] */ + unsigned int dfx_arid46_tx_err : 1 ; /* [14] */ + unsigned int dfx_arid47_tx_err : 1 ; /* [15] */ + unsigned int dfx_arid48_tx_err : 1 ; /* [16] */ + unsigned int dfx_arid49_tx_err : 1 ; /* [17] */ + unsigned int dfx_arid50_tx_err : 1 ; /* [18] */ + unsigned int dfx_arid51_tx_err : 1 ; /* [19] */ + unsigned int dfx_arid52_tx_err : 1 ; /* [20] */ + unsigned int dfx_arid53_tx_err : 1 ; /* [21] */ + unsigned int dfx_arid54_tx_err : 1 ; /* [22] */ + unsigned int dfx_arid55_tx_err : 1 ; /* [23] */ + unsigned int dfx_arid56_tx_err : 1 ; /* [24] */ + unsigned int dfx_arid57_tx_err : 1 ; /* [25] */ + unsigned int dfx_arid58_tx_err : 1 ; /* [26] */ + unsigned int dfx_arid59_tx_err : 1 ; /* [27] */ + unsigned int dfx_arid60_tx_err : 1 ; /* [28] */ + unsigned int dfx_arid61_tx_err : 1 ; /* [29] */ + unsigned int dfx_arid62_tx_err : 1 ; /* [30] */ + unsigned int dfx_arid63_tx_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_TX_1ERR; + +/* Define the union U_AXIDFX_ARID_TX_2ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid64_tx_err : 1 ; /* [0] */ + unsigned int dfx_arid65_tx_err : 1 ; /* [1] */ + unsigned int dfx_arid66_tx_err : 1 ; /* [2] */ + unsigned int dfx_arid67_tx_err : 1 ; /* [3] */ + unsigned int Reserved_673 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_TX_2ERR; + +/* Define the union U_AXIDFX_RID_RX_0ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_rid0_rx_err : 1 ; /* [0] */ + unsigned int dfx_rid1_rx_err : 1 ; /* [1] */ + unsigned int dfx_rid2_rx_err : 1 ; /* [2] */ + unsigned int dfx_rid3_rx_err : 1 ; /* [3] */ + unsigned int dfx_rid4_rx_err : 1 ; /* [4] */ + unsigned int dfx_rid5_rx_err : 1 ; /* [5] */ + unsigned int dfx_rid6_rx_err : 1 ; /* [6] */ + unsigned int dfx_rid7_rx_err : 1 ; /* [7] */ + unsigned int dfx_rid8_rx_err : 1 ; /* [8] */ + unsigned int dfx_rid9_rx_err : 1 ; /* [9] */ + unsigned int dfx_rid10_rx_err : 1 ; /* [10] */ + unsigned int dfx_rid11_rx_err : 1 ; /* [11] */ + unsigned int dfx_rid12_rx_err : 1 ; /* [12] */ + unsigned int dfx_rid13_rx_err : 1 ; /* [13] */ + unsigned int dfx_rid14_rx_err : 1 ; /* [14] */ + unsigned int dfx_rid15_rx_err : 1 ; /* [15] */ + unsigned int dfx_rid16_rx_err : 1 ; /* [16] */ + unsigned int dfx_rid17_rx_err : 1 ; /* [17] */ + unsigned int dfx_rid18_rx_err : 1 ; /* [18] */ + unsigned int dfx_rid19_rx_err : 1 ; /* [19] */ + unsigned int dfx_rid20_rx_err : 1 ; /* [20] */ + unsigned int dfx_rid21_rx_err : 1 ; /* [21] */ + unsigned int dfx_rid22_rx_err : 1 ; /* [22] */ + unsigned int dfx_rid23_rx_err : 1 ; /* [23] */ + unsigned int dfx_rid24_rx_err : 1 ; /* [24] */ + unsigned int dfx_rid25_rx_err : 1 ; /* [25] */ + unsigned int dfx_rid26_rx_err : 1 ; /* [26] */ + unsigned int dfx_rid27_rx_err : 1 ; /* [27] */ + unsigned int dfx_rid28_rx_err : 1 ; /* [28] */ + unsigned int dfx_rid29_rx_err : 1 ; /* [29] */ + unsigned int dfx_rid30_rx_err : 1 ; /* [30] */ + unsigned int dfx_rid31_rx_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_RID_RX_0ERR; + +/* Define the union U_AXIDFX_RID_RX_1ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_rid32_rx_err : 1 ; /* [0] */ + unsigned int dfx_rid33_rx_err : 1 ; /* [1] */ + unsigned int dfx_rid34_rx_err : 1 ; /* [2] */ + unsigned int dfx_rid35_rx_err : 1 ; /* [3] */ + unsigned int dfx_rid36_rx_err : 1 ; /* [4] */ + unsigned int dfx_rid37_rx_err : 1 ; /* [5] */ + unsigned int dfx_rid38_rx_err : 1 ; /* [6] */ + unsigned int dfx_rid39_rx_err : 1 ; /* [7] */ + unsigned int dfx_rid40_rx_err : 1 ; /* [8] */ + unsigned int dfx_rid41_rx_err : 1 ; /* [9] */ + unsigned int dfx_rid42_rx_err : 1 ; /* [10] */ + unsigned int dfx_rid43_rx_err : 1 ; /* [11] */ + unsigned int dfx_rid44_rx_err : 1 ; /* [12] */ + unsigned int dfx_rid45_rx_err : 1 ; /* [13] */ + unsigned int dfx_rid46_rx_err : 1 ; /* [14] */ + unsigned int dfx_rid47_rx_err : 1 ; /* [15] */ + unsigned int dfx_rid48_rx_err : 1 ; /* [16] */ + unsigned int dfx_rid49_rx_err : 1 ; /* [17] */ + unsigned int dfx_rid50_rx_err : 1 ; /* [18] */ + unsigned int dfx_rid51_rx_err : 1 ; /* [19] */ + unsigned int dfx_rid52_rx_err : 1 ; /* [20] */ + unsigned int dfx_rid53_rx_err : 1 ; /* [21] */ + unsigned int dfx_rid54_rx_err : 1 ; /* [22] */ + unsigned int dfx_rid55_rx_err : 1 ; /* [23] */ + unsigned int dfx_rid56_rx_err : 1 ; /* [24] */ + unsigned int dfx_rid57_rx_err : 1 ; /* [25] */ + unsigned int dfx_rid58_rx_err : 1 ; /* [26] */ + unsigned int dfx_rid59_rx_err : 1 ; /* [27] */ + unsigned int dfx_rid60_rx_err : 1 ; /* [28] */ + unsigned int dfx_rid61_rx_err : 1 ; /* [29] */ + unsigned int dfx_rid62_rx_err : 1 ; /* [30] */ + unsigned int dfx_rid63_rx_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_RID_RX_1ERR; + +/* Define the union U_AXIDFX_RID_RX_2ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_rid64_rx_err : 1 ; /* [0] */ + unsigned int dfx_rid65_rx_err : 1 ; /* [1] */ + unsigned int dfx_rid66_rx_err : 1 ; /* [2] */ + unsigned int dfx_rid67_rx_err : 1 ; /* [3] */ + unsigned int Reserved_675 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_RID_RX_2ERR; + +/* Define the union U_AXIDFX_ARID_RX_0ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_awid0_rx_err : 1 ; /* [0] */ + unsigned int dfx_awid1_rx_err : 1 ; /* [1] */ + unsigned int dfx_awid2_rx_err : 1 ; /* [2] */ + unsigned int dfx_awid3_rx_err : 1 ; /* [3] */ + unsigned int dfx_awid4_rx_err : 1 ; /* [4] */ + unsigned int dfx_awid5_rx_err : 1 ; /* [5] */ + unsigned int dfx_awid6_rx_err : 1 ; /* [6] */ + unsigned int dfx_awid7_rx_err : 1 ; /* [7] */ + unsigned int Reserved_677 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_RX_0ERR; + +/* Define the union U_AXIDFX_BID_RX_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_bid0_rx_err : 1 ; /* [0] */ + unsigned int dfx_bid1_rx_err : 1 ; /* [1] */ + unsigned int dfx_bid2_rx_err : 1 ; /* [2] */ + unsigned int dfx_bid3_rx_err : 1 ; /* [3] */ + unsigned int dfx_bid4_rx_err : 1 ; /* [4] */ + unsigned int dfx_bid5_rx_err : 1 ; /* [5] */ + unsigned int dfx_bid6_rx_err : 1 ; /* [6] */ + unsigned int dfx_bid7_rx_err : 1 ; /* [7] */ + unsigned int Reserved_678 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_BID_RX_ERR; + +/* Define the union U_AXIDFX_ARID_LEN_0ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid0_len_err : 1 ; /* [0] */ + unsigned int dfx_arid1_len_err : 1 ; /* [1] */ + unsigned int dfx_arid2_len_err : 1 ; /* [2] */ + unsigned int dfx_arid3_len_err : 1 ; /* [3] */ + unsigned int dfx_arid4_len_err : 1 ; /* [4] */ + unsigned int dfx_arid5_len_err : 1 ; /* [5] */ + unsigned int dfx_arid6_len_err : 1 ; /* [6] */ + unsigned int dfx_arid7_len_err : 1 ; /* [7] */ + unsigned int dfx_arid8_len_err : 1 ; /* [8] */ + unsigned int dfx_arid9_len_err : 1 ; /* [9] */ + unsigned int dfx_arid10_len_err : 1 ; /* [10] */ + unsigned int dfx_arid11_len_err : 1 ; /* [11] */ + unsigned int dfx_arid12_len_err : 1 ; /* [12] */ + unsigned int dfx_arid13_len_err : 1 ; /* [13] */ + unsigned int dfx_arid14_len_err : 1 ; /* [14] */ + unsigned int dfx_arid15_len_err : 1 ; /* [15] */ + unsigned int dfx_arid16_len_err : 1 ; /* [16] */ + unsigned int dfx_arid17_len_err : 1 ; /* [17] */ + unsigned int dfx_arid18_len_err : 1 ; /* [18] */ + unsigned int dfx_arid19_len_err : 1 ; /* [19] */ + unsigned int dfx_arid20_len_err : 1 ; /* [20] */ + unsigned int dfx_arid21_len_err : 1 ; /* [21] */ + unsigned int dfx_arid22_len_err : 1 ; /* [22] */ + unsigned int dfx_arid23_len_err : 1 ; /* [23] */ + unsigned int dfx_arid24_len_err : 1 ; /* [24] */ + unsigned int dfx_arid25_len_err : 1 ; /* [25] */ + unsigned int dfx_arid26_len_err : 1 ; /* [26] */ + unsigned int dfx_arid27_len_err : 1 ; /* [27] */ + unsigned int dfx_arid28_len_err : 1 ; /* [28] */ + unsigned int dfx_arid29_len_err : 1 ; /* [29] */ + unsigned int dfx_arid30_len_err : 1 ; /* [30] */ + unsigned int dfx_arid31_len_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_LEN_0ERR; + +/* Define the union U_AXIDFX_ARID_LEN_1ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid32_len_err : 1 ; /* [0] */ + unsigned int dfx_arid33_len_err : 1 ; /* [1] */ + unsigned int dfx_arid34_len_err : 1 ; /* [2] */ + unsigned int dfx_arid35_len_err : 1 ; /* [3] */ + unsigned int dfx_arid36_len_err : 1 ; /* [4] */ + unsigned int dfx_arid37_len_err : 1 ; /* [5] */ + unsigned int dfx_arid38_len_err : 1 ; /* [6] */ + unsigned int dfx_arid39_len_err : 1 ; /* [7] */ + unsigned int dfx_arid40_len_err : 1 ; /* [8] */ + unsigned int dfx_arid41_len_err : 1 ; /* [9] */ + unsigned int dfx_arid42_len_err : 1 ; /* [10] */ + unsigned int dfx_arid43_len_err : 1 ; /* [11] */ + unsigned int dfx_arid44_len_err : 1 ; /* [12] */ + unsigned int dfx_arid45_len_err : 1 ; /* [13] */ + unsigned int dfx_arid46_len_err : 1 ; /* [14] */ + unsigned int dfx_arid47_len_err : 1 ; /* [15] */ + unsigned int dfx_arid48_len_err : 1 ; /* [16] */ + unsigned int dfx_arid49_len_err : 1 ; /* [17] */ + unsigned int dfx_arid50_len_err : 1 ; /* [18] */ + unsigned int dfx_arid51_len_err : 1 ; /* [19] */ + unsigned int dfx_arid52_len_err : 1 ; /* [20] */ + unsigned int dfx_arid53_len_err : 1 ; /* [21] */ + unsigned int dfx_arid54_len_err : 1 ; /* [22] */ + unsigned int dfx_arid55_len_err : 1 ; /* [23] */ + unsigned int dfx_arid56_len_err : 1 ; /* [24] */ + unsigned int dfx_arid57_len_err : 1 ; /* [25] */ + unsigned int dfx_arid58_len_err : 1 ; /* [26] */ + unsigned int dfx_arid59_len_err : 1 ; /* [27] */ + unsigned int dfx_arid60_len_err : 1 ; /* [28] */ + unsigned int dfx_arid61_len_err : 1 ; /* [29] */ + unsigned int dfx_arid62_len_err : 1 ; /* [30] */ + unsigned int dfx_arid63_len_err : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_LEN_1ERR; + +/* Define the union U_AXIDFX_ARID_LEN_2ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arid64_len_err : 1 ; /* [0] */ + unsigned int dfx_arid65_len_err : 1 ; /* [1] */ + unsigned int dfx_arid66_len_err : 1 ; /* [2] */ + unsigned int dfx_arid67_len_err : 1 ; /* [3] */ + unsigned int Reserved_680 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ARID_LEN_2ERR; + +/* Define the union U_AXIDFX_RESP_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_rresp_err : 1 ; /* [0] */ + unsigned int Reserved_684 : 3 ; /* [3..1] */ + unsigned int dfx_bresp_err : 1 ; /* [4] */ + unsigned int Reserved_683 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_RESP_ERR; + +/* Define the union U_AXIDFX_ERR_RESP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_rresp : 2 ; /* [1..0] */ + unsigned int dfx_err_bresp : 2 ; /* [3..2] */ + unsigned int Reserved_685 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_RESP; + +/* Define the union U_AXIDFX_LEN_ERR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_arlen_err : 1 ; /* [0] */ + unsigned int Reserved_687 : 3 ; /* [3..1] */ + unsigned int dfx_awlen_err : 1 ; /* [4] */ + unsigned int Reserved_686 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_LEN_ERR; + +/* Define the union U_AXIDFX_ERR_LEN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_err_arlen : 4 ; /* [3..0] */ + unsigned int dfx_err_awlen : 4 ; /* [7..4] */ + unsigned int Reserved_688 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_ERR_LEN; + +/* Define the union U_AXIDFX_2RID_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_2rid_flag : 4 ; /* [3..0] */ + unsigned int Reserved_689 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_2RID_FLAG; + +/* Define the union U_AXIDFX_WID_FLAG */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dfx_wid_flag : 8 ; /* [7..0] */ + unsigned int Reserved_690 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_WID_FLAG; + +/* Define the union U_AXIDFX_AXI_ST */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int arvalid : 1 ; /* [0] */ + unsigned int arready : 1 ; /* [1] */ + unsigned int rvalid : 1 ; /* [2] */ + unsigned int rready : 1 ; /* [3] */ + unsigned int awvalid : 1 ; /* [4] */ + unsigned int awready : 1 ; /* [5] */ + unsigned int wvalid : 1 ; /* [6] */ + unsigned int wready : 1 ; /* [7] */ + unsigned int bvalid : 1 ; /* [8] */ + unsigned int bready : 1 ; /* [9] */ + unsigned int Reserved_691 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_AXI_ST; + +/* Define the union U_AXIDFX_SOFT_RST_REQ */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int axi_soft_rst_req : 1 ; /* [0] */ + unsigned int Reserved_693 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_SOFT_RST_REQ; + +/* Define the union U_AXIDFX_SOFT_RST_ACK */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int axi_soft_rst_ack : 1 ; /* [0] */ + unsigned int Reserved_694 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_SOFT_RST_ACK; + +/* Define the union U_AXIDFX_SOFT_RST_FORCE_REQ_ACK */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int axi_soft_rst_force_req_ack : 1 ; /* [0] */ + unsigned int Reserved_696 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_AXIDFX_SOFT_RST_FORCE_REQ_ACK; + +/* Define the union U_SMMU_MSTR_GLB_BYPASS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int glb_bypass : 1 ; /* [0] */ + unsigned int Reserved_698 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_GLB_BYPASS; + +/* Define the union U_SMMU_MSTR_DEBUG_MODE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int debug_mode : 1 ; /* [0] */ + unsigned int axilock_en : 1 ; /* [1] */ + unsigned int Reserved_699 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_DEBUG_MODE; + +/* Define the union U_SMMU_MSTR_MEM_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mem_ctrl_s : 16 ; /* [15..0] */ + unsigned int mem_ctrl_d1w2r : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_MEM_CTRL; + +/* Define the union U_SMMU_MSTR_CLK_EN */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int apb_clk_en : 2 ; /* [1..0] */ + unsigned int core_clk_en : 2 ; /* [3..2] */ + unsigned int Reserved_700 : 28 ; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_CLK_EN; + +/* Define the union U_SMMU_MSTR_END_REQ_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int end_req_2 : 24 ; /* [23..0] */ + unsigned int Reserved_701 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_END_REQ_2; + +/* Define the union U_SMMU_MSTR_END_ACK_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int end_ack_2 : 24 ; /* [23..0] */ + unsigned int Reserved_702 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_END_ACK_2; + +/* Define the union U_SMMU_MSTR_SMRX_START_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int stream_start_2 : 24 ; /* [23..0] */ + unsigned int Reserved_703 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_SMRX_START_2; + +/* Define the union U_SMMU_MSTR_INPT_SEL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_start_sel : 1 ; /* [0] */ + unsigned int end_req_sel : 1 ; /* [1] */ + unsigned int Reserved_704 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_INPT_SEL; + +/* Define the union U_SMMU_MSTR_INTMASK */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_va_err0_msk : 1 ; /* [0] */ + unsigned int rd_va_err1_msk : 1 ; /* [1] */ + unsigned int wr_va_err0_msk : 1 ; /* [2] */ + unsigned int wr_va_err1_msk : 1 ; /* [3] */ + unsigned int wdata_burst_msk : 1 ; /* [4] */ + unsigned int Reserved_706 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_INTMASK; + +/* Define the union U_SMMU_MSTR_INTRAW */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_va_err0_raw : 1 ; /* [0] */ + unsigned int rd_va_err1_raw : 1 ; /* [1] */ + unsigned int wr_va_err0_raw : 1 ; /* [2] */ + unsigned int wr_va_err1_raw : 1 ; /* [3] */ + unsigned int wdata_burst_raw : 1 ; /* [4] */ + unsigned int Reserved_707 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_INTRAW; + +/* Define the union U_SMMU_MSTR_INTSTAT */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_va_err0_stat : 1 ; /* [0] */ + unsigned int rd_va_err1_stat : 1 ; /* [1] */ + unsigned int wr_va_err0_stat : 1 ; /* [2] */ + unsigned int wr_va_err1_stat : 1 ; /* [3] */ + unsigned int wdata_burst_stat : 1 ; /* [4] */ + unsigned int Reserved_708 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_INTSTAT; + +/* Define the union U_SMMU_MSTR_INTCLR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_va_err0_clr : 1 ; /* [0] */ + unsigned int rd_va_err1_clr : 1 ; /* [1] */ + unsigned int wr_va_err0_clr : 1 ; /* [2] */ + unsigned int wr_va_err1_clr : 1 ; /* [3] */ + unsigned int wdata_burst_clr : 1 ; /* [4] */ + unsigned int Reserved_709 : 27 ; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_INTCLR; + +/* Define the union U_SMMU_MSTR_DBG_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_sid : 8 ; /* [7..0] */ + unsigned int Reserved_710 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_DBG_0; + +/* Define the union U_SMMU_MSTR_DBG_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int wr_sid : 8 ; /* [7..0] */ + unsigned int Reserved_711 : 24 ; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_DBG_2; + +/* Define the union U_SMMU_MSTR_DBG_4 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int awid : 8 ; /* [7..0] */ + unsigned int awlen : 8 ; /* [15..8] */ + unsigned int wid : 8 ; /* [23..16] */ + unsigned int wdata_len : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_DBG_4; + +/* Define the union U_SMMU_MSTR_DBG_PORT_IN_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_cfg_addr : 16 ; /* [15..0] */ + unsigned int dbg_cfg_cs : 1 ; /* [16] */ + unsigned int dbg_cfg_wr : 1 ; /* [17] */ + unsigned int Reserved_713 : 14 ; /* [31..18] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_DBG_PORT_IN_0; + +/* Define the union U_SMMU_MSTR_SMRX_0 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int bypass : 1 ; /* [0] */ + unsigned int Reserved_716 : 3 ; /* [3..1] */ + unsigned int upwin : 8 ; /* [11..4] */ + unsigned int len : 8 ; /* [19..12] */ + unsigned int Reserved_715 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_SMRX_0; + +/* Define the union U_SMMU_MSTR_SMRX_1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_717 : 15 ; /* [14..0] */ + unsigned int va_str : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_SMRX_1; + +/* Define the union U_SMMU_MSTR_SMRX_2 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_718 : 15 ; /* [14..0] */ + unsigned int va_end : 17 ; /* [31..15] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MSTR_SMRX_2; + +/* Define the union U_RD_CMD_TRANS_LATENCY */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int rd_cmd_max_latency : 16 ; /* [15..0] */ + unsigned int rd_cmd_avg_latency : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_RD_CMD_TRANS_LATENCY; + +/* Define the union U_WR_CMD_TRANS_LATENCY */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int wr_cmd_max_latency : 16 ; /* [15..0] */ + unsigned int wr_cmd_avg_latency : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_WR_CMD_TRANS_LATENCY; + +/* Define the union U_SMMU_SCR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int glb_bypass : 1 ; /* [0] */ + unsigned int rqos_en : 1 ; /* [1] */ + unsigned int wqos_en : 1 ; /* [2] */ + unsigned int Reserved_723 : 1 ; /* [3] */ + unsigned int cache_l1_en : 1 ; /* [4] */ + unsigned int cache_l2_en : 1 ; /* [5] */ + unsigned int rqos : 4 ; /* [9..6] */ + unsigned int wqos : 4 ; /* [13..10] */ + unsigned int Reserved_722 : 1 ; /* [14] */ + unsigned int smr_rd_shadow : 1 ; /* [15] */ + unsigned int ptw_pf : 4 ; /* [19..16] */ + unsigned int Reserved_721 : 12 ; /* [31..20] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCR; + +/* Define the union U_SMMU_MEMCTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int mem_ctrl_wr : 16 ; /* [15..0] */ + unsigned int mem_ctrl_rd : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_MEMCTRL; + +/* Define the union U_SMMU_LP_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int auto_clk_gt_en : 2 ; /* [1..0] */ + unsigned int Reserved_724 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_LP_CTRL; + +/* Define the union U_SMMU_PRESS_REMAP */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int remap_sel0 : 2 ; /* [1..0] */ + unsigned int remap_sel1 : 2 ; /* [3..2] */ + unsigned int remap_sel2 : 2 ; /* [5..4] */ + unsigned int remap_sel3 : 2 ; /* [7..6] */ + unsigned int remap_sel4 : 2 ; /* [9..8] */ + unsigned int remap_sel5 : 2 ; /* [11..10] */ + unsigned int remap_sel6 : 2 ; /* [13..12] */ + unsigned int remap_sel7 : 2 ; /* [15..14] */ + unsigned int remap_sel8 : 2 ; /* [17..16] */ + unsigned int remap_sel9 : 2 ; /* [19..18] */ + unsigned int remap_sel10 : 2 ; /* [21..20] */ + unsigned int remap_sel11 : 2 ; /* [23..22] */ + unsigned int remap_sel12 : 2 ; /* [25..24] */ + unsigned int remap_sel13 : 2 ; /* [27..26] */ + unsigned int remap_sel14 : 2 ; /* [29..28] */ + unsigned int remap_sel15 : 2 ; /* [31..30] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_PRESS_REMAP; + +/* Define the union U_SMMU_INTMASK_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intns_permis_msk : 1 ; /* [0] */ + unsigned int intns_ext_msk : 1 ; /* [1] */ + unsigned int intns_tlbmiss_msk : 1 ; /* [2] */ + unsigned int intns_ptw_trans_msk : 1 ; /* [3] */ + unsigned int intns_ptw_invalid_msk : 1 ; /* [4] */ + unsigned int intns_ptw_ns_msk : 1 ; /* [5] */ + unsigned int Reserved_725 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTMASK_NS; + +/* Define the union U_SMMU_INTRAW_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intns_permis_raw : 1 ; /* [0] */ + unsigned int intns_ext_raw : 1 ; /* [1] */ + unsigned int intns_tlbmiss_raw : 1 ; /* [2] */ + unsigned int intns_ptw_trans_raw : 1 ; /* [3] */ + unsigned int intns_ptw_invalid_raw : 1 ; /* [4] */ + unsigned int intns_ptw_ns_raw : 1 ; /* [5] */ + unsigned int Reserved_726 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTRAW_NS; + +/* Define the union U_SMMU_INTSTAT_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intns_permis_stat : 1 ; /* [0] */ + unsigned int intns_ext_stat : 1 ; /* [1] */ + unsigned int intns_tlbmiss_stat : 1 ; /* [2] */ + unsigned int intns_ptw_trans_stat : 1 ; /* [3] */ + unsigned int intns_ptw_invalid_stat : 1 ; /* [4] */ + unsigned int intns_ptw_ns_stat : 1 ; /* [5] */ + unsigned int Reserved_727 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTSTAT_NS; + +/* Define the union U_SMMU_INTCLR_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intns_permis_clr : 1 ; /* [0] */ + unsigned int intns_ext_clr : 1 ; /* [1] */ + unsigned int intns_tlbmiss_clr : 1 ; /* [2] */ + unsigned int intns_ptw_trans_clr : 1 ; /* [3] */ + unsigned int intns_ptw_invalid_clr : 1 ; /* [4] */ + unsigned int intns_ptw_ns_clr : 1 ; /* [5] */ + unsigned int Reserved_728 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTCLR_NS; + +/* Define the union U_SMMU_SMRX_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_bypass : 1 ; /* [0] */ + unsigned int Reserved_730 : 1 ; /* [1] */ + unsigned int smr_ptw_qos : 2 ; /* [3..2] */ + unsigned int smr_invld_en : 1 ; /* [4] */ + unsigned int Reserved_729 : 7 ; /* [11..5] */ + unsigned int smr_offset_addr : 20 ; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SMRX_NS; + +/* Define the union U_SMMU_RLD_EN2_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_rld_en2 : 24 ; /* [23..0] */ + unsigned int Reserved_731 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_RLD_EN2_NS; + +/* Define the union U_SMMU_CB_SCTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cb_bypass : 1 ; /* [0] */ + unsigned int Reserved_732 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_CB_SCTRL; + +/* Define the union U_SMMU_CB_TTBCR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cb_ttbcr_des : 1 ; /* [0] */ + unsigned int cb_ttbcr_t0sz : 3 ; /* [3..1] */ + unsigned int cb_ttbcr_n : 3 ; /* [6..4] */ + unsigned int Reserved_734 : 9 ; /* [15..7] */ + unsigned int cb_ttbcr_t1sz : 3 ; /* [18..16] */ + unsigned int Reserved_733 : 13 ; /* [31..19] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_CB_TTBCR; + +/* Define the union U_SMMU_OFFSET_ADDR_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int offset_addr_ns : 14 ; /* [13..0] */ + unsigned int Reserved_735 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OFFSET_ADDR_NS; + +/* Define the union U_SMMU_SCACHEI_ALL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cache_all_invalid : 1 ; /* [0] */ + unsigned int cache_all_level : 2 ; /* [2..1] */ + unsigned int Reserved_736 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCACHEI_ALL; + +/* Define the union U_SMMU_SCACHEI_L1 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cache_l1_invalid : 1 ; /* [0] */ + unsigned int cache_l1_security : 2 ; /* [2..1] */ + unsigned int Reserved_737 : 29 ; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCACHEI_L1; + +/* Define the union U_SMMU_SCACHEI_L2L3 */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int cache_l2l3_invalid : 1 ; /* [0] */ + unsigned int cache_l2l3_strmid : 15 ; /* [15..1] */ + unsigned int Reserved_738 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCACHEI_L2L3; + +/* Define the union U_SMMU_FAMA_CTRL0_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_sdes_msb_ns : 7 ; /* [6..0] */ + unsigned int fama_chn_sel_ns : 1 ; /* [7] */ + unsigned int fama_bps_msb_ns : 6 ; /* [13..8] */ + unsigned int Reserved_739 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL0_NS; + +/* Define the union U_SMMU_FAMA_CTRL1_NS */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_ptw_msb_ns : 7 ; /* [6..0] */ + unsigned int Reserved_740 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL1_NS; + +/* Define the union U_SMMU_ADDR_MSB */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int msb_errrd : 7 ; /* [6..0] */ + unsigned int msb_errwr : 7 ; /* [13..7] */ + unsigned int msb_ova : 7 ; /* [20..14] */ + unsigned int Reserved_741 : 11 ; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_ADDR_MSB; + +/* Define the union U_SMMU_FAULT_ID_TCU */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fault_index_id_tcu : 16 ; /* [15..0] */ + unsigned int fault_strm_id_tcu : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAULT_ID_TCU; + +/* Define the union U_SMMU_FAULT_ID_TBUX */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fault_index_id_tbu : 16 ; /* [15..0] */ + unsigned int fault_strm_id_tbu : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAULT_ID_TBUX; + +/* Define the union U_SMMU_FAULT_INFOX */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fault_tlbmiss_err_tbu : 2 ; /* [1..0] */ + unsigned int fault_permis_err_tbu : 3 ; /* [4..2] */ + unsigned int fautl_ext_err_tbu : 2 ; /* [6..5] */ + unsigned int fault_ext_err_id_tbu : 9 ; /* [15..7] */ + unsigned int Reserved_742 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAULT_INFOX; + +/* Define the union U_SMMU_DBGRPTR_TLB */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_tlbword_pointer : 3 ; /* [2..0] */ + unsigned int dbg_tlbentry_pointer : 13 ; /* [15..3] */ + unsigned int Reserved_744 : 14 ; /* [29..16] */ + unsigned int dbg_tlb_type : 1 ; /* [30] */ + unsigned int Reserved_743 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRPTR_TLB; + +/* Define the union U_SMMU_DBGRDATA_TLB */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_tlb_rdata : 31 ; /* [30..0] */ + unsigned int Reserved_745 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRDATA_TLB; + +/* Define the union U_SMMU_DBGRPTR_CACHE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_cache_level : 2 ; /* [1..0] */ + unsigned int dbg_cache_l1_pointer : 2 ; /* [3..2] */ + unsigned int dbg_cache_l1_ns : 1 ; /* [4] */ + unsigned int dbg_cache_l2_strmid : 11 ; /* [15..5] */ + unsigned int Reserved_746 : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRPTR_CACHE; + +/* Define the union U_SMMU_DBGRDATA0_CACHE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_cache_rdata0 : 29 ; /* [28..0] */ + unsigned int Reserved_747 : 3 ; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRDATA0_CACHE; + +/* Define the union U_SMMU_DBGRDATA1_CACHE */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_cache_rdata1 : 12 ; /* [11..0] */ + unsigned int Reserved_748 : 20 ; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRDATA1_CACHE; + +/* Define the union U_SMMU_DBGAXI_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_axilock_en : 1 ; /* [0] */ + unsigned int Reserved_749 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGAXI_CTRL; + +/* Define the union U_SMMU_OPA_ADDR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int override_acquire_pa : 27 ; /* [26..0] */ + unsigned int Reserved_750 : 4 ; /* [30..27] */ + unsigned int override_pa_done : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OPA_ADDR; + +/* Define the union U_SMMU_OVA_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int override_va_cfg : 1 ; /* [0] */ + unsigned int Reserved_751 : 1 ; /* [1] */ + unsigned int override_va_type : 1 ; /* [2] */ + unsigned int override_va_indexid : 13 ; /* [15..3] */ + unsigned int override_va_strmid : 12 ; /* [27..16] */ + unsigned int override_tbu_num : 4 ; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OVA_CTRL; + +/* Define the union U_SMMU_OPREF_CTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int override_pref_cfg : 1 ; /* [0] */ + unsigned int Reserved_752 : 1 ; /* [1] */ + unsigned int override_pref_type : 1 ; /* [2] */ + unsigned int override_pref_initial : 1 ; /* [3] */ + unsigned int override_pref_indexid : 12 ; /* [15..4] */ + unsigned int override_pref_strmid : 16 ; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OPREF_CTRL; + +/* Define the union U_SMMU_SMRX_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_nscfg : 1 ; /* [0] */ + unsigned int smr_nscfg_en : 1 ; /* [1] */ + unsigned int smr_bypass_s : 1 ; /* [2] */ + unsigned int Reserved_753 : 2 ; /* [4..3] */ + unsigned int smr_mid_en_s : 1 ; /* [5] */ + unsigned int smr_mid_s : 6 ; /* [11..6] */ + unsigned int smr_offset_addr_s : 20 ; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SMRX_S; + +/* Define the union U_SMMU_RLD_EN2_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_rld_en2_s : 24 ; /* [23..0] */ + unsigned int Reserved_754 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_RLD_EN2_S; + +/* Define the union U_SMMU_INTMAS_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ints_permis_msk : 1 ; /* [0] */ + unsigned int ints_ext_msk : 1 ; /* [1] */ + unsigned int ints_tlbmiss_msk : 1 ; /* [2] */ + unsigned int ints_ptw_trans_msk : 1 ; /* [3] */ + unsigned int ints_ptw_invalid_msk : 1 ; /* [4] */ + unsigned int ints_ptw_ns_msk : 1 ; /* [5] */ + unsigned int Reserved_755 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTMAS_S; + +/* Define the union U_SMMU_INTRAW_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ints_permis_raw : 1 ; /* [0] */ + unsigned int ints_ext_raw : 1 ; /* [1] */ + unsigned int ints_tlbmiss_raw : 1 ; /* [2] */ + unsigned int ints_ptw_trans_raw : 1 ; /* [3] */ + unsigned int ints_ptw_invalid_raw : 1 ; /* [4] */ + unsigned int ints_ptw_ns_raw : 1 ; /* [5] */ + unsigned int Reserved_756 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTRAW_S; + +/* Define the union U_SMMU_INTSTAT_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ints_permis_stat : 1 ; /* [0] */ + unsigned int ints_ext_stat : 1 ; /* [1] */ + unsigned int ints_tlbmiss_stat : 1 ; /* [2] */ + unsigned int ints_ptw_trans_stat : 1 ; /* [3] */ + unsigned int ints_ptw_invalid_stat : 1 ; /* [4] */ + unsigned int ints_ptw_ns_stat : 1 ; /* [5] */ + unsigned int Reserved_757 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTSTAT_S; + +/* Define the union U_SMMU_INTCLR_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int ints_permis_clr : 1 ; /* [0] */ + unsigned int ints_ext_clr : 1 ; /* [1] */ + unsigned int ints_tlbmiss_clr : 1 ; /* [2] */ + unsigned int ints_ptw_trans_clr : 1 ; /* [3] */ + unsigned int ints_ptw_invalid_clr : 1 ; /* [4] */ + unsigned int ints_ptw_ns_clr : 1 ; /* [5] */ + unsigned int Reserved_758 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTCLR_S; + +/* Define the union U_SMMU_SCR_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int glb_nscfg : 2 ; /* [1..0] */ + unsigned int mid_s : 6 ; /* [7..2] */ + unsigned int glb_bypass_s : 1 ; /* [8] */ + unsigned int mid_en_s : 1 ; /* [9] */ + unsigned int Reserved_759 : 22 ; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCR_S; + +/* Define the union U_SMMU_SCB_SCTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int scb_bypass : 1 ; /* [0] */ + unsigned int Reserved_760 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCB_SCTRL; + +/* Define the union U_SMMU_SCB_TTBCR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int scb_ttbcr_des : 1 ; /* [0] */ + unsigned int Reserved_761 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCB_TTBCR; + +/* Define the union U_SMMU_OFFSET_ADDR_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int offset_addr_s : 14 ; /* [13..0] */ + unsigned int Reserved_762 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OFFSET_ADDR_S; + +/* Define the union U_SMMU_FAMA_CTRL0_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_sdes_msb_s : 7 ; /* [6..0] */ + unsigned int fama_chn_sel_s : 1 ; /* [7] */ + unsigned int fama_bps_msb_s : 6 ; /* [13..8] */ + unsigned int Reserved_763 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL0_S; + +/* Define the union U_SMMU_FAMA_CTRL1_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_ptw_msb_s : 7 ; /* [6..0] */ + unsigned int Reserved_764 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL1_S; + +/* Define the union U_SMMU_DBGRPTR_TLB_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_tlb_en : 1 ; /* [0] */ + unsigned int Reserved_765 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRPTR_TLB_S; + +/* Define the union U_SMMU_DBGRPTR_CACHE_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int dbg_cache_en : 1 ; /* [0] */ + unsigned int Reserved_766 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_DBGRPTR_CACHE_S; + +/* Define the union U_SMMU_OVERRIDE_CTRL_S */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int Reserved_768 : 1 ; /* [0] */ + unsigned int override_va_security : 1 ; /* [1] */ + unsigned int Reserved_767 : 30 ; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OVERRIDE_CTRL_S; + +/* Define the union U_SMMU_SMRX_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_protect_en : 1 ; /* [0] */ + unsigned int Reserved_770 : 1 ; /* [1] */ + unsigned int smr_bypass_p : 1 ; /* [2] */ + unsigned int Reserved_769 : 9 ; /* [11..3] */ + unsigned int smr_offset_addr_p : 20 ; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SMRX_P; + +/* Define the union U_SMMU_RLD_EN2_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int smr_rld_en2_p : 24 ; /* [23..0] */ + unsigned int Reserved_771 : 8 ; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_RLD_EN2_P; + +/* Define the union U_SMMU_INTMAS_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intp_permis_msk : 1 ; /* [0] */ + unsigned int intp_ext_msk : 1 ; /* [1] */ + unsigned int intp_tlbmiss_msk : 1 ; /* [2] */ + unsigned int intp_ptw_trans_msk : 1 ; /* [3] */ + unsigned int intp_ptw_invalid_msk : 1 ; /* [4] */ + unsigned int intp_ptw_ns_msk : 1 ; /* [5] */ + unsigned int Reserved_772 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTMAS_P; + +/* Define the union U_SMMU_INTRAW_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intp_permis_raw : 1 ; /* [0] */ + unsigned int intp_ext_raw : 1 ; /* [1] */ + unsigned int intp_tlbmiss_raw : 1 ; /* [2] */ + unsigned int intp_ptw_trans_raw : 1 ; /* [3] */ + unsigned int intp_ptw_invalid_raw : 1 ; /* [4] */ + unsigned int intp_ptw_ns_raw : 1 ; /* [5] */ + unsigned int Reserved_773 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTRAW_P; + +/* Define the union U_SMMU_INTSTAT_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intp_permis_stat : 1 ; /* [0] */ + unsigned int intp_ext_stat : 1 ; /* [1] */ + unsigned int intp_tlbmiss_stat : 1 ; /* [2] */ + unsigned int intp_ptw_trans_stat : 1 ; /* [3] */ + unsigned int intp_ptw_invalid_stat : 1 ; /* [4] */ + unsigned int intp_ptw_ns_stat : 1 ; /* [5] */ + unsigned int Reserved_774 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTSTAT_P; + +/* Define the union U_SMMU_INTCLR_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int intp_permis_clr : 1 ; /* [0] */ + unsigned int intp_ext_clr : 1 ; /* [1] */ + unsigned int intp_tlbmiss_clr : 1 ; /* [2] */ + unsigned int intp_ptw_trans_clr : 1 ; /* [3] */ + unsigned int intp_ptw_invalid_clr : 1 ; /* [4] */ + unsigned int intp_ptw_ns_clr : 1 ; /* [5] */ + unsigned int Reserved_775 : 26 ; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_INTCLR_P; + +/* Define the union U_SMMU_SCR_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int glb_prot_cfg : 1 ; /* [0] */ + unsigned int Reserved_777 : 7 ; /* [7..1] */ + unsigned int glb_bypass_p : 1 ; /* [8] */ + unsigned int Reserved_776 : 23 ; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_SCR_P; + +/* Define the union U_SMMU_PCB_SCTRL */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pcb_bypass : 1 ; /* [0] */ + unsigned int Reserved_778 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_PCB_SCTRL; + +/* Define the union U_SMMU_PCB_TTBCR */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int pcb_ttbcr_des : 1 ; /* [0] */ + unsigned int Reserved_779 : 31 ; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_PCB_TTBCR; + +/* Define the union U_SMMU_OFFSET_ADDR_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int offset_addr_p : 14 ; /* [13..0] */ + unsigned int Reserved_780 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_OFFSET_ADDR_P; + +/* Define the union U_SMMU_FAMA_CTRL0_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_sdes_msb_p : 7 ; /* [6..0] */ + unsigned int fama_chn_sel_p : 1 ; /* [7] */ + unsigned int fama_bps_msb_p : 6 ; /* [13..8] */ + unsigned int Reserved_781 : 18 ; /* [31..14] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL0_P; + +/* Define the union U_SMMU_FAMA_CTRL1_P */ +typedef union +{ + /* Define the struct bits */ + struct + { + unsigned int fama_ptw_msb_p : 7 ; /* [6..0] */ + unsigned int Reserved_782 : 25 ; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} U_SMMU_FAMA_CTRL1_P; + +//============================================================================== +/* Define the global struct */ +typedef struct +{ + volatile U_VEDU_VCPI_INTMASK VEDU_VCPI_INTMASK; + volatile U_VEDU_VCPI_INTCLR VEDU_VCPI_INTCLR; + volatile U_VEDU_VCPI_START VEDU_VCPI_START; + volatile U_VEDU_VCPI_CNTCLR VEDU_VCPI_CNTCLR; + volatile unsigned int VEDU_VCPI_FRAMENO; + volatile U_VEDU_VCPI_BP_POS VEDU_VCPI_BP_POS; + volatile unsigned int VEDU_VCPI_TIMEOUT; + volatile U_VEDU_VCPI_MODE VEDU_VCPI_MODE; + volatile U_VEDU_VCPI_TILE_SIZE VEDU_VCPI_TILE_SIZE; + volatile U_VEDU_VCPI_PICSIZE_PIX VEDU_VCPI_PICSIZE_PIX; + volatile U_VEDU_VCPI_MULTISLC VEDU_VCPI_MULTISLC; + volatile U_VEDU_VCPI_QPCFG VEDU_VCPI_QPCFG; + volatile U_VEDU_VCPI_DBLKCFG VEDU_VCPI_DBLKCFG; + volatile U_VEDU_VCPI_LOW_POWER VEDU_VCPI_LOW_POWER; + volatile U_VEDU_VCPI_OUTSTD VEDU_VCPI_OUTSTD; + volatile U_VEDU_VCPI_TMV_LOAD VEDU_VCPI_TMV_LOAD; + volatile U_VEDU_VCPI_CROSS_TILE_SLC VEDU_VCPI_CROSS_TILE_SLC; + volatile U_VEDU_VCPI_MEM_CTRL VEDU_VCPI_MEM_CTRL; + volatile U_VEDU_VCPI_INTRA_INTER_CU_EN VEDU_VCPI_INTRA_INTER_CU_EN; + volatile U_VEDU_VCPI_VLC_CONFIG VEDU_VCPI_VLC_CONFIG; + volatile U_VEDU_VCPI_PRE_JUDGE_EXT_EN VEDU_VCPI_PRE_JUDGE_EXT_EN; + volatile U_VEDU_VCPI_PRE_JUDGE_COST_THR VEDU_VCPI_PRE_JUDGE_COST_THR; + volatile U_VEDU_VCPI_IBLK_PRE_MV_THR VEDU_VCPI_IBLK_PRE_MV_THR; + volatile U_VEDU_VCPI_PME_PARAM VEDU_VCPI_PME_PARAM; + volatile U_VEDU_VCPI_PIC_STRONG_EN VEDU_VCPI_PIC_STRONG_EN; + volatile U_VEDU_VCPI_REF_FLAG VEDU_VCPI_REF_FLAG; + volatile U_VEDU_VCPI_RC_ENABLE VEDU_VCPI_RC_ENABLE; + volatile U_VEDU_VCPI_PINTRA_THRESH0 VEDU_VCPI_PINTRA_THRESH0; + volatile U_VEDU_VCPI_PINTRA_THRESH1 VEDU_VCPI_PINTRA_THRESH1; + volatile U_VEDU_VCPI_PINTRA_THRESH2 VEDU_VCPI_PINTRA_THRESH2; + volatile U_VEDU_VCPI_I_SLC_INSERT VEDU_VCPI_I_SLC_INSERT; + volatile U_VEDU_VCPI_CLKDIV_ENABLE VEDU_VCPI_CLKDIV_ENABLE; + volatile U_VEDU_VCPI_OSD_ENABLE VEDU_VCPI_OSD_ENABLE; + volatile U_VEDU_VCPI_OSD_POS_0 VEDU_VCPI_OSD_POS_0; + volatile U_VEDU_VCPI_OSD_POS_1 VEDU_VCPI_OSD_POS_1; + volatile U_VEDU_VCPI_OSD_POS_2 VEDU_VCPI_OSD_POS_2; + volatile U_VEDU_VCPI_OSD_POS_3 VEDU_VCPI_OSD_POS_3; + volatile U_VEDU_VCPI_OSD_POS_4 VEDU_VCPI_OSD_POS_4; + volatile U_VEDU_VCPI_OSD_POS_5 VEDU_VCPI_OSD_POS_5; + volatile U_VEDU_VCPI_OSD_POS_6 VEDU_VCPI_OSD_POS_6; + volatile U_VEDU_VCPI_OSD_POS_7 VEDU_VCPI_OSD_POS_7; + volatile U_VEDU_VCPI_OSD_SIZE_0 VEDU_VCPI_OSD_SIZE_0; + volatile U_VEDU_VCPI_OSD_SIZE_1 VEDU_VCPI_OSD_SIZE_1; + volatile U_VEDU_VCPI_OSD_SIZE_2 VEDU_VCPI_OSD_SIZE_2; + volatile U_VEDU_VCPI_OSD_SIZE_3 VEDU_VCPI_OSD_SIZE_3; + volatile U_VEDU_VCPI_OSD_SIZE_4 VEDU_VCPI_OSD_SIZE_4; + volatile U_VEDU_VCPI_OSD_SIZE_5 VEDU_VCPI_OSD_SIZE_5; + volatile U_VEDU_VCPI_OSD_SIZE_6 VEDU_VCPI_OSD_SIZE_6; + volatile U_VEDU_VCPI_OSD_SIZE_7 VEDU_VCPI_OSD_SIZE_7; + volatile U_VEDU_VCPI_OSD_LAYERID VEDU_VCPI_OSD_LAYERID; + volatile U_VEDU_VCPI_OSD_QP0 VEDU_VCPI_OSD_QP0; + volatile U_VEDU_VCPI_OSD_QP1 VEDU_VCPI_OSD_QP1; + volatile U_VEDU_VCPI_SW_L0_SIZE VEDU_VCPI_SW_L0_SIZE; + volatile U_VEDU_VCPI_SW_L1_SIZE VEDU_VCPI_SW_L1_SIZE; + volatile unsigned int VEDU_VCPI_PMEINFO_ST_ADDR; + volatile unsigned int VEDU_VCPI_PMEINFO_LD0_ADDR; + volatile unsigned int VEDU_VCPI_PMEINFO_LD1_ADDR; + volatile unsigned int VEDU_VCPI_QPGLD_INF_ADDR; + volatile unsigned int VEDU_VCPI_TUNLCELL_ADDR; + volatile unsigned int VEDU_VCPI_SRC_YADDR; + volatile unsigned int VEDU_VCPI_SRC_CADDR; + volatile unsigned int VEDU_VCPI_SRC_VADDR; + volatile unsigned int VEDU_VCPI_YH_ADDR; + volatile unsigned int VEDU_VCPI_CH_ADDR; + volatile U_VEDU_VCPI_STRIDE VEDU_VCPI_STRIDE; + volatile unsigned int VEDU_VCPI_REC_YADDR; + volatile unsigned int VEDU_VCPI_REC_CADDR; + volatile U_VEDU_VCPI_REC_STRIDE VEDU_VCPI_REC_STRIDE; + volatile unsigned int VEDU_VCPI_REC_YH_ADDR; + volatile unsigned int VEDU_VCPI_REC_CH_ADDR; + volatile U_VEDU_VCPI_REC_HEAD_STRIDE VEDU_VCPI_REC_HEAD_STRIDE; + volatile unsigned int VEDU_VCPI_REFY_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFC_L0_ADDR; + volatile U_VEDU_VCPI_REF_L0_STRIDE VEDU_VCPI_REF_L0_STRIDE; + volatile unsigned int VEDU_VCPI_REFYH_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFCH_L0_ADDR; + volatile U_VEDU_VCPI_REFH_L0_STRIDE VEDU_VCPI_REFH_L0_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFY_L1_ADDR; + volatile unsigned int VEDU_VCPI_REFC_L1_ADDR; + volatile U_VEDU_VCPI_REF_L1_STRIDE VEDU_VCPI_REF_L1_STRIDE; + volatile unsigned int VEDU_VCPI_REFYH_L1_ADDR; + volatile unsigned int VEDU_VCPI_REFCH_L1_ADDR; + volatile U_VEDU_VCPI_REFH_L1_STRIDE VEDU_VCPI_REFH_L1_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_L1_ADDR; + volatile unsigned int VEDU_VCPI_PMEST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_UPST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_MVST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_MVLD_ADDR; + volatile unsigned int VEDU_VCPI_STRMADDR; + volatile unsigned int VEDU_VCPI_SWPTRADDR; + volatile unsigned int VEDU_VCPI_SRPTRADDR; + volatile unsigned int VEDU_VCPI_LLILD_ADDR; + volatile U_VEDU_VCPI_STRFMT VEDU_VCPI_STRFMT; + volatile U_VEDU_VCPI_CROP_START VEDU_VCPI_CROP_START; + volatile U_VEDU_VCPI_CROP_END VEDU_VCPI_CROP_END; + volatile U_VEDU_VCPI_SCALE_PARA VEDU_VCPI_SCALE_PARA; + volatile U_VEDU_VCPI_ORI_PICSIZE VEDU_VCPI_ORI_PICSIZE; + volatile U_VEDU_VCPI_BG_ENABLE VEDU_VCPI_BG_ENABLE; + volatile unsigned int VEDU_VCPI_BGL_ADDR; + volatile unsigned int VEDU_VCPI_BGC_ADDR; + volatile unsigned int VEDU_VCPI_BGINF_ADDR; + volatile U_VEDU_VCPI_BG_STRIDE VEDU_VCPI_BG_STRIDE; + volatile U_VEDU_VCPI_BG_FLT_PARA0 VEDU_VCPI_BG_FLT_PARA0; + volatile U_VEDU_VCPI_BG_FLT_PARA1 VEDU_VCPI_BG_FLT_PARA1; + volatile U_VEDU_VCPI_BG_FLT_PARA2 VEDU_VCPI_BG_FLT_PARA2; + volatile U_VEDU_VCPI_BG_THR0 VEDU_VCPI_BG_THR0; + volatile U_VEDU_VCPI_BG_THR1 VEDU_VCPI_BG_THR1; + volatile U_VEDU_VCPI_MEM_CTRL_T16 VEDU_VCPI_MEM_CTRL_T16; + volatile unsigned int VEDU_VCPI_PMEST_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_STRIDE; + volatile U_VEDU_VCPI_INTRA32_LOW_POWER VEDU_VCPI_INTRA32_LOW_POWER; + volatile U_VEDU_VCPI_INTRA16_LOW_POWER VEDU_VCPI_INTRA16_LOW_POWER; + volatile U_VEDU_VCPI_INTRA_REDUCE_RDO_NUM VEDU_VCPI_INTRA_REDUCE_RDO_NUM; + volatile unsigned int VEDU_VCPI_DBLK_INFO_ADDR; + volatile U_VEDU_VCPI_NOFORCEZERO VEDU_VCPI_NOFORCEZERO; + volatile U_VEDU_VCPI_INTMASK_S VEDU_VCPI_INTMASK_S; + volatile U_VEDU_VCPI_INTCLR_S VEDU_VCPI_INTCLR_S; + volatile unsigned int RESERVED_VCPI[10]; + volatile U_VEDU_VCTRL_ROI_CFG0 VEDU_VCTRL_ROI_CFG0; + volatile U_VEDU_VCTRL_ROI_CFG1 VEDU_VCTRL_ROI_CFG1; + volatile U_VEDU_VCTRL_ROI_CFG2 VEDU_VCTRL_ROI_CFG2; + volatile U_VEDU_VCTRL_ROI_SIZE_0 VEDU_VCTRL_ROI_SIZE_0; + volatile U_VEDU_VCTRL_ROI_SIZE_1 VEDU_VCTRL_ROI_SIZE_1; + volatile U_VEDU_VCTRL_ROI_SIZE_2 VEDU_VCTRL_ROI_SIZE_2; + volatile U_VEDU_VCTRL_ROI_SIZE_3 VEDU_VCTRL_ROI_SIZE_3; + volatile U_VEDU_VCTRL_ROI_SIZE_4 VEDU_VCTRL_ROI_SIZE_4; + volatile U_VEDU_VCTRL_ROI_SIZE_5 VEDU_VCTRL_ROI_SIZE_5; + volatile U_VEDU_VCTRL_ROI_SIZE_6 VEDU_VCTRL_ROI_SIZE_6; + volatile U_VEDU_VCTRL_ROI_SIZE_7 VEDU_VCTRL_ROI_SIZE_7; + volatile U_VEDU_VCTRL_ROI_START_0 VEDU_VCTRL_ROI_START_0; + volatile U_VEDU_VCTRL_ROI_START_1 VEDU_VCTRL_ROI_START_1; + volatile U_VEDU_VCTRL_ROI_START_2 VEDU_VCTRL_ROI_START_2; + volatile U_VEDU_VCTRL_ROI_START_3 VEDU_VCTRL_ROI_START_3; + volatile U_VEDU_VCTRL_ROI_START_4 VEDU_VCTRL_ROI_START_4; + volatile U_VEDU_VCTRL_ROI_START_5 VEDU_VCTRL_ROI_START_5; + volatile U_VEDU_VCTRL_ROI_START_6 VEDU_VCTRL_ROI_START_6; + volatile U_VEDU_VCTRL_ROI_START_7 VEDU_VCTRL_ROI_START_7; + volatile U_VEDU_VCTRL_LCU_TARGET_BIT VEDU_VCTRL_LCU_TARGET_BIT; + volatile U_VEDU_VCTRL_NARROW_THRESHOLD VEDU_VCTRL_NARROW_THRESHOLD; + volatile U_VEDU_VCTRL_LCU_BASELINE VEDU_VCTRL_LCU_BASELINE; + volatile U_VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_COEFF_DENOISE VEDU_VCTRL_NORM_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_ENG_DENOISE VEDU_VCTRL_NORM_ENG_DENOISE; + volatile U_VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_COEFF_DENOISE VEDU_VCTRL_SKIN_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_ENG_DENOISE VEDU_VCTRL_SKIN_ENG_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_COEFF_DENOISE VEDU_VCTRL_HEDGE_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_ENG_DENOISE VEDU_VCTRL_HEDGE_ENG_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_ENG_DENOISE VEDU_VCTRL_HEDGEMOV_ENG_DENOISE; + volatile U_VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_COEFF_DENOISE VEDU_VCTRL_STATIC_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_ENG_DENOISE VEDU_VCTRL_STATIC_ENG_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_ENG_DENOISE VEDU_VCTRL_SOBELSTR_ENG_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_ENG_DENOISE VEDU_VCTRL_SOBELWEAK_ENG_DENOISE; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_0 VEDU_VCTRL_INTRA_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_1 VEDU_VCTRL_INTRA_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_2 VEDU_VCTRL_INTRA_RDO_FACTOR_2; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_0 VEDU_VCTRL_MRG_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_1 VEDU_VCTRL_MRG_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_2 VEDU_VCTRL_MRG_RDO_FACTOR_2; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_0 VEDU_VCTRL_FME_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_1 VEDU_VCTRL_FME_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_2 VEDU_VCTRL_FME_RDO_FACTOR_2; + volatile unsigned int RESERVED_VCTRL[69]; + volatile U_VEDU_CURLD_GCFG VEDU_CURLD_GCFG; + volatile U_VEDU_CURLD_OSD01_ALPHA VEDU_CURLD_OSD01_ALPHA; + volatile U_VEDU_CURLD_OSD23_ALPHA VEDU_CURLD_OSD23_ALPHA; + volatile U_VEDU_CURLD_OSD45_ALPHA VEDU_CURLD_OSD45_ALPHA; + volatile U_VEDU_CURLD_OSD67_ALPHA VEDU_CURLD_OSD67_ALPHA; + volatile U_VEDU_CURLD_OSD_GALPHA0 VEDU_CURLD_OSD_GALPHA0; + volatile U_VEDU_CURLD_OSD_GALPHA1 VEDU_CURLD_OSD_GALPHA1; + volatile unsigned int VEDU_CURLD_OSD0_ADDR; + volatile unsigned int VEDU_CURLD_OSD1_ADDR; + volatile unsigned int VEDU_CURLD_OSD2_ADDR; + volatile unsigned int VEDU_CURLD_OSD3_ADDR; + volatile unsigned int VEDU_CURLD_OSD4_ADDR; + volatile unsigned int VEDU_CURLD_OSD5_ADDR; + volatile unsigned int VEDU_CURLD_OSD6_ADDR; + volatile unsigned int VEDU_CURLD_OSD7_ADDR; + volatile U_VEDU_CURLD_OSD01_STRIDE VEDU_CURLD_OSD01_STRIDE; + volatile U_VEDU_CURLD_OSD23_STRIDE VEDU_CURLD_OSD23_STRIDE; + volatile U_VEDU_CURLD_OSD45_STRIDE VEDU_CURLD_OSD45_STRIDE; + volatile U_VEDU_CURLD_OSD67_STRIDE VEDU_CURLD_OSD67_STRIDE; + volatile U_VEDU_CURLD_CLIP_THR VEDU_CURLD_CLIP_THR; + volatile U_VEDU_CURLD_HOR_FILTER VEDU_CURLD_HOR_FILTER; + volatile U_VEDU_CURLD_VER_FILTER VEDU_CURLD_VER_FILTER; + volatile U_VEDU_CURLD_ARGB_YUV_0COEFF VEDU_CURLD_ARGB_YUV_0COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_1COEFF VEDU_CURLD_ARGB_YUV_1COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_2COEFF VEDU_CURLD_ARGB_YUV_2COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_3COEFF VEDU_CURLD_ARGB_YUV_3COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_4COEFF VEDU_CURLD_ARGB_YUV_4COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_5COEFF VEDU_CURLD_ARGB_YUV_5COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_6COEFF VEDU_CURLD_ARGB_YUV_6COEFF; + volatile U_VEDU_CURLD_ARGB_CLIP VEDU_CURLD_ARGB_CLIP; + volatile U_VEDU_CURLD_NARROW_EN VEDU_CURLD_NARROW_EN; + volatile U_VEDU_CURLD_SRCH_STRIDE VEDU_CURLD_SRCH_STRIDE; + volatile U_VEDU_CURLD_HFBCD VEDU_CURLD_HFBCD; + volatile unsigned int RESERVED_CURLD[31]; + volatile unsigned int RESERVED_NBI[64]; + volatile U_VEDU_PME_SW_ADAPT_EN VEDU_PME_SW_ADAPT_EN; + volatile U_VEDU_PME_SW_THR0 VEDU_PME_SW_THR0; + volatile U_VEDU_PME_SW_THR1 VEDU_PME_SW_THR1; + volatile U_VEDU_PME_SW_THR2 VEDU_PME_SW_THR2; + volatile U_VEDU_PME_SKIP_PRE VEDU_PME_SKIP_PRE; + volatile U_VEDU_PME_TR_WEIGHTX VEDU_PME_TR_WEIGHTX; + volatile U_VEDU_PME_TR_WEIGHTY VEDU_PME_TR_WEIGHTY; + volatile U_VEDU_PME_SR_WEIGHT VEDU_PME_SR_WEIGHT; + volatile U_VEDU_PME_INTRABLK_DET VEDU_PME_INTRABLK_DET; + volatile U_VEDU_PME_INTRABLK_DET_THR VEDU_PME_INTRABLK_DET_THR; + volatile U_VEDU_PME_SKIN_THR VEDU_PME_SKIN_THR; + volatile U_VEDU_PME_INTRA_LOWPOW VEDU_PME_INTRA_LOWPOW; + volatile U_VEDU_PME_IBLK_COST_THR VEDU_PME_IBLK_COST_THR; + volatile U_VEDU_PME_STRONG_EDGE VEDU_PME_STRONG_EDGE; + volatile U_VEDU_PME_LARGE_MOVE_THR VEDU_PME_LARGE_MOVE_THR; + volatile U_VEDU_PME_INTER_STRONG_EDGE VEDU_PME_INTER_STRONG_EDGE; + volatile U_VEDU_PME_NEW_COST VEDU_PME_NEW_COST; + volatile U_VEDU_PME_WINDOW_SIZE0_L0 VEDU_PME_WINDOW_SIZE0_L0; + volatile U_VEDU_PME_WINDOW_SIZE1_L0 VEDU_PME_WINDOW_SIZE1_L0; + volatile U_VEDU_PME_WINDOW_SIZE2_L0 VEDU_PME_WINDOW_SIZE2_L0; + volatile U_VEDU_PME_WINDOW_SIZE3_L0 VEDU_PME_WINDOW_SIZE3_L0; + volatile U_VEDU_PME_WINDOW_SIZE0_L1 VEDU_PME_WINDOW_SIZE0_L1; + volatile U_VEDU_PME_WINDOW_SIZE1_L1 VEDU_PME_WINDOW_SIZE1_L1; + volatile U_VEDU_PME_WINDOW_SIZE2_L1 VEDU_PME_WINDOW_SIZE2_L1; + volatile U_VEDU_PME_WINDOW_SIZE3_L1 VEDU_PME_WINDOW_SIZE3_L1; + volatile U_VEDU_PME_COST_OFFSET VEDU_PME_COST_OFFSET; + volatile U_VEDU_PME_SAFE_CFG VEDU_PME_SAFE_CFG; + volatile U_VEDU_PME_IBLK_REFRESH VEDU_PME_IBLK_REFRESH; + volatile U_VEDU_PME_IBLK_REFRESH_NUM VEDU_PME_IBLK_REFRESH_NUM; + volatile U_VEDU_PME_QPG_RC_THR0 VEDU_PME_QPG_RC_THR0; + volatile U_VEDU_PME_QPG_RC_THR1 VEDU_PME_QPG_RC_THR1; + volatile U_VEDU_PME_LOW_LUMA_THR VEDU_PME_LOW_LUMA_THR; + volatile U_VEDU_PME_PBLK_PRE1 VEDU_PME_PBLK_PRE1; + volatile U_VEDU_PME_CHROMA_FLAT VEDU_PME_CHROMA_FLAT; + volatile U_VEDU_PME_LUMA_FLAT VEDU_PME_LUMA_FLAT; + volatile U_VEDU_PME_MADI_FLAT VEDU_PME_MADI_FLAT; + volatile U_VEDU_PME_SKIP_LARGE_RES VEDU_PME_SKIP_LARGE_RES; + volatile unsigned int RESERVED_PME[91]; + volatile unsigned int RESERVED_PMEST[64]; + volatile U_VEDU_QPG_MAX_MIN_QP VEDU_QPG_MAX_MIN_QP; + volatile U_VEDU_QPG_ROW_TARGET_BITS VEDU_QPG_ROW_TARGET_BITS; + volatile U_VEDU_QPG_AVERAGE_LCU_BITS VEDU_QPG_AVERAGE_LCU_BITS; + volatile U_VEDU_QPG_LOWLUMA VEDU_QPG_LOWLUMA; + volatile U_VEDU_QPG_HEDGE VEDU_QPG_HEDGE; + volatile U_VEDU_QPG_HEDGE_MOVE VEDU_QPG_HEDGE_MOVE; + volatile U_VEDU_QPG_LARGE_MOVE VEDU_QPG_LARGE_MOVE; + volatile U_VEDU_QPG_SKIN VEDU_QPG_SKIN; + volatile U_VEDU_QPG_INTRA_DET VEDU_QPG_INTRA_DET; + volatile U_VEDU_QPG_H264_SMOOTH VEDU_QPG_H264_SMOOTH; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG0 VEDU_QPG_CU_QP_DELTA_THRESH_REG0; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG1 VEDU_QPG_CU_QP_DELTA_THRESH_REG1; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG2 VEDU_QPG_CU_QP_DELTA_THRESH_REG2; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG3 VEDU_QPG_CU_QP_DELTA_THRESH_REG3; + volatile U_VEDU_QPG_DELTA_LEVEL VEDU_QPG_DELTA_LEVEL; + volatile U_VEDU_QPG_MADI_SWITCH_THR VEDU_QPG_MADI_SWITCH_THR; + volatile U_VEDU_QPG_CU32_DELTA VEDU_QPG_CU32_DELTA; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG00 VEDU_QPG_QP_LAMBDA_CTRL_REG00; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG01 VEDU_QPG_QP_LAMBDA_CTRL_REG01; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG02 VEDU_QPG_QP_LAMBDA_CTRL_REG02; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG03 VEDU_QPG_QP_LAMBDA_CTRL_REG03; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG04 VEDU_QPG_QP_LAMBDA_CTRL_REG04; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG05 VEDU_QPG_QP_LAMBDA_CTRL_REG05; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG06 VEDU_QPG_QP_LAMBDA_CTRL_REG06; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG07 VEDU_QPG_QP_LAMBDA_CTRL_REG07; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG08 VEDU_QPG_QP_LAMBDA_CTRL_REG08; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG09 VEDU_QPG_QP_LAMBDA_CTRL_REG09; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG10 VEDU_QPG_QP_LAMBDA_CTRL_REG10; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG11 VEDU_QPG_QP_LAMBDA_CTRL_REG11; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG12 VEDU_QPG_QP_LAMBDA_CTRL_REG12; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG13 VEDU_QPG_QP_LAMBDA_CTRL_REG13; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG14 VEDU_QPG_QP_LAMBDA_CTRL_REG14; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG15 VEDU_QPG_QP_LAMBDA_CTRL_REG15; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG16 VEDU_QPG_QP_LAMBDA_CTRL_REG16; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG17 VEDU_QPG_QP_LAMBDA_CTRL_REG17; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG18 VEDU_QPG_QP_LAMBDA_CTRL_REG18; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG19 VEDU_QPG_QP_LAMBDA_CTRL_REG19; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG20 VEDU_QPG_QP_LAMBDA_CTRL_REG20; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG21 VEDU_QPG_QP_LAMBDA_CTRL_REG21; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG22 VEDU_QPG_QP_LAMBDA_CTRL_REG22; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG23 VEDU_QPG_QP_LAMBDA_CTRL_REG23; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG24 VEDU_QPG_QP_LAMBDA_CTRL_REG24; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG25 VEDU_QPG_QP_LAMBDA_CTRL_REG25; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG26 VEDU_QPG_QP_LAMBDA_CTRL_REG26; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG27 VEDU_QPG_QP_LAMBDA_CTRL_REG27; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG28 VEDU_QPG_QP_LAMBDA_CTRL_REG28; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG29 VEDU_QPG_QP_LAMBDA_CTRL_REG29; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG30 VEDU_QPG_QP_LAMBDA_CTRL_REG30; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG31 VEDU_QPG_QP_LAMBDA_CTRL_REG31; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG32 VEDU_QPG_QP_LAMBDA_CTRL_REG32; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG33 VEDU_QPG_QP_LAMBDA_CTRL_REG33; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG34 VEDU_QPG_QP_LAMBDA_CTRL_REG34; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG35 VEDU_QPG_QP_LAMBDA_CTRL_REG35; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG36 VEDU_QPG_QP_LAMBDA_CTRL_REG36; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG37 VEDU_QPG_QP_LAMBDA_CTRL_REG37; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG38 VEDU_QPG_QP_LAMBDA_CTRL_REG38; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG39 VEDU_QPG_QP_LAMBDA_CTRL_REG39; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG40 VEDU_QPG_QP_LAMBDA_CTRL_REG40; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG41 VEDU_QPG_QP_LAMBDA_CTRL_REG41; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG42 VEDU_QPG_QP_LAMBDA_CTRL_REG42; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG43 VEDU_QPG_QP_LAMBDA_CTRL_REG43; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG44 VEDU_QPG_QP_LAMBDA_CTRL_REG44; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG45 VEDU_QPG_QP_LAMBDA_CTRL_REG45; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG46 VEDU_QPG_QP_LAMBDA_CTRL_REG46; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG47 VEDU_QPG_QP_LAMBDA_CTRL_REG47; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG48 VEDU_QPG_QP_LAMBDA_CTRL_REG48; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG49 VEDU_QPG_QP_LAMBDA_CTRL_REG49; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG50 VEDU_QPG_QP_LAMBDA_CTRL_REG50; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG51 VEDU_QPG_QP_LAMBDA_CTRL_REG51; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG52 VEDU_QPG_QP_LAMBDA_CTRL_REG52; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG53 VEDU_QPG_QP_LAMBDA_CTRL_REG53; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG54 VEDU_QPG_QP_LAMBDA_CTRL_REG54; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG55 VEDU_QPG_QP_LAMBDA_CTRL_REG55; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG56 VEDU_QPG_QP_LAMBDA_CTRL_REG56; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG57 VEDU_QPG_QP_LAMBDA_CTRL_REG57; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG58 VEDU_QPG_QP_LAMBDA_CTRL_REG58; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG59 VEDU_QPG_QP_LAMBDA_CTRL_REG59; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG60 VEDU_QPG_QP_LAMBDA_CTRL_REG60; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG61 VEDU_QPG_QP_LAMBDA_CTRL_REG61; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG62 VEDU_QPG_QP_LAMBDA_CTRL_REG62; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG63 VEDU_QPG_QP_LAMBDA_CTRL_REG63; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG64 VEDU_QPG_QP_LAMBDA_CTRL_REG64; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG65 VEDU_QPG_QP_LAMBDA_CTRL_REG65; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG66 VEDU_QPG_QP_LAMBDA_CTRL_REG66; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG67 VEDU_QPG_QP_LAMBDA_CTRL_REG67; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG68 VEDU_QPG_QP_LAMBDA_CTRL_REG68; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG69 VEDU_QPG_QP_LAMBDA_CTRL_REG69; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG70 VEDU_QPG_QP_LAMBDA_CTRL_REG70; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG71 VEDU_QPG_QP_LAMBDA_CTRL_REG71; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG72 VEDU_QPG_QP_LAMBDA_CTRL_REG72; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG73 VEDU_QPG_QP_LAMBDA_CTRL_REG73; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG74 VEDU_QPG_QP_LAMBDA_CTRL_REG74; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG75 VEDU_QPG_QP_LAMBDA_CTRL_REG75; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG76 VEDU_QPG_QP_LAMBDA_CTRL_REG76; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG77 VEDU_QPG_QP_LAMBDA_CTRL_REG77; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG78 VEDU_QPG_QP_LAMBDA_CTRL_REG78; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG79 VEDU_QPG_QP_LAMBDA_CTRL_REG79; + volatile U_VEDU_QPG_LAMBDA_MODE VEDU_QPG_LAMBDA_MODE; + volatile U_VEDU_QPG_QP_RESTRAIN VEDU_QPG_QP_RESTRAIN; + volatile unsigned int VEDU_QPG_CU_MIN_SAD_THRESH_0; + volatile unsigned int VEDU_QPG_CU_MIN_SAD_THRESH_1; + volatile U_VEDU_QPG_CU_MIN_SAD_REG VEDU_QPG_CU_MIN_SAD_REG; + volatile U_VEDU_QPG_SMART_REG VEDU_QPG_SMART_REG; + volatile U_VEDU_QPG_FLAT_REGION VEDU_QPG_FLAT_REGION; + volatile unsigned int RESERVED_QPG[88]; + volatile unsigned int RESERVED_REFLD[64]; + volatile U_VEDU_IME_INTER_MODE VEDU_IME_INTER_MODE; + volatile U_VEDU_IME_RDOCFG VEDU_IME_RDOCFG; + volatile U_VEDU_IME_FME_LPOW_THR VEDU_IME_FME_LPOW_THR; + volatile U_VEDU_IME_LAYER3TO2_THR VEDU_IME_LAYER3TO2_THR; + volatile U_VEDU_IME_LAYER3TO2_THR1 VEDU_IME_LAYER3TO2_THR1; + volatile U_VEDU_IME_LAYER3TO1_THR VEDU_IME_LAYER3TO1_THR; + volatile U_VEDU_IME_LAYER3TO1_THR1 VEDU_IME_LAYER3TO1_THR1; + volatile unsigned int RESERVED_IME[57]; + volatile U_VEDU_FME_BIAS_COST0 VEDU_FME_BIAS_COST0; + volatile U_VEDU_FME_BIAS_COST1 VEDU_FME_BIAS_COST1; + volatile U_VEDU_FME_PU64_LWP VEDU_FME_PU64_LWP; + volatile unsigned int RESERVED_FME[61]; + volatile U_VEDU_MRG_FORCE_ZERO_EN VEDU_MRG_FORCE_ZERO_EN; + volatile U_VEDU_MRG_FORCE_SKIP_EN VEDU_MRG_FORCE_SKIP_EN; + volatile U_VEDU_MRG_BIAS_COST0 VEDU_MRG_BIAS_COST0; + volatile U_VEDU_MRG_BIAS_COST1 VEDU_MRG_BIAS_COST1; + volatile U_VEDU_MRG_ABS_OFFSET0 VEDU_MRG_ABS_OFFSET0; + volatile U_VEDU_MRG_ABS_OFFSET1 VEDU_MRG_ABS_OFFSET1; + volatile U_VEDU_MRG_ADJ_WEIGHT VEDU_MRG_ADJ_WEIGHT; + volatile unsigned int RESERVED_MRG[57]; + volatile U_VEDU_INTRA_CFG VEDU_INTRA_CFG; + volatile U_VEDU_INTRA_SMOOTH VEDU_INTRA_SMOOTH; + volatile U_VEDU_INTRA_BIT_WEIGHT VEDU_INTRA_BIT_WEIGHT; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_0 VEDU_INTRA_RDO_COST_OFFSET_0; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_1 VEDU_INTRA_RDO_COST_OFFSET_1; + volatile U_VEDU_INTRA_NO_DC_COST_OFFSET_0 VEDU_INTRA_NO_DC_COST_OFFSET_0; + volatile U_VEDU_INTRA_NO_DC_COST_OFFSET_1 VEDU_INTRA_NO_DC_COST_OFFSET_1; + volatile U_VEDU_INTRA_CHNL4_ANG_0EN VEDU_INTRA_CHNL4_ANG_0EN; + volatile U_VEDU_INTRA_CHNL4_ANG_1EN VEDU_INTRA_CHNL4_ANG_1EN; + volatile U_VEDU_INTRA_CHNL8_ANG_0EN VEDU_INTRA_CHNL8_ANG_0EN; + volatile U_VEDU_INTRA_CHNL8_ANG_1EN VEDU_INTRA_CHNL8_ANG_1EN; + volatile U_VEDU_INTRA_CHNL16_ANG_0EN VEDU_INTRA_CHNL16_ANG_0EN; + volatile U_VEDU_INTRA_CHNL16_ANG_1EN VEDU_INTRA_CHNL16_ANG_1EN; + volatile U_VEDU_INTRA_CHNL32_ANG_0EN VEDU_INTRA_CHNL32_ANG_0EN; + volatile U_VEDU_INTRA_CHNL32_ANG_1EN VEDU_INTRA_CHNL32_ANG_1EN; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_3 VEDU_INTRA_RDO_COST_OFFSET_3; + volatile unsigned int RESERVED_INTRA[48]; + volatile unsigned int VEDU_PMV_POC_0; + volatile unsigned int VEDU_PMV_POC_1; + volatile unsigned int VEDU_PMV_POC_2; + volatile unsigned int VEDU_PMV_POC_3; + volatile unsigned int VEDU_PMV_POC_4; + volatile unsigned int VEDU_PMV_POC_5; + volatile U_VEDU_PMV_TMV_EN VEDU_PMV_TMV_EN; + volatile unsigned int RESERVED_PMV[57]; + volatile U_VEDU_TQITQ_DEADZONE VEDU_TQITQ_DEADZONE; + volatile unsigned int RESERVED_TQITQ[191]; + volatile unsigned int RESERVED0_SEL[4]; + volatile U_VEDU_SEL_OFFSET_STRENGTH VEDU_SEL_OFFSET_STRENGTH; + volatile U_VEDU_SEL_CU32_DC_AC_TH_OFFSET VEDU_SEL_CU32_DC_AC_TH_OFFSET; + volatile U_VEDU_SEL_CU32_QP_TH VEDU_SEL_CU32_QP_TH; + volatile U_VEDU_SEL_RES_DC_AC_TH VEDU_SEL_RES_DC_AC_TH; + volatile unsigned int RESERVED1_SEL[56]; + volatile unsigned int RESERVED_DBLK[64]; + volatile unsigned int VEDU_SAO_SSD_AERA0; + volatile unsigned int VEDU_SAO_SSD_AERA1; + volatile unsigned int VEDU_SAO_SSD_AERA2; + volatile unsigned int VEDU_SAO_SSD_AERA3; + volatile unsigned int VEDU_SAO_SSD_AERA4; + volatile unsigned int VEDU_SAO_SSD_AERA5; + volatile unsigned int VEDU_SAO_SSD_AERA6; + volatile unsigned int VEDU_SAO_SSD_AERA7; + volatile unsigned int RESERVED_SAO[56]; + volatile U_VEDU_EMAR_WAIT_TIM_OUT VEDU_EMAR_WAIT_TIM_OUT; + volatile U_VEDU_EMAR_RCH_RPT_TH0 VEDU_EMAR_RCH_RPT_TH0; + volatile U_VEDU_EMAR_RCH_RPT_TH1 VEDU_EMAR_RCH_RPT_TH1; + volatile U_VEDU_EMAR_RCH_RPT_TH2 VEDU_EMAR_RCH_RPT_TH2; + volatile U_VEDU_EMAR_WCH_RPT_TH0 VEDU_EMAR_WCH_RPT_TH0; + volatile U_VEDU_EMAR_WCH_RPT_TH1 VEDU_EMAR_WCH_RPT_TH1; + volatile U_VEDU_EMAR_WCH_RPT_TH2 VEDU_EMAR_WCH_RPT_TH2; + volatile U_VEDU_EMAR_SCRAMBLE_TYPE VEDU_EMAR_SCRAMBLE_TYPE; + volatile unsigned int RESERVED_EMAR[56]; + volatile unsigned int VEDU_PACK_SYNTAX_CONFIG; + volatile U_VEDU_PACK_CU_PARAMETER VEDU_PACK_CU_PARAMETER; + volatile U_VEDU_PACK_PCM_PARAMETER VEDU_PACK_PCM_PARAMETER; + volatile U_VEDU_PACK_TF_SKIP_FLAG VEDU_PACK_TF_SKIP_FLAG; + volatile unsigned int RESERVED_PACK[60]; + volatile U_VEDU_CABAC_GLB_CFG VEDU_CABAC_GLB_CFG; + volatile U_VEDU_CABAC_SLCHDR_SIZE VEDU_CABAC_SLCHDR_SIZE; + volatile U_VEDU_CABAC_SLCHDR_PART1 VEDU_CABAC_SLCHDR_PART1; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG1; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG2; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG3; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG4; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG5; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG6; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG7; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG8; + volatile U_VEDU_CABAC_SLCHDR_SIZE_I VEDU_CABAC_SLCHDR_SIZE_I; + volatile U_VEDU_CABAC_SLCHDR_PART1_I VEDU_CABAC_SLCHDR_PART1_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG1_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG2_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG3_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG4_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG5_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG6_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG7_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG8_I; + volatile unsigned int RESERVED_CABAC[43]; + volatile unsigned int VEDU_VLC_SLCHDRSTRM0; + volatile unsigned int VEDU_VLC_SLCHDRSTRM1; + volatile unsigned int VEDU_VLC_SLCHDRSTRM2; + volatile unsigned int VEDU_VLC_SLCHDRSTRM3; + volatile unsigned int VEDU_VLC_REORDERSTRM0; + volatile unsigned int VEDU_VLC_REORDERSTRM1; + volatile unsigned int VEDU_VLC_MARKINGSTRM0; + volatile unsigned int VEDU_VLC_MARKINGSTRM1; + volatile U_VEDU_VLC_SLCHDRPARA VEDU_VLC_SLCHDRPARA; + volatile U_VEDU_VLC_SVC VEDU_VLC_SVC; + volatile unsigned int VEDU_VLC_SLCHDRSTRM0_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM1_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM2_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM3_I; + volatile unsigned int VEDU_VLC_REORDERSTRM0_I; + volatile unsigned int VEDU_VLC_REORDERSTRM1_I; + volatile unsigned int VEDU_VLC_MARKINGSTRM0_I; + volatile unsigned int VEDU_VLC_MARKINGSTRM1_I; + volatile U_VEDU_VLC_SLCHDRPARA_I VEDU_VLC_SLCHDRPARA_I; + volatile unsigned int RESERVED_VLC[45]; + volatile unsigned int RESERVED_VLCST0; + volatile U_VEDU_VLCST_PTBITS_EN VEDU_VLCST_PTBITS_EN; + volatile unsigned int VEDU_VLCST_PTBITS; + volatile unsigned int VEDU_VLCST_STRMBUFLEN0; + volatile unsigned int VEDU_VLCST_STRMBUFLEN1; + volatile unsigned int VEDU_VLCST_STRMBUFLEN2; + volatile unsigned int VEDU_VLCST_STRMBUFLEN3; + volatile unsigned int VEDU_VLCST_STRMBUFLEN4; + volatile unsigned int VEDU_VLCST_STRMBUFLEN5; + volatile unsigned int VEDU_VLCST_STRMBUFLEN6; + volatile unsigned int VEDU_VLCST_STRMBUFLEN7; + volatile unsigned int VEDU_VLCST_STRMBUFLEN8; + volatile unsigned int VEDU_VLCST_STRMBUFLEN9; + volatile unsigned int VEDU_VLCST_STRMBUFLEN10; + volatile unsigned int VEDU_VLCST_STRMBUFLEN11; + volatile unsigned int VEDU_VLCST_STRMBUFLEN12; + volatile unsigned int VEDU_VLCST_STRMBUFLEN13; + volatile unsigned int VEDU_VLCST_STRMBUFLEN14; + volatile unsigned int VEDU_VLCST_STRMBUFLEN15; + volatile unsigned int VEDU_VLCST_STRMADDR0; + volatile unsigned int VEDU_VLCST_STRMADDR1; + volatile unsigned int VEDU_VLCST_STRMADDR2; + volatile unsigned int VEDU_VLCST_STRMADDR3; + volatile unsigned int VEDU_VLCST_STRMADDR4; + volatile unsigned int VEDU_VLCST_STRMADDR5; + volatile unsigned int VEDU_VLCST_STRMADDR6; + volatile unsigned int VEDU_VLCST_STRMADDR7; + volatile unsigned int VEDU_VLCST_STRMADDR8; + volatile unsigned int VEDU_VLCST_STRMADDR9; + volatile unsigned int VEDU_VLCST_STRMADDR10; + volatile unsigned int VEDU_VLCST_STRMADDR11; + volatile unsigned int VEDU_VLCST_STRMADDR12; + volatile unsigned int VEDU_VLCST_STRMADDR13; + volatile unsigned int VEDU_VLCST_STRMADDR14; + volatile unsigned int VEDU_VLCST_STRMADDR15; + volatile unsigned int VEDU_VLCST_PARA_ADDR; + volatile U_VEDU_VLCST_PARAMETER VEDU_VLCST_PARAMETER; + volatile unsigned int VEDU_VLCST_PARA_DATA0; + volatile unsigned int VEDU_VLCST_PARA_DATA1; + volatile unsigned int VEDU_VLCST_PARA_DATA2; + volatile unsigned int VEDU_VLCST_PARA_DATA3; + volatile unsigned int VEDU_VLCST_PARA_DATA4; + volatile unsigned int VEDU_VLCST_PARA_DATA5; + volatile unsigned int VEDU_VLCST_PARA_DATA6; + volatile unsigned int VEDU_VLCST_PARA_DATA7; + volatile unsigned int VEDU_VLCST_PARA_DATA8; + volatile unsigned int VEDU_VLCST_PARA_DATA9; + volatile unsigned int VEDU_VLCST_PARA_DATA10; + volatile unsigned int VEDU_VLCST_PARA_DATA11; + volatile unsigned int VEDU_VLCST_PARA_DATA12; + volatile unsigned int VEDU_VLCST_PARA_DATA13; + volatile unsigned int VEDU_VLCST_PARA_DATA14; + volatile unsigned int VEDU_VLCST_PARA_DATA15; + volatile unsigned int VEDU_VLCST_PARA_DATA16; + volatile unsigned int VEDU_VLCST_PARA_DATA17; + volatile unsigned int VEDU_VLCST_PARA_DATA18; + volatile unsigned int VEDU_VLCST_PARA_DATA19; + volatile unsigned int VEDU_VLCST_PARA_DATA20; + volatile unsigned int VEDU_VLCST_PARA_DATA21; + volatile unsigned int VEDU_VLCST_PARA_DATA22; + volatile unsigned int VEDU_VLCST_PARA_DATA23; + volatile unsigned int VEDU_VLCST_PARA_DATA24; + volatile unsigned int VEDU_VLCST_PARA_DATA25; + volatile unsigned int VEDU_VLCST_PARA_DATA26; + volatile unsigned int VEDU_VLCST_PARA_DATA27; + volatile unsigned int VEDU_VLCST_PARA_DATA28; + volatile unsigned int VEDU_VLCST_PARA_DATA29; + volatile unsigned int VEDU_VLCST_PARA_DATA30; + volatile unsigned int VEDU_VLCST_PARA_DATA31; + volatile unsigned int VEDU_VLCST_PARA_DATA32; + volatile unsigned int VEDU_VLCST_PARA_DATA33; + volatile unsigned int VEDU_VLCST_PARA_DATA34; + volatile unsigned int VEDU_VLCST_PARA_DATA35; + volatile unsigned int VEDU_VLCST_PARA_DATA36; + volatile unsigned int VEDU_VLCST_PARA_DATA37; + volatile unsigned int VEDU_VLCST_PARA_DATA38; + volatile unsigned int VEDU_VLCST_PARA_DATA39; + volatile unsigned int VEDU_VLCST_PARA_DATA40; + volatile unsigned int VEDU_VLCST_PARA_DATA41; + volatile unsigned int VEDU_VLCST_PARA_DATA42; + volatile unsigned int VEDU_VLCST_PARA_DATA43; + volatile unsigned int VEDU_VLCST_PARA_DATA44; + volatile unsigned int VEDU_VLCST_PARA_DATA45; + volatile unsigned int VEDU_VLCST_PARA_DATA46; + volatile unsigned int VEDU_VLCST_PARA_DATA47; + volatile unsigned int RESERVED_VLCST1[43]; + volatile unsigned int VEDU_PPFD_ST_ADDR0; + volatile unsigned int VEDU_PPFD_ST_ADDR1; + volatile unsigned int VEDU_PPFD_ST_LEN0; + volatile unsigned int VEDU_PPFD_ST_LEN1; + volatile U_VEDU_PPFD_ST_CFG VEDU_PPFD_ST_CFG; + volatile unsigned int RESERVED_PPFD[59]; + volatile U_VEDU_ENV_CHN VEDU_ENV_CHN; + volatile unsigned int RESERVED_ENV[1087]; + volatile U_FUNC_VCPI_INTSTAT FUNC_VCPI_INTSTAT; + volatile U_FUNC_VCPI_RAWINT FUNC_VCPI_RAWINT; + volatile unsigned int FUNC_VCPI_VEDU_TIMER; + volatile unsigned int FUNC_VCPI_IDLE_TIMER; + volatile U_FUNC_VCPI_INTSTAT_S FUNC_VCPI_INTSTAT_S; + volatile U_FUNC_VCPI_RAWINT_S FUNC_VCPI_RAWINT_S; + volatile unsigned int RESERVED_FUNC_VCPI[10]; + volatile unsigned int RESERVED_FUNC_VCTRL[16]; + volatile unsigned int RESERVED_FUNC_QPGLD[16]; + volatile unsigned int RESERVED_FUNC_CURLD[16]; + volatile unsigned int RESERVED_FUNC_NBI[16]; + volatile unsigned int RESERVED_FUNC_PMELD[16]; + volatile unsigned int RESERVED_FUNC_PMEINFO_LD[16]; + volatile U_FUNC_PME_MADI_SUM FUNC_PME_MADI_SUM; + volatile U_FUNC_PME_MADP_SUM FUNC_PME_MADP_SUM; + volatile U_FUNC_PME_MADI_NUM FUNC_PME_MADI_NUM; + volatile U_FUNC_PME_MADP_NUM FUNC_PME_MADP_NUM; + volatile unsigned int RESERVED_FUNC_PME[12]; + volatile unsigned int RESERVED_FUNC_PMEST[16]; + volatile unsigned int RESERVED_FUNC_PMEINFO_ST[16]; + volatile U_FUNC_BGGEN_BLOCK_COUNT FUNC_BGGEN_BLOCK_COUNT; + volatile U_FUNC_BGGEN_FRAME_BGM_DIST FUNC_BGGEN_FRAME_BGM_DIST; + volatile unsigned int RESERVED_FUNC_BGST[14]; + volatile unsigned int RESERVED_FUNC_QPG[16]; + volatile unsigned int RESERVED_FUNC_REFLD[16]; + volatile unsigned int RESERVED_FUNC_PINTRA[16]; + volatile unsigned int RESERVED_FUNC_IME[16]; + volatile unsigned int RESERVED_FUNC_FME[16]; + volatile unsigned int RESERVED_FUNC_MRG0[16]; + volatile unsigned int RESERVED_FUNC_MRG1[16]; + volatile unsigned int RESERVED_FUNC_INTRA0[16]; + volatile unsigned int RESERVED_FUNC_INTRA1[16]; + volatile unsigned int RESERVED_FUNC_PMV0[16]; + volatile unsigned int RESERVED_FUNC_PMV1[16]; + volatile unsigned int RESERVED_FUNC_TQITQ0[16]; + volatile unsigned int RESERVED_FUNC_TQITQ1[16]; + volatile unsigned int RESERVED_FUNC_XXX0[16]; + volatile unsigned int RESERVED_FUNC_LFLDST[16]; + volatile unsigned int RESERVED_FUNC_DBLK[16]; + volatile unsigned int RESERVED_FUNC_XXX1[16]; + volatile unsigned int RESERVED_FUNC_RECST[16]; + volatile unsigned int RESERVED_FUNC_PACK0[16]; + volatile unsigned int RESERVED_FUNC_PACK1[16]; + volatile unsigned int FUNC_CABAC_PIC_STRMSIZE; + volatile unsigned int FUNC_CABAC_BIT_NUM; + volatile unsigned int RESERVED_FUNC_CABAC[15]; + volatile unsigned int VLC_SLC_TTBITS; + volatile unsigned int VLC_PIC_TTBITS; + volatile unsigned int RESERVED_FUNC_VLC[13]; + volatile unsigned int FUNC_VLCST_SLC_LEN_CNT; + volatile U_FUNC_VLCST_DSRPTR00 FUNC_VLCST_DSRPTR00; + volatile U_FUNC_VLCST_DSRPTR01 FUNC_VLCST_DSRPTR01; + volatile U_FUNC_VLCST_DSRPTR10 FUNC_VLCST_DSRPTR10; + volatile U_FUNC_VLCST_DSRPTR11 FUNC_VLCST_DSRPTR11; + volatile U_FUNC_VLCST_DSRPTR20 FUNC_VLCST_DSRPTR20; + volatile U_FUNC_VLCST_DSRPTR21 FUNC_VLCST_DSRPTR21; + volatile U_FUNC_VLCST_DSRPTR30 FUNC_VLCST_DSRPTR30; + volatile U_FUNC_VLCST_DSRPTR31 FUNC_VLCST_DSRPTR31; + volatile U_FUNC_VLCST_DSRPTR40 FUNC_VLCST_DSRPTR40; + volatile U_FUNC_VLCST_DSRPTR41 FUNC_VLCST_DSRPTR41; + volatile U_FUNC_VLCST_DSRPTR50 FUNC_VLCST_DSRPTR50; + volatile U_FUNC_VLCST_DSRPTR51 FUNC_VLCST_DSRPTR51; + volatile U_FUNC_VLCST_DSRPTR60 FUNC_VLCST_DSRPTR60; + volatile U_FUNC_VLCST_DSRPTR61 FUNC_VLCST_DSRPTR61; + volatile U_FUNC_VLCST_DSRPTR70 FUNC_VLCST_DSRPTR70; + volatile U_FUNC_VLCST_DSRPTR71 FUNC_VLCST_DSRPTR71; + volatile U_FUNC_VLCST_DSRPTR80 FUNC_VLCST_DSRPTR80; + volatile U_FUNC_VLCST_DSRPTR81 FUNC_VLCST_DSRPTR81; + volatile U_FUNC_VLCST_DSRPTR90 FUNC_VLCST_DSRPTR90; + volatile U_FUNC_VLCST_DSRPTR91 FUNC_VLCST_DSRPTR91; + volatile U_FUNC_VLCST_DSRPTR100 FUNC_VLCST_DSRPTR100; + volatile U_FUNC_VLCST_DSRPTR101 FUNC_VLCST_DSRPTR101; + volatile U_FUNC_VLCST_DSRPTR110 FUNC_VLCST_DSRPTR110; + volatile U_FUNC_VLCST_DSRPTR111 FUNC_VLCST_DSRPTR111; + volatile U_FUNC_VLCST_DSRPTR120 FUNC_VLCST_DSRPTR120; + volatile U_FUNC_VLCST_DSRPTR121 FUNC_VLCST_DSRPTR121; + volatile U_FUNC_VLCST_DSRPTR130 FUNC_VLCST_DSRPTR130; + volatile U_FUNC_VLCST_DSRPTR131 FUNC_VLCST_DSRPTR131; + volatile U_FUNC_VLCST_DSRPTR140 FUNC_VLCST_DSRPTR140; + volatile U_FUNC_VLCST_DSRPTR141 FUNC_VLCST_DSRPTR141; + volatile U_FUNC_VLCST_DSRPTR150 FUNC_VLCST_DSRPTR150; + volatile U_FUNC_VLCST_DSRPTR151 FUNC_VLCST_DSRPTR151; + volatile unsigned int RESERVED_FUNC_VLCST[95]; + volatile unsigned int RESERVED_FUNC_EMAR[16]; + volatile unsigned int RESERVED_FUNC_PPFD[16]; + volatile U_FUNC_SEL_OPT_8X8_CNT FUNC_SEL_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_OPT_8X8_CNT FUNC_SEL_INTRA_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_PCM_OPT_8X8_CNT FUNC_SEL_INTRA_PCM_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_OPT_8X8_CNT FUNC_SEL_INTER_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_8X8_CNT FUNC_SEL_INTER_FME_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_8X8_CNT FUNC_SEL_INTER_MERGE_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_8X8_CNT FUNC_SEL_INTER_SKIP_OPT_8X8_CNT; + volatile U_FUNC_SEL_OPT_16X16_CNT FUNC_SEL_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTRA_OPT_16X16_CNT FUNC_SEL_INTRA_OPT_16X16_CNT; + volatile U_FUNC_SEL_OPT_4X4_CNT FUNC_SEL_OPT_4X4_CNT; + volatile unsigned int RESERVED0_FUNC_SEL; + volatile U_FUNC_SEL_INTER_OPT_16X16_CNT FUNC_SEL_INTER_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_16X16_CNT FUNC_SEL_INTER_FME_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_16X16_CNT FUNC_SEL_INTER_MERGE_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_16X16_CNT FUNC_SEL_INTER_SKIP_OPT_16X16_CNT; + volatile U_FUNC_SEL_OPT_32X32_CNT FUNC_SEL_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTRA_OPT_32X32_CNT FUNC_SEL_INTRA_OPT_32X32_CNT; + volatile unsigned int RESERVED1_FUNC_SEL; + volatile U_FUNC_SEL_INTER_OPT_32X32_CNT FUNC_SEL_INTER_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_32X32_CNT FUNC_SEL_INTER_FME_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_32X32_CNT FUNC_SEL_INTER_MERGE_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_32X32_CNT FUNC_SEL_INTER_SKIP_OPT_32X32_CNT; + volatile U_FUNC_SEL_OPT_64X64_CNT FUNC_SEL_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_64X64_CNT FUNC_SEL_INTER_FME_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_64X64_CNT FUNC_SEL_INTER_MERGE_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_64X64_CNT FUNC_SEL_INTER_SKIP_OPT_64X64_CNT; + volatile U_FUNC_SEL_TOTAL_LUMA_QP FUNC_SEL_TOTAL_LUMA_QP; + volatile U_FUNC_SEL_MAX_MIN_LUMA_QP FUNC_SEL_MAX_MIN_LUMA_QP; + volatile unsigned int RESERVED2_FUNC_SEL[35]; + volatile U_FUNC_SEL_LUMA_QP0_CNT FUNC_SEL_LUMA_QP0_CNT; + volatile U_FUNC_SEL_LUMA_QP1_CNT FUNC_SEL_LUMA_QP1_CNT; + volatile U_FUNC_SEL_LUMA_QP2_CNT FUNC_SEL_LUMA_QP2_CNT; + volatile U_FUNC_SEL_LUMA_QP3_CNT FUNC_SEL_LUMA_QP3_CNT; + volatile U_FUNC_SEL_LUMA_QP4_CNT FUNC_SEL_LUMA_QP4_CNT; + volatile U_FUNC_SEL_LUMA_QP5_CNT FUNC_SEL_LUMA_QP5_CNT; + volatile U_FUNC_SEL_LUMA_QP6_CNT FUNC_SEL_LUMA_QP6_CNT; + volatile U_FUNC_SEL_LUMA_QP7_CNT FUNC_SEL_LUMA_QP7_CNT; + volatile U_FUNC_SEL_LUMA_QP8_CNT FUNC_SEL_LUMA_QP8_CNT; + volatile U_FUNC_SEL_LUMA_QP9_CNT FUNC_SEL_LUMA_QP9_CNT; + volatile U_FUNC_SEL_LUMA_QP10_CNT FUNC_SEL_LUMA_QP10_CNT; + volatile U_FUNC_SEL_LUMA_QP11_CNT FUNC_SEL_LUMA_QP11_CNT; + volatile U_FUNC_SEL_LUMA_QP12_CNT FUNC_SEL_LUMA_QP12_CNT; + volatile U_FUNC_SEL_LUMA_QP13_CNT FUNC_SEL_LUMA_QP13_CNT; + volatile U_FUNC_SEL_LUMA_QP14_CNT FUNC_SEL_LUMA_QP14_CNT; + volatile U_FUNC_SEL_LUMA_QP15_CNT FUNC_SEL_LUMA_QP15_CNT; + volatile U_FUNC_SEL_LUMA_QP16_CNT FUNC_SEL_LUMA_QP16_CNT; + volatile U_FUNC_SEL_LUMA_QP17_CNT FUNC_SEL_LUMA_QP17_CNT; + volatile U_FUNC_SEL_LUMA_QP18_CNT FUNC_SEL_LUMA_QP18_CNT; + volatile U_FUNC_SEL_LUMA_QP19_CNT FUNC_SEL_LUMA_QP19_CNT; + volatile U_FUNC_SEL_LUMA_QP20_CNT FUNC_SEL_LUMA_QP20_CNT; + volatile U_FUNC_SEL_LUMA_QP21_CNT FUNC_SEL_LUMA_QP21_CNT; + volatile U_FUNC_SEL_LUMA_QP22_CNT FUNC_SEL_LUMA_QP22_CNT; + volatile U_FUNC_SEL_LUMA_QP23_CNT FUNC_SEL_LUMA_QP23_CNT; + volatile U_FUNC_SEL_LUMA_QP24_CNT FUNC_SEL_LUMA_QP24_CNT; + volatile U_FUNC_SEL_LUMA_QP25_CNT FUNC_SEL_LUMA_QP25_CNT; + volatile U_FUNC_SEL_LUMA_QP26_CNT FUNC_SEL_LUMA_QP26_CNT; + volatile U_FUNC_SEL_LUMA_QP27_CNT FUNC_SEL_LUMA_QP27_CNT; + volatile U_FUNC_SEL_LUMA_QP28_CNT FUNC_SEL_LUMA_QP28_CNT; + volatile U_FUNC_SEL_LUMA_QP29_CNT FUNC_SEL_LUMA_QP29_CNT; + volatile U_FUNC_SEL_LUMA_QP30_CNT FUNC_SEL_LUMA_QP30_CNT; + volatile U_FUNC_SEL_LUMA_QP31_CNT FUNC_SEL_LUMA_QP31_CNT; + volatile U_FUNC_SEL_LUMA_QP32_CNT FUNC_SEL_LUMA_QP32_CNT; + volatile U_FUNC_SEL_LUMA_QP33_CNT FUNC_SEL_LUMA_QP33_CNT; + volatile U_FUNC_SEL_LUMA_QP34_CNT FUNC_SEL_LUMA_QP34_CNT; + volatile U_FUNC_SEL_LUMA_QP35_CNT FUNC_SEL_LUMA_QP35_CNT; + volatile U_FUNC_SEL_LUMA_QP36_CNT FUNC_SEL_LUMA_QP36_CNT; + volatile U_FUNC_SEL_LUMA_QP37_CNT FUNC_SEL_LUMA_QP37_CNT; + volatile U_FUNC_SEL_LUMA_QP38_CNT FUNC_SEL_LUMA_QP38_CNT; + volatile U_FUNC_SEL_LUMA_QP39_CNT FUNC_SEL_LUMA_QP39_CNT; + volatile U_FUNC_SEL_LUMA_QP40_CNT FUNC_SEL_LUMA_QP40_CNT; + volatile U_FUNC_SEL_LUMA_QP41_CNT FUNC_SEL_LUMA_QP41_CNT; + volatile U_FUNC_SEL_LUMA_QP42_CNT FUNC_SEL_LUMA_QP42_CNT; + volatile U_FUNC_SEL_LUMA_QP43_CNT FUNC_SEL_LUMA_QP43_CNT; + volatile U_FUNC_SEL_LUMA_QP44_CNT FUNC_SEL_LUMA_QP44_CNT; + volatile U_FUNC_SEL_LUMA_QP45_CNT FUNC_SEL_LUMA_QP45_CNT; + volatile U_FUNC_SEL_LUMA_QP46_CNT FUNC_SEL_LUMA_QP46_CNT; + volatile U_FUNC_SEL_LUMA_QP47_CNT FUNC_SEL_LUMA_QP47_CNT; + volatile U_FUNC_SEL_LUMA_QP48_CNT FUNC_SEL_LUMA_QP48_CNT; + volatile U_FUNC_SEL_LUMA_QP49_CNT FUNC_SEL_LUMA_QP49_CNT; + volatile U_FUNC_SEL_LUMA_QP50_CNT FUNC_SEL_LUMA_QP50_CNT; + volatile U_FUNC_SEL_LUMA_QP51_CNT FUNC_SEL_LUMA_QP51_CNT; + volatile unsigned int RESERVED3_FUNC_SEL[140]; + volatile unsigned int FUNC_SAO_MSE_SUM; + volatile U_FUNC_SAO_MSE_CNT FUNC_SAO_MSE_CNT; + volatile U_FUNC_SAO_MSE_MAX FUNC_SAO_MSE_MAX; + volatile unsigned int FUNC_SAO_SSD_AERA0_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA1_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA2_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA3_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA4_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA5_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA6_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA7_SUM; + volatile unsigned int RESERVED_FUNC_0SAO[8]; + volatile U_FUNC_SAO_OFF_NUM FUNC_SAO_OFF_NUM; + volatile U_FUNC_SAO_LCU_CNT FUNC_SAO_LCU_CNT; + volatile unsigned int RESERVED_FUNC_1SAO[11]; + volatile unsigned int RESERVED_FUNC[48]; + volatile unsigned int RESERVED_MIDDLE[4096]; + #if 1 //256KB SPACE + volatile U_MMU_PRE_GLB_SCR MMU_PRE_GLB_SCR; //8000 + volatile unsigned int MMU_PRE_RESERVED_0[3]; + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_END; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_END; + volatile unsigned int MMU_PRE_PMEST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEST_ADDR_END; + volatile unsigned int MMU_PRE_PMELD_ADDR_STR; + volatile unsigned int MMU_PRE_PMELD_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_END; + volatile unsigned int MST_PRE_RESERVED_1[2]; + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_END; + volatile unsigned int MMU_PRE_QPGLD_ADDR_STR; + volatile unsigned int MMU_PRE_QPGLD_ADDR_END; + volatile unsigned int MMU_PRE_REC_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_YH_ADDR_END; + volatile unsigned int MMU_PRE_REC_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_CH_ADDR_END; + volatile unsigned int MMU_PRE_REC_YADDR_STR; + volatile unsigned int MMU_PRE_REC_YADDR_END; + volatile unsigned int MMU_PRE_REC_CADDR_STR; + volatile unsigned int MMU_PRE_REC_CADDR_END; + volatile unsigned int MMU_PRE_REF_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_YH_ADDR_END; + volatile unsigned int MMU_PRE_REF_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_CH_ADDR_END; + volatile unsigned int MMU_PRE_REF_YADDR_STR; + volatile unsigned int MMU_PRE_REF_YADDR_END; + volatile unsigned int MMU_PRE_REF_CADDR_STR; + volatile unsigned int MMU_PRE_REF_CADDR_END; + volatile unsigned int MMU_PRE_SRC_YHADDR_STR; + volatile unsigned int MMU_PRE_SRC_YHADDR_END; + volatile unsigned int MMU_PRE_SRC_CHADDR_STR; + volatile unsigned int MMU_PRE_SRC_CHADDR_END; + volatile unsigned int MMU_PRE_SRC_YADDR_STR; + volatile unsigned int MMU_PRE_SRC_YADDR_END; + volatile unsigned int MMU_PRE_SRC_CADDR_STR; + volatile unsigned int MMU_PRE_SRC_CADDR_END; + volatile unsigned int MMU_PRE_SRC_VADDR_STR; + volatile unsigned int MMU_PRE_SRC_VADDR_END; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_STR; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_END; + volatile unsigned int MMU_PRE_PPS_ADDR_STR; + volatile unsigned int MMU_PRE_PPS_ADDR_END; + volatile unsigned int MMU_PRE_STRMADDR0_STR; + volatile unsigned int MMU_PRE_STRMADDR0_END; + volatile unsigned int MMU_PRE_STRMADDR1_STR; + volatile unsigned int MMU_PRE_STRMADDR1_END; + volatile unsigned int MMU_PRE_STRMADDR2_STR; + volatile unsigned int MMU_PRE_STRMADDR2_END; + volatile unsigned int MMU_PRE_STRMADDR3_STR; + volatile unsigned int MMU_PRE_STRMADDR3_END; + volatile unsigned int MMU_PRE_STRMADDR4_STR; + volatile unsigned int MMU_PRE_STRMADDR4_END; + volatile unsigned int MMU_PRE_STRMADDR5_STR; + volatile unsigned int MMU_PRE_STRMADDR5_END; + volatile unsigned int MMU_PRE_STRMADDR6_STR; + volatile unsigned int MMU_PRE_STRMADDR6_END; + volatile unsigned int MMU_PRE_STRMADDR7_STR; + volatile unsigned int MMU_PRE_STRMADDR7_END; + volatile unsigned int MMU_PRE_STRMADDR8_STR; + volatile unsigned int MMU_PRE_STRMADDR8_END; + volatile unsigned int MMU_PRE_STRMADDR9_STR; + volatile unsigned int MMU_PRE_STRMADDR9_END; + volatile unsigned int MMU_PRE_STRMADDR10_STR; + volatile unsigned int MMU_PRE_STRMADDR10_END; + volatile unsigned int MMU_PRE_STRMADDR11_STR; + volatile unsigned int MMU_PRE_STRMADDR11_END; + volatile unsigned int MMU_PRE_STRMADDR12_STR; + volatile unsigned int MMU_PRE_STRMADDR12_END; + volatile unsigned int MMU_PRE_STRMADDR13_STR; + volatile unsigned int MMU_PRE_STRMADDR13_END; + volatile unsigned int MMU_PRE_STRMADDR14_STR; + volatile unsigned int MMU_PRE_STRMADDR14_END; + volatile unsigned int MMU_PRE_STRMADDR15_STR; + volatile unsigned int MMU_PRE_STRMADDR15_END; + volatile U_MMU_PRE_DFX_ARERR_FLAG MMU_PRE_DFX_ARERR_FLAG; + volatile U_MMU_PRE_DFX_ARERR_ID MMU_PRE_DFX_ARERR_ID; + volatile unsigned int MMU_PRE_DFX_ARERR_ADDR; + volatile unsigned int MST_PRE_RESERVED_2; + volatile U_MMU_PRE_DFX_AWERR_FLAG MMU_PRE_DFX_AWERR_FLAG; + volatile U_MMU_PRE_DFX_AWERR_ID MMU_PRE_DFX_AWERR_ID; + volatile unsigned int MMU_PRE_DFX_AWERR_ADDR; + volatile unsigned int MMU_PRE_RESERVED_3[933]; + volatile U_AXIDFX_ERR AXIDFX_ERR; //9000 + volatile unsigned int RESERVED_1[3]; + volatile U_AXIDFX_AR_R_CNT AXIDFX_AR_R_CNT; + volatile U_AXIDFX_AW_W_CNT AXIDFX_AW_W_CNT; + volatile U_AXIDFX_AW_B_CNT AXIDFX_AW_B_CNT; + volatile unsigned int RESERVED_2; + volatile U_AXIDFX_AR_R_ID_ERR AXIDFX_AR_R_ID_ERR; + volatile U_AXIDFX_ERR_ARID AXIDFX_ERR_ARID; + volatile U_AXIDFX_ERR_RID AXIDFX_ERR_RID; + volatile unsigned int RESERVED_3; + volatile U_AXIDFX_AW_W_B_ID_ERR AXIDFX_AW_W_B_ID_ERR; + volatile U_AXIDFX_ERR_AWID AXIDFX_ERR_AWID; + volatile U_AXIDFX_ERR_WID AXIDFX_ERR_WID; + volatile U_AXIDFX_ERR_BID AXIDFX_ERR_BID; + volatile U_AXIDFX_ARID_TX_0ERR AXIDFX_ARID_TX_0ERR; + volatile U_AXIDFX_ARID_TX_1ERR AXIDFX_ARID_TX_1ERR; + volatile U_AXIDFX_ARID_TX_2ERR AXIDFX_ARID_TX_2ERR; + volatile unsigned int RESERVED_4; + volatile U_AXIDFX_RID_RX_0ERR AXIDFX_RID_RX_0ERR; + volatile U_AXIDFX_RID_RX_1ERR AXIDFX_RID_RX_1ERR; + volatile U_AXIDFX_RID_RX_2ERR AXIDFX_RID_RX_2ERR; + volatile unsigned int RESERVED_5; + volatile U_AXIDFX_ARID_RX_0ERR AXIDFX_ARID_RX_0ERR; + volatile U_AXIDFX_BID_RX_ERR AXIDFX_BID_RX_ERR; + volatile unsigned int RESERVED_6[2]; + volatile U_AXIDFX_ARID_LEN_0ERR AXIDFX_ARID_LEN_0ERR; + volatile U_AXIDFX_ARID_LEN_1ERR AXIDFX_ARID_LEN_1ERR; + volatile U_AXIDFX_ARID_LEN_2ERR AXIDFX_ARID_LEN_2ERR; + volatile unsigned int RESERVED_7; + volatile unsigned int AXIDFX_AWLEN_CNT; + volatile unsigned int AXIDFX_WLEN_CNT; + volatile unsigned int RESERVED_8[2]; + volatile U_AXIDFX_RESP_ERR AXIDFX_RESP_ERR; + volatile U_AXIDFX_ERR_RESP AXIDFX_ERR_RESP; + volatile U_AXIDFX_LEN_ERR AXIDFX_LEN_ERR; + volatile U_AXIDFX_ERR_LEN AXIDFX_ERR_LEN; + volatile unsigned int AXIDFX_0RID_FLAG; + volatile unsigned int AXIDFX_1RID_FLAG; + volatile U_AXIDFX_2RID_FLAG AXIDFX_2RID_FLAG; + volatile U_AXIDFX_WID_FLAG AXIDFX_WID_FLAG; + volatile U_AXIDFX_AXI_ST AXIDFX_AXI_ST; + volatile unsigned int RESERVED_9[19]; + volatile U_AXIDFX_SOFT_RST_REQ AXIDFX_SOFT_RST_REQ; + volatile U_AXIDFX_SOFT_RST_ACK AXIDFX_SOFT_RST_ACK; + volatile unsigned int RESERVED_11[2]; + volatile U_AXIDFX_SOFT_RST_FORCE_REQ_ACK AXIDFX_SOFT_RST_FORCE_REQ_ACK; + volatile unsigned int AXIDFX_SOFT_RST_STATE0; + volatile unsigned int AXIDFX_SOFT_RST_STATE1; + volatile unsigned int RESERVED_12[7097]; + volatile U_SMMU_MSTR_GLB_BYPASS SMMU_MSTR_GLB_BYPASS; //30000 + volatile U_SMMU_MSTR_DEBUG_MODE SMMU_MSTR_DEBUG_MODE; + volatile U_SMMU_MSTR_MEM_CTRL SMMU_MSTR_MEM_CTRL; + volatile U_SMMU_MSTR_CLK_EN SMMU_MSTR_CLK_EN; + volatile unsigned int SMMU_MSTR_END_REQ_0; + volatile unsigned int SMMU_MSTR_END_REQ_1; + volatile U_SMMU_MSTR_END_REQ_2 SMMU_MSTR_END_REQ_2; + volatile unsigned int SMMU_MSTR_END_ACK_0; + volatile unsigned int SMMU_MSTR_END_ACK_1; + volatile U_SMMU_MSTR_END_ACK_2 SMMU_MSTR_END_ACK_2; + volatile unsigned int SMMU_MSTR_SMRX_START_0; + volatile unsigned int SMMU_MSTR_SMRX_START_1; + volatile U_SMMU_MSTR_SMRX_START_2 SMMU_MSTR_SMRX_START_2; + volatile U_SMMU_MSTR_INPT_SEL SMMU_MSTR_INPT_SEL; + volatile unsigned int SMMU_MSTR_RESERVED_0[2]; + volatile U_SMMU_MSTR_INTMASK SMMU_MSTR_INTMASK; + volatile U_SMMU_MSTR_INTRAW SMMU_MSTR_INTRAW; + volatile U_SMMU_MSTR_INTSTAT SMMU_MSTR_INTSTAT; + volatile U_SMMU_MSTR_INTCLR SMMU_MSTR_INTCLR; + volatile U_SMMU_MSTR_DBG_0 SMMU_MSTR_DBG_0; + volatile unsigned int SMMU_MSTR_DBG_1; + volatile U_SMMU_MSTR_DBG_2 SMMU_MSTR_DBG_2; + volatile unsigned int SMMU_MSTR_DBG_3; + volatile U_SMMU_MSTR_DBG_4 SMMU_MSTR_DBG_4; + volatile unsigned int SMMU_MSTR_DBG_5; + volatile unsigned int SMMU_MSTR_RESERVED_1[2]; + volatile U_SMMU_MSTR_DBG_PORT_IN_0 SMMU_MSTR_DBG_PORT_IN_0; + volatile unsigned int SMMU_MSTR_DBG_PORT_IN_1; + volatile unsigned int SMMU_MSTR_DBG_PORT_OUT; + volatile unsigned int SMMU_MSTR_RESERVED_2[33]; + volatile U_SMMU_MSTR_SMRX_0 SMMU_MSTR_SMRX_0[88]; + volatile U_SMMU_MSTR_SMRX_1 SMMU_MSTR_SMRX_1[88]; + volatile U_SMMU_MSTR_SMRX_2 SMMU_MSTR_SMRX_2[144]; + volatile unsigned int RD_CMD_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_MISS_CNT[88]; + volatile unsigned int RD_DATA_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_CASE_CNT[6]; + volatile U_RD_CMD_TRANS_LATENCY RD_CMD_TRANS_LATENCY[50]; + volatile unsigned int WR_CMD_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_MISS_CNT[88]; + volatile unsigned int WR_DATA_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_CASE_CNT[6]; + volatile U_WR_CMD_TRANS_LATENCY WR_CMD_TRANS_LATENCY[50]; + volatile unsigned int RESERVED_MSTR_RESERVED_4[15360]; + volatile U_SMMU_SCR SMMU_SCR; //40000 + volatile U_SMMU_MEMCTRL SMMU_MEMCTRL; + volatile U_SMMU_LP_CTRL SMMU_LP_CTRL; + volatile U_SMMU_PRESS_REMAP SMMU_PRESS_REMAP; + volatile U_SMMU_INTMASK_NS SMMU_INTMASK_NS; + volatile U_SMMU_INTRAW_NS SMMU_INTRAW_NS; + volatile U_SMMU_INTSTAT_NS SMMU_INTSTAT_NS; + volatile U_SMMU_INTCLR_NS SMMU_INTCLR_NS; + volatile U_SMMU_SMRX_NS SMMU_SMRX_NS[116]; + volatile unsigned int SMMU_RLD_EN0_NS; + volatile unsigned int SMMU_RLD_EN1_NS; + volatile U_SMMU_RLD_EN2_NS SMMU_RLD_EN2_NS[2]; + volatile U_SMMU_CB_SCTRL SMMU_CB_SCTRL; + volatile unsigned int SMMU_CB_TTBR0; + volatile unsigned int SMMU_CB_TTBR1; + volatile U_SMMU_CB_TTBCR SMMU_CB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_NS SMMU_OFFSET_ADDR_NS; + volatile U_SMMU_SCACHEI_ALL SMMU_SCACHEI_ALL; + volatile U_SMMU_SCACHEI_L1 SMMU_SCACHEI_L1; + volatile U_SMMU_SCACHEI_L2L3 SMMU_SCACHEI_L2L3; + volatile U_SMMU_FAMA_CTRL0_NS SMMU_FAMA_CTRL0_NS; + volatile U_SMMU_FAMA_CTRL1_NS SMMU_FAMA_CTRL1_NS[55]; + volatile U_SMMU_ADDR_MSB SMMU_ADDR_MSB; + volatile unsigned int SMMU_ERR_RDADDR; + volatile unsigned int SMMU_ERR_WRADDR[2]; + volatile unsigned int SMMU_FAULT_ADDR_TCU; + volatile U_SMMU_FAULT_ID_TCU SMMU_FAULT_ID_TCU[3]; + volatile unsigned int SMMU_FAULT_ADDR_TBUX; + volatile U_SMMU_FAULT_ID_TBUX SMMU_FAULT_ID_TBUX; + volatile U_SMMU_FAULT_INFOX SMMU_FAULT_INFOX[22]; + volatile U_SMMU_DBGRPTR_TLB SMMU_DBGRPTR_TLB; + volatile U_SMMU_DBGRDATA_TLB SMMU_DBGRDATA_TLB; + volatile U_SMMU_DBGRPTR_CACHE SMMU_DBGRPTR_CACHE; + volatile U_SMMU_DBGRDATA0_CACHE SMMU_DBGRDATA0_CACHE; + volatile U_SMMU_DBGRDATA1_CACHE SMMU_DBGRDATA1_CACHE; + volatile U_SMMU_DBGAXI_CTRL SMMU_DBGAXI_CTRL; + volatile unsigned int SMMU_OVA_ADDR; + volatile U_SMMU_OPA_ADDR SMMU_OPA_ADDR; + volatile U_SMMU_OVA_CTRL SMMU_OVA_CTRL; + volatile unsigned int SMMU_OPREF_ADDR; + volatile U_SMMU_OPREF_CTRL SMMU_OPREF_CTRL; + volatile unsigned int SMMU_OPREF_CNT[85]; + volatile U_SMMU_SMRX_S SMMU_SMRX_S[124]; + volatile unsigned int SMMU_RLD_EN0_S; + volatile unsigned int SMMU_RLD_EN1_S; + volatile U_SMMU_RLD_EN2_S SMMU_RLD_EN2_S[2]; + volatile U_SMMU_INTMAS_S SMMU_INTMAS_S; + volatile U_SMMU_INTRAW_S SMMU_INTRAW_S; + volatile U_SMMU_INTSTAT_S SMMU_INTSTAT_S; + volatile U_SMMU_INTCLR_S SMMU_INTCLR_S; + volatile U_SMMU_SCR_S SMMU_SCR_S; + volatile U_SMMU_SCB_SCTRL SMMU_SCB_SCTRL; + volatile unsigned int SMMU_SCB_TTBR; + volatile U_SMMU_SCB_TTBCR SMMU_SCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_S SMMU_OFFSET_ADDR_S; + volatile U_SMMU_FAMA_CTRL0_S SMMU_FAMA_CTRL0_S; + volatile U_SMMU_FAMA_CTRL1_S SMMU_FAMA_CTRL1_S; + volatile U_SMMU_DBGRPTR_TLB_S SMMU_DBGRPTR_TLB_S; + volatile U_SMMU_DBGRPTR_CACHE_S SMMU_DBGRPTR_CACHE_S; + volatile U_SMMU_OVERRIDE_CTRL_S SMMU_OVERRIDE_CTRL_S[15923]; + volatile U_SMMU_SMRX_P SMMU_SMRX_P[124]; + volatile unsigned int SMMU_RLD_EN0_P; + volatile unsigned int SMMU_RLD_EN1_P; + volatile U_SMMU_RLD_EN2_P SMMU_RLD_EN2_P[2]; + volatile U_SMMU_INTMAS_P SMMU_INTMAS_P; + volatile U_SMMU_INTRAW_P SMMU_INTRAW_P; + volatile U_SMMU_INTSTAT_P SMMU_INTSTAT_P; + volatile U_SMMU_INTCLR_P SMMU_INTCLR_P; + volatile U_SMMU_SCR_P SMMU_SCR_P; + volatile U_SMMU_PCB_SCTRL SMMU_PCB_SCTRL; + volatile unsigned int SMMU_PCB_TTBR; + volatile U_SMMU_PCB_TTBCR SMMU_PCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_P SMMU_OFFSET_ADDR_P; + volatile U_SMMU_FAMA_CTRL0_P SMMU_FAMA_CTRL0_P; + volatile U_SMMU_FAMA_CTRL1_P SMMU_FAMA_CTRL1_P; + #else //128KB SPACE + volatile U_MMU_PRE_GLB_SCR MMU_PRE_GLB_SCR; //8000 + volatile unsigned int MMU_PRE_RESERVED_0[3]; + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_END; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_END; + volatile unsigned int MMU_PRE_PMEST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEST_ADDR_END; + volatile unsigned int MMU_PRE_PMELD_ADDR_STR; + volatile unsigned int MMU_PRE_PMELD_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_END; + volatile unsigned int MST_PRE_RESERVED_1[2]; + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_END; + volatile unsigned int MMU_PRE_QPGLD_ADDR_STR; + volatile unsigned int MMU_PRE_QPGLD_ADDR_END; + volatile unsigned int MMU_PRE_REC_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_YH_ADDR_END; + volatile unsigned int MMU_PRE_REC_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_CH_ADDR_END; + volatile unsigned int MMU_PRE_REC_YADDR_STR; + volatile unsigned int MMU_PRE_REC_YADDR_END; + volatile unsigned int MMU_PRE_REC_CADDR_STR; + volatile unsigned int MMU_PRE_REC_CADDR_END; + volatile unsigned int MMU_PRE_REF_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_YH_ADDR_END; + volatile unsigned int MMU_PRE_REF_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_CH_ADDR_END; + volatile unsigned int MMU_PRE_REF_YADDR_STR; + volatile unsigned int MMU_PRE_REF_YADDR_END; + volatile unsigned int MMU_PRE_REF_CADDR_STR; + volatile unsigned int MMU_PRE_REF_CADDR_END; + volatile unsigned int MMU_PRE_SRC_YHADDR_STR; + volatile unsigned int MMU_PRE_SRC_YHADDR_END; + volatile unsigned int MMU_PRE_SRC_CHADDR_STR; + volatile unsigned int MMU_PRE_SRC_CHADDR_END; + volatile unsigned int MMU_PRE_SRC_YADDR_STR; + volatile unsigned int MMU_PRE_SRC_YADDR_END; + volatile unsigned int MMU_PRE_SRC_CADDR_STR; + volatile unsigned int MMU_PRE_SRC_CADDR_END; + volatile unsigned int MMU_PRE_SRC_VADDR_STR; + volatile unsigned int MMU_PRE_SRC_VADDR_END; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_STR; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_END; + volatile unsigned int MMU_PRE_PPS_ADDR_STR; + volatile unsigned int MMU_PRE_PPS_ADDR_END; + volatile unsigned int MMU_PRE_STRMADDR0_STR; + volatile unsigned int MMU_PRE_STRMADDR0_END; + volatile unsigned int MMU_PRE_STRMADDR1_STR; + volatile unsigned int MMU_PRE_STRMADDR1_END; + volatile unsigned int MMU_PRE_STRMADDR2_STR; + volatile unsigned int MMU_PRE_STRMADDR2_END; + volatile unsigned int MMU_PRE_STRMADDR3_STR; + volatile unsigned int MMU_PRE_STRMADDR3_END; + volatile unsigned int MMU_PRE_STRMADDR4_STR; + volatile unsigned int MMU_PRE_STRMADDR4_END; + volatile unsigned int MMU_PRE_STRMADDR5_STR; + volatile unsigned int MMU_PRE_STRMADDR5_END; + volatile unsigned int MMU_PRE_STRMADDR6_STR; + volatile unsigned int MMU_PRE_STRMADDR6_END; + volatile unsigned int MMU_PRE_STRMADDR7_STR; + volatile unsigned int MMU_PRE_STRMADDR7_END; + volatile unsigned int MMU_PRE_STRMADDR8_STR; + volatile unsigned int MMU_PRE_STRMADDR8_END; + volatile unsigned int MMU_PRE_STRMADDR9_STR; + volatile unsigned int MMU_PRE_STRMADDR9_END; + volatile unsigned int MMU_PRE_STRMADDR10_STR; + volatile unsigned int MMU_PRE_STRMADDR10_END; + volatile unsigned int MMU_PRE_STRMADDR11_STR; + volatile unsigned int MMU_PRE_STRMADDR11_END; + volatile unsigned int MMU_PRE_STRMADDR12_STR; + volatile unsigned int MMU_PRE_STRMADDR12_END; + volatile unsigned int MMU_PRE_STRMADDR13_STR; + volatile unsigned int MMU_PRE_STRMADDR13_END; + volatile unsigned int MMU_PRE_STRMADDR14_STR; + volatile unsigned int MMU_PRE_STRMADDR14_END; + volatile unsigned int MMU_PRE_STRMADDR15_STR; + volatile unsigned int MMU_PRE_STRMADDR15_END; + volatile U_MMU_PRE_DFX_ARERR_FLAG MMU_PRE_DFX_ARERR_FLAG; + volatile U_MMU_PRE_DFX_ARERR_ID MMU_PRE_DFX_ARERR_ID; + volatile unsigned int MMU_PRE_DFX_ARERR_ADDR; + volatile unsigned int MST_PRE_RESERVED_2; + volatile U_MMU_PRE_DFX_AWERR_FLAG MMU_PRE_DFX_AWERR_FLAG; + volatile U_MMU_PRE_DFX_AWERR_ID MMU_PRE_DFX_AWERR_ID; + volatile unsigned int MMU_PRE_DFX_AWERR_ADDR; + volatile unsigned int MMU_PRE_RESERVED_3[933]; + volatile U_AXIDFX_ERR AXIDFX_ERR;//9000 + volatile unsigned int RESERVED_1[3]; + volatile U_AXIDFX_AR_R_CNT AXIDFX_AR_R_CNT; + volatile U_AXIDFX_AW_W_CNT AXIDFX_AW_W_CNT; + volatile U_AXIDFX_AW_B_CNT AXIDFX_AW_B_CNT; + volatile unsigned int RESERVED_2; + volatile U_AXIDFX_AR_R_ID_ERR AXIDFX_AR_R_ID_ERR; + volatile U_AXIDFX_ERR_ARID AXIDFX_ERR_ARID; + volatile U_AXIDFX_ERR_RID AXIDFX_ERR_RID; + volatile unsigned int RESERVED_3; + volatile U_AXIDFX_AW_W_B_ID_ERR AXIDFX_AW_W_B_ID_ERR; + volatile U_AXIDFX_ERR_AWID AXIDFX_ERR_AWID; + volatile U_AXIDFX_ERR_WID AXIDFX_ERR_WID; + volatile U_AXIDFX_ERR_BID AXIDFX_ERR_BID; + volatile U_AXIDFX_ARID_TX_0ERR AXIDFX_ARID_TX_0ERR; + volatile U_AXIDFX_ARID_TX_1ERR AXIDFX_ARID_TX_1ERR; + volatile U_AXIDFX_ARID_TX_2ERR AXIDFX_ARID_TX_2ERR; + volatile unsigned int RESERVED_4; + volatile U_AXIDFX_RID_RX_0ERR AXIDFX_RID_RX_0ERR; + volatile U_AXIDFX_RID_RX_1ERR AXIDFX_RID_RX_1ERR; + volatile U_AXIDFX_RID_RX_2ERR AXIDFX_RID_RX_2ERR; + volatile unsigned int RESERVED_5; + volatile U_AXIDFX_ARID_RX_0ERR AXIDFX_ARID_RX_0ERR; + volatile U_AXIDFX_BID_RX_ERR AXIDFX_BID_RX_ERR; + volatile unsigned int RESERVED_6[2]; + volatile U_AXIDFX_ARID_LEN_0ERR AXIDFX_ARID_LEN_0ERR; + volatile U_AXIDFX_ARID_LEN_1ERR AXIDFX_ARID_LEN_1ERR; + volatile U_AXIDFX_ARID_LEN_2ERR AXIDFX_ARID_LEN_2ERR; + volatile unsigned int RESERVED_7; + volatile unsigned int AXIDFX_AWLEN_CNT; + volatile unsigned int AXIDFX_WLEN_CNT; + volatile unsigned int RESERVED_8[2]; + volatile U_AXIDFX_RESP_ERR AXIDFX_RESP_ERR; + volatile U_AXIDFX_ERR_RESP AXIDFX_ERR_RESP; + volatile U_AXIDFX_LEN_ERR AXIDFX_LEN_ERR; + volatile U_AXIDFX_ERR_LEN AXIDFX_ERR_LEN; + volatile unsigned int AXIDFX_0RID_FLAG; + volatile unsigned int AXIDFX_1RID_FLAG; + volatile U_AXIDFX_2RID_FLAG AXIDFX_2RID_FLAG; + volatile U_AXIDFX_WID_FLAG AXIDFX_WID_FLAG; + volatile U_AXIDFX_AXI_ST AXIDFX_AXI_ST; + volatile unsigned int RESERVED_9[19]; + volatile U_AXIDFX_SOFT_RST_REQ AXIDFX_SOFT_RST_REQ; + volatile U_AXIDFX_SOFT_RST_ACK AXIDFX_SOFT_RST_ACK; + volatile unsigned int RESERVED_11[2]; + volatile U_AXIDFX_SOFT_RST_FORCE_REQ_ACK AXIDFX_SOFT_RST_FORCE_REQ_ACK; + volatile unsigned int AXIDFX_SOFT_RST_STATE0; + volatile unsigned int AXIDFX_SOFT_RST_STATE1; + volatile unsigned int RESERVED_12[57]; + volatile unsigned int VEDU_RESERVED_REGS1[896]; + volatile U_SMMU_MSTR_GLB_BYPASS SMMU_MSTR_GLB_BYPASS; //a000 + volatile U_SMMU_MSTR_DEBUG_MODE SMMU_MSTR_DEBUG_MODE; + volatile U_SMMU_MSTR_MEM_CTRL SMMU_MSTR_MEM_CTRL; + volatile U_SMMU_MSTR_CLK_EN SMMU_MSTR_CLK_EN; + volatile unsigned int SMMU_MSTR_END_REQ_0; + volatile unsigned int SMMU_MSTR_END_REQ_1; + volatile U_SMMU_MSTR_END_REQ_2 SMMU_MSTR_END_REQ_2; + volatile unsigned int SMMU_MSTR_END_ACK_0; + volatile unsigned int SMMU_MSTR_END_ACK_1; + volatile U_SMMU_MSTR_END_ACK_2 SMMU_MSTR_END_ACK_2; + volatile unsigned int SMMU_MSTR_SMRX_START_0; + volatile unsigned int SMMU_MSTR_SMRX_START_1; + volatile U_SMMU_MSTR_SMRX_START_2 SMMU_MSTR_SMRX_START_2; + volatile U_SMMU_MSTR_INPT_SEL SMMU_MSTR_INPT_SEL; + volatile unsigned int SMMU_MSTR_RESERVED_0[2]; + volatile U_SMMU_MSTR_INTMASK SMMU_MSTR_INTMASK; + volatile U_SMMU_MSTR_INTRAW SMMU_MSTR_INTRAW; + volatile U_SMMU_MSTR_INTSTAT SMMU_MSTR_INTSTAT; + volatile U_SMMU_MSTR_INTCLR SMMU_MSTR_INTCLR; + volatile U_SMMU_MSTR_DBG_0 SMMU_MSTR_DBG_0; + volatile unsigned int SMMU_MSTR_DBG_1; + volatile U_SMMU_MSTR_DBG_2 SMMU_MSTR_DBG_2; + volatile unsigned int SMMU_MSTR_DBG_3; + volatile U_SMMU_MSTR_DBG_4 SMMU_MSTR_DBG_4; + volatile unsigned int SMMU_MSTR_DBG_5; + volatile unsigned int SMMU_MSTR_RESERVED_1[2]; + volatile U_SMMU_MSTR_DBG_PORT_IN_0 SMMU_MSTR_DBG_PORT_IN_0; + volatile unsigned int SMMU_MSTR_DBG_PORT_IN_1; + volatile unsigned int SMMU_MSTR_DBG_PORT_OUT; + volatile unsigned int SMMU_MSTR_RESERVED_2[33]; + volatile U_SMMU_MSTR_SMRX_0 SMMU_MSTR_SMRX_0[88]; + volatile U_SMMU_MSTR_SMRX_1 SMMU_MSTR_SMRX_1[88]; + volatile U_SMMU_MSTR_SMRX_2 SMMU_MSTR_SMRX_2[144]; + volatile unsigned int RD_CMD_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_MISS_CNT[88]; + volatile unsigned int RD_DATA_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_CASE_CNT[6]; + volatile U_RD_CMD_TRANS_LATENCY RD_CMD_TRANS_LATENCY[50]; + volatile unsigned int WR_CMD_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_MISS_CNT[88]; + volatile unsigned int WR_DATA_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_CASE_CNT[6]; + volatile U_WR_CMD_TRANS_LATENCY WR_CMD_TRANS_LATENCY[50]; + volatile U_SMMU_SCR SMMU_SCR;//b000 + volatile U_SMMU_MEMCTRL SMMU_MEMCTRL; + volatile U_SMMU_LP_CTRL SMMU_LP_CTRL; + volatile U_SMMU_PRESS_REMAP SMMU_PRESS_REMAP; + volatile U_SMMU_INTMASK_NS SMMU_INTMASK_NS; + volatile U_SMMU_INTRAW_NS SMMU_INTRAW_NS; + volatile U_SMMU_INTSTAT_NS SMMU_INTSTAT_NS; + volatile U_SMMU_INTCLR_NS SMMU_INTCLR_NS; + volatile U_SMMU_SMRX_NS SMMU_SMRX_NS[116]; + volatile unsigned int SMMU_RLD_EN0_NS; + volatile unsigned int SMMU_RLD_EN1_NS; + volatile U_SMMU_RLD_EN2_NS SMMU_RLD_EN2_NS[2]; + volatile U_SMMU_CB_SCTRL SMMU_CB_SCTRL; + volatile unsigned int SMMU_CB_TTBR0; + volatile unsigned int SMMU_CB_TTBR1; + volatile U_SMMU_CB_TTBCR SMMU_CB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_NS SMMU_OFFSET_ADDR_NS; + volatile U_SMMU_SCACHEI_ALL SMMU_SCACHEI_ALL; + volatile U_SMMU_SCACHEI_L1 SMMU_SCACHEI_L1; + volatile U_SMMU_SCACHEI_L2L3 SMMU_SCACHEI_L2L3; + volatile U_SMMU_FAMA_CTRL0_NS SMMU_FAMA_CTRL0_NS; + volatile U_SMMU_FAMA_CTRL1_NS SMMU_FAMA_CTRL1_NS[55]; + volatile U_SMMU_ADDR_MSB SMMU_ADDR_MSB; + volatile unsigned int SMMU_ERR_RDADDR; + volatile unsigned int SMMU_ERR_WRADDR[2]; + volatile unsigned int SMMU_FAULT_ADDR_TCU; + volatile U_SMMU_FAULT_ID_TCU SMMU_FAULT_ID_TCU[3]; + volatile unsigned int SMMU_FAULT_ADDR_TBUX; + volatile U_SMMU_FAULT_ID_TBUX SMMU_FAULT_ID_TBUX; + volatile U_SMMU_FAULT_INFOX SMMU_FAULT_INFOX[22]; + volatile U_SMMU_DBGRPTR_TLB SMMU_DBGRPTR_TLB; + volatile U_SMMU_DBGRDATA_TLB SMMU_DBGRDATA_TLB; + volatile U_SMMU_DBGRPTR_CACHE SMMU_DBGRPTR_CACHE; + volatile U_SMMU_DBGRDATA0_CACHE SMMU_DBGRDATA0_CACHE; + volatile U_SMMU_DBGRDATA1_CACHE SMMU_DBGRDATA1_CACHE; + volatile U_SMMU_DBGAXI_CTRL SMMU_DBGAXI_CTRL; + volatile unsigned int SMMU_OVA_ADDR; + volatile U_SMMU_OPA_ADDR SMMU_OPA_ADDR; + volatile U_SMMU_OVA_CTRL SMMU_OVA_CTRL; + volatile unsigned int SMMU_OPREF_ADDR; + volatile U_SMMU_OPREF_CTRL SMMU_OPREF_CTRL; + volatile unsigned int SMMU_OPREF_CNT[85]; + volatile U_SMMU_SMRX_S SMMU_SMRX_S[124]; + volatile unsigned int SMMU_RLD_EN0_S; + volatile unsigned int SMMU_RLD_EN1_S; + volatile U_SMMU_RLD_EN2_S SMMU_RLD_EN2_S[2]; + volatile U_SMMU_INTMAS_S SMMU_INTMAS_S; + volatile U_SMMU_INTRAW_S SMMU_INTRAW_S; + volatile U_SMMU_INTSTAT_S SMMU_INTSTAT_S; + volatile U_SMMU_INTCLR_S SMMU_INTCLR_S; + volatile U_SMMU_SCR_S SMMU_SCR_S; + volatile U_SMMU_SCB_SCTRL SMMU_SCB_SCTRL; + volatile unsigned int SMMU_SCB_TTBR; + volatile U_SMMU_SCB_TTBCR SMMU_SCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_S SMMU_OFFSET_ADDR_S; + volatile U_SMMU_FAMA_CTRL0_S SMMU_FAMA_CTRL0_S; + volatile U_SMMU_FAMA_CTRL1_S SMMU_FAMA_CTRL1_S; + volatile U_SMMU_DBGRPTR_TLB_S SMMU_DBGRPTR_TLB_S; + volatile U_SMMU_DBGRPTR_CACHE_S SMMU_DBGRPTR_CACHE_S; + volatile U_SMMU_OVERRIDE_CTRL_S SMMU_OVERRIDE_CTRL_S[15923]; + volatile U_SMMU_SMRX_P SMMU_SMRX_P[124]; + volatile unsigned int SMMU_RLD_EN0_P; + volatile unsigned int SMMU_RLD_EN1_P; + volatile U_SMMU_RLD_EN2_P SMMU_RLD_EN2_P[2]; + volatile U_SMMU_INTMAS_P SMMU_INTMAS_P; + volatile U_SMMU_INTRAW_P SMMU_INTRAW_P; + volatile U_SMMU_INTSTAT_P SMMU_INTSTAT_P; + volatile U_SMMU_INTCLR_P SMMU_INTCLR_P; + volatile U_SMMU_SCR_P SMMU_SCR_P; + volatile U_SMMU_PCB_SCTRL SMMU_PCB_SCTRL; + volatile unsigned int SMMU_PCB_TTBR; + volatile U_SMMU_PCB_TTBCR SMMU_PCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_P SMMU_OFFSET_ADDR_P; + volatile U_SMMU_FAMA_CTRL0_P SMMU_FAMA_CTRL0_P; + volatile U_SMMU_FAMA_CTRL1_P SMMU_FAMA_CTRL1_P; + #endif + + +} S_HEVC_AVC_REGS_TYPE; + +typedef struct +{ + volatile U_VEDU_VCPI_INTMASK VEDU_VCPI_INTMASK; + volatile U_VEDU_VCPI_INTCLR VEDU_VCPI_INTCLR; + volatile U_VEDU_VCPI_START VEDU_VCPI_START; + volatile U_VEDU_VCPI_CNTCLR VEDU_VCPI_CNTCLR; + volatile unsigned int VEDU_VCPI_FRAMENO; + volatile U_VEDU_VCPI_BP_POS VEDU_VCPI_BP_POS; + volatile unsigned int VEDU_VCPI_TIMEOUT; + volatile U_VEDU_VCPI_MODE VEDU_VCPI_MODE; + volatile U_VEDU_VCPI_TILE_SIZE VEDU_VCPI_TILE_SIZE; + volatile U_VEDU_VCPI_PICSIZE_PIX VEDU_VCPI_PICSIZE_PIX; + volatile U_VEDU_VCPI_MULTISLC VEDU_VCPI_MULTISLC; + volatile U_VEDU_VCPI_QPCFG VEDU_VCPI_QPCFG; + volatile U_VEDU_VCPI_DBLKCFG VEDU_VCPI_DBLKCFG; + volatile U_VEDU_VCPI_LOW_POWER VEDU_VCPI_LOW_POWER; + volatile U_VEDU_VCPI_OUTSTD VEDU_VCPI_OUTSTD; + volatile U_VEDU_VCPI_TMV_LOAD VEDU_VCPI_TMV_LOAD; + volatile U_VEDU_VCPI_CROSS_TILE_SLC VEDU_VCPI_CROSS_TILE_SLC; + volatile U_VEDU_VCPI_MEM_CTRL VEDU_VCPI_MEM_CTRL; + volatile U_VEDU_VCPI_INTRA_INTER_CU_EN VEDU_VCPI_INTRA_INTER_CU_EN; + volatile U_VEDU_VCPI_VLC_CONFIG VEDU_VCPI_VLC_CONFIG; + volatile U_VEDU_VCPI_PRE_JUDGE_EXT_EN VEDU_VCPI_PRE_JUDGE_EXT_EN; + volatile U_VEDU_VCPI_PRE_JUDGE_COST_THR VEDU_VCPI_PRE_JUDGE_COST_THR; + volatile U_VEDU_VCPI_IBLK_PRE_MV_THR VEDU_VCPI_IBLK_PRE_MV_THR; + volatile U_VEDU_VCPI_PME_PARAM VEDU_VCPI_PME_PARAM; + volatile U_VEDU_VCPI_PIC_STRONG_EN VEDU_VCPI_PIC_STRONG_EN; + volatile U_VEDU_VCPI_REF_FLAG VEDU_VCPI_REF_FLAG; + volatile U_VEDU_VCPI_RC_ENABLE VEDU_VCPI_RC_ENABLE; + volatile U_VEDU_VCPI_PINTRA_THRESH0 VEDU_VCPI_PINTRA_THRESH0; + volatile U_VEDU_VCPI_PINTRA_THRESH1 VEDU_VCPI_PINTRA_THRESH1; + volatile U_VEDU_VCPI_PINTRA_THRESH2 VEDU_VCPI_PINTRA_THRESH2; + volatile U_VEDU_VCPI_I_SLC_INSERT VEDU_VCPI_I_SLC_INSERT; + volatile U_VEDU_VCPI_CLKDIV_ENABLE VEDU_VCPI_CLKDIV_ENABLE; + volatile U_VEDU_VCPI_OSD_ENABLE VEDU_VCPI_OSD_ENABLE; + volatile U_VEDU_VCPI_OSD_POS_0 VEDU_VCPI_OSD_POS_0; + volatile U_VEDU_VCPI_OSD_POS_1 VEDU_VCPI_OSD_POS_1; + volatile U_VEDU_VCPI_OSD_POS_2 VEDU_VCPI_OSD_POS_2; + volatile U_VEDU_VCPI_OSD_POS_3 VEDU_VCPI_OSD_POS_3; + volatile U_VEDU_VCPI_OSD_POS_4 VEDU_VCPI_OSD_POS_4; + volatile U_VEDU_VCPI_OSD_POS_5 VEDU_VCPI_OSD_POS_5; + volatile U_VEDU_VCPI_OSD_POS_6 VEDU_VCPI_OSD_POS_6; + volatile U_VEDU_VCPI_OSD_POS_7 VEDU_VCPI_OSD_POS_7; + volatile U_VEDU_VCPI_OSD_SIZE_0 VEDU_VCPI_OSD_SIZE_0; + volatile U_VEDU_VCPI_OSD_SIZE_1 VEDU_VCPI_OSD_SIZE_1; + volatile U_VEDU_VCPI_OSD_SIZE_2 VEDU_VCPI_OSD_SIZE_2; + volatile U_VEDU_VCPI_OSD_SIZE_3 VEDU_VCPI_OSD_SIZE_3; + volatile U_VEDU_VCPI_OSD_SIZE_4 VEDU_VCPI_OSD_SIZE_4; + volatile U_VEDU_VCPI_OSD_SIZE_5 VEDU_VCPI_OSD_SIZE_5; + volatile U_VEDU_VCPI_OSD_SIZE_6 VEDU_VCPI_OSD_SIZE_6; + volatile U_VEDU_VCPI_OSD_SIZE_7 VEDU_VCPI_OSD_SIZE_7; + volatile U_VEDU_VCPI_OSD_LAYERID VEDU_VCPI_OSD_LAYERID; + volatile U_VEDU_VCPI_OSD_QP0 VEDU_VCPI_OSD_QP0; + volatile U_VEDU_VCPI_OSD_QP1 VEDU_VCPI_OSD_QP1; + volatile U_VEDU_VCPI_SW_L0_SIZE VEDU_VCPI_SW_L0_SIZE; + volatile U_VEDU_VCPI_SW_L1_SIZE VEDU_VCPI_SW_L1_SIZE; + volatile unsigned int VEDU_VCPI_PMEINFO_ST_ADDR; + volatile unsigned int VEDU_VCPI_PMEINFO_LD0_ADDR; + volatile unsigned int VEDU_VCPI_PMEINFO_LD1_ADDR; + volatile unsigned int VEDU_VCPI_QPGLD_INF_ADDR; + volatile unsigned int VEDU_VCPI_TUNLCELL_ADDR; + volatile unsigned int VEDU_VCPI_SRC_YADDR; + volatile unsigned int VEDU_VCPI_SRC_CADDR; + volatile unsigned int VEDU_VCPI_SRC_VADDR; + volatile unsigned int VEDU_VCPI_YH_ADDR; + volatile unsigned int VEDU_VCPI_CH_ADDR; + volatile U_VEDU_VCPI_STRIDE VEDU_VCPI_STRIDE; + volatile unsigned int VEDU_VCPI_REC_YADDR; + volatile unsigned int VEDU_VCPI_REC_CADDR; + volatile U_VEDU_VCPI_REC_STRIDE VEDU_VCPI_REC_STRIDE; + volatile unsigned int VEDU_VCPI_REC_YH_ADDR; + volatile unsigned int VEDU_VCPI_REC_CH_ADDR; + volatile U_VEDU_VCPI_REC_HEAD_STRIDE VEDU_VCPI_REC_HEAD_STRIDE; + volatile unsigned int VEDU_VCPI_REFY_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFC_L0_ADDR; + volatile U_VEDU_VCPI_REF_L0_STRIDE VEDU_VCPI_REF_L0_STRIDE; + volatile unsigned int VEDU_VCPI_REFYH_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFCH_L0_ADDR; + volatile U_VEDU_VCPI_REFH_L0_STRIDE VEDU_VCPI_REFH_L0_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_L0_ADDR; + volatile unsigned int VEDU_VCPI_REFY_L1_ADDR; + volatile unsigned int VEDU_VCPI_REFC_L1_ADDR; + volatile U_VEDU_VCPI_REF_L1_STRIDE VEDU_VCPI_REF_L1_STRIDE; + volatile unsigned int VEDU_VCPI_REFYH_L1_ADDR; + volatile unsigned int VEDU_VCPI_REFCH_L1_ADDR; + volatile U_VEDU_VCPI_REFH_L1_STRIDE VEDU_VCPI_REFH_L1_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_L1_ADDR; + volatile unsigned int VEDU_VCPI_PMEST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_UPST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_MVST_ADDR; + volatile unsigned int VEDU_VCPI_NBI_MVLD_ADDR; + volatile unsigned int VEDU_VCPI_STRMADDR; + volatile unsigned int VEDU_VCPI_SWPTRADDR; + volatile unsigned int VEDU_VCPI_SRPTRADDR; + volatile unsigned int VEDU_VCPI_LLILD_ADDR; + volatile U_VEDU_VCPI_STRFMT VEDU_VCPI_STRFMT; + volatile U_VEDU_VCPI_CROP_START VEDU_VCPI_CROP_START; + volatile U_VEDU_VCPI_CROP_END VEDU_VCPI_CROP_END; + volatile U_VEDU_VCPI_SCALE_PARA VEDU_VCPI_SCALE_PARA; + volatile U_VEDU_VCPI_ORI_PICSIZE VEDU_VCPI_ORI_PICSIZE; + volatile U_VEDU_VCPI_BG_ENABLE VEDU_VCPI_BG_ENABLE; + volatile unsigned int VEDU_VCPI_BGL_ADDR; + volatile unsigned int VEDU_VCPI_BGC_ADDR; + volatile unsigned int VEDU_VCPI_BGINF_ADDR; + volatile U_VEDU_VCPI_BG_STRIDE VEDU_VCPI_BG_STRIDE; + volatile U_VEDU_VCPI_BG_FLT_PARA0 VEDU_VCPI_BG_FLT_PARA0; + volatile U_VEDU_VCPI_BG_FLT_PARA1 VEDU_VCPI_BG_FLT_PARA1; + volatile U_VEDU_VCPI_BG_FLT_PARA2 VEDU_VCPI_BG_FLT_PARA2; + volatile U_VEDU_VCPI_BG_THR0 VEDU_VCPI_BG_THR0; + volatile U_VEDU_VCPI_BG_THR1 VEDU_VCPI_BG_THR1; + volatile U_VEDU_VCPI_MEM_CTRL_T16 VEDU_VCPI_MEM_CTRL_T16; + volatile unsigned int VEDU_VCPI_PMEST_STRIDE; + volatile unsigned int VEDU_VCPI_PMELD_STRIDE; + volatile U_VEDU_VCPI_INTRA32_LOW_POWER VEDU_VCPI_INTRA32_LOW_POWER; + volatile U_VEDU_VCPI_INTRA16_LOW_POWER VEDU_VCPI_INTRA16_LOW_POWER; + volatile U_VEDU_VCPI_INTRA_REDUCE_RDO_NUM VEDU_VCPI_INTRA_REDUCE_RDO_NUM; + volatile unsigned int VEDU_VCPI_DBLK_INFO_ADDR; + volatile U_VEDU_VCPI_NOFORCEZERO VEDU_VCPI_NOFORCEZERO; + volatile U_VEDU_VCPI_INTMASK_S VEDU_VCPI_INTMASK_S; + volatile U_VEDU_VCPI_INTCLR_S VEDU_VCPI_INTCLR_S; + + volatile U_VEDU_VCTRL_ROI_CFG0 VEDU_VCTRL_ROI_CFG0; + volatile U_VEDU_VCTRL_ROI_CFG1 VEDU_VCTRL_ROI_CFG1; + volatile U_VEDU_VCTRL_ROI_CFG2 VEDU_VCTRL_ROI_CFG2; + volatile U_VEDU_VCTRL_ROI_SIZE_0 VEDU_VCTRL_ROI_SIZE_0; + volatile U_VEDU_VCTRL_ROI_SIZE_1 VEDU_VCTRL_ROI_SIZE_1; + volatile U_VEDU_VCTRL_ROI_SIZE_2 VEDU_VCTRL_ROI_SIZE_2; + volatile U_VEDU_VCTRL_ROI_SIZE_3 VEDU_VCTRL_ROI_SIZE_3; + volatile U_VEDU_VCTRL_ROI_SIZE_4 VEDU_VCTRL_ROI_SIZE_4; + volatile U_VEDU_VCTRL_ROI_SIZE_5 VEDU_VCTRL_ROI_SIZE_5; + volatile U_VEDU_VCTRL_ROI_SIZE_6 VEDU_VCTRL_ROI_SIZE_6; + volatile U_VEDU_VCTRL_ROI_SIZE_7 VEDU_VCTRL_ROI_SIZE_7; + volatile U_VEDU_VCTRL_ROI_START_0 VEDU_VCTRL_ROI_START_0; + volatile U_VEDU_VCTRL_ROI_START_1 VEDU_VCTRL_ROI_START_1; + volatile U_VEDU_VCTRL_ROI_START_2 VEDU_VCTRL_ROI_START_2; + volatile U_VEDU_VCTRL_ROI_START_3 VEDU_VCTRL_ROI_START_3; + volatile U_VEDU_VCTRL_ROI_START_4 VEDU_VCTRL_ROI_START_4; + volatile U_VEDU_VCTRL_ROI_START_5 VEDU_VCTRL_ROI_START_5; + volatile U_VEDU_VCTRL_ROI_START_6 VEDU_VCTRL_ROI_START_6; + volatile U_VEDU_VCTRL_ROI_START_7 VEDU_VCTRL_ROI_START_7; + volatile U_VEDU_VCTRL_LCU_TARGET_BIT VEDU_VCTRL_LCU_TARGET_BIT; + volatile U_VEDU_VCTRL_NARROW_THRESHOLD VEDU_VCTRL_NARROW_THRESHOLD; + volatile U_VEDU_VCTRL_LCU_BASELINE VEDU_VCTRL_LCU_BASELINE; + volatile U_VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_COEFF_DENOISE VEDU_VCTRL_NORM_COEFF_DENOISE; + volatile U_VEDU_VCTRL_NORM_ENG_DENOISE VEDU_VCTRL_NORM_ENG_DENOISE; + volatile U_VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_COEFF_DENOISE VEDU_VCTRL_SKIN_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SKIN_ENG_DENOISE VEDU_VCTRL_SKIN_ENG_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_COEFF_DENOISE VEDU_VCTRL_HEDGE_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGE_ENG_DENOISE VEDU_VCTRL_HEDGE_ENG_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE; + volatile U_VEDU_VCTRL_HEDGEMOV_ENG_DENOISE VEDU_VCTRL_HEDGEMOV_ENG_DENOISE; + volatile U_VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_COEFF_DENOISE VEDU_VCTRL_STATIC_COEFF_DENOISE; + volatile U_VEDU_VCTRL_STATIC_ENG_DENOISE VEDU_VCTRL_STATIC_ENG_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_COEFF_DENOISE VEDU_VCTRL_SOBELSTR_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELSTR_ENG_DENOISE VEDU_VCTRL_SOBELSTR_ENG_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE; + volatile U_VEDU_VCTRL_SOBELWEAK_ENG_DENOISE VEDU_VCTRL_SOBELWEAK_ENG_DENOISE; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_0 VEDU_VCTRL_INTRA_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_1 VEDU_VCTRL_INTRA_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_INTRA_RDO_FACTOR_2 VEDU_VCTRL_INTRA_RDO_FACTOR_2; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_0 VEDU_VCTRL_MRG_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_1 VEDU_VCTRL_MRG_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_MRG_RDO_FACTOR_2 VEDU_VCTRL_MRG_RDO_FACTOR_2; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_0 VEDU_VCTRL_FME_RDO_FACTOR_0; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_1 VEDU_VCTRL_FME_RDO_FACTOR_1; + volatile U_VEDU_VCTRL_FME_RDO_FACTOR_2 VEDU_VCTRL_FME_RDO_FACTOR_2; + volatile U_VEDU_CURLD_GCFG VEDU_CURLD_GCFG; + volatile U_VEDU_CURLD_OSD01_ALPHA VEDU_CURLD_OSD01_ALPHA; + volatile U_VEDU_CURLD_OSD23_ALPHA VEDU_CURLD_OSD23_ALPHA; + volatile U_VEDU_CURLD_OSD45_ALPHA VEDU_CURLD_OSD45_ALPHA; + volatile U_VEDU_CURLD_OSD67_ALPHA VEDU_CURLD_OSD67_ALPHA; + volatile U_VEDU_CURLD_OSD_GALPHA0 VEDU_CURLD_OSD_GALPHA0; + volatile U_VEDU_CURLD_OSD_GALPHA1 VEDU_CURLD_OSD_GALPHA1; + volatile unsigned int VEDU_CURLD_OSD0_ADDR; + volatile unsigned int VEDU_CURLD_OSD1_ADDR; + volatile unsigned int VEDU_CURLD_OSD2_ADDR; + volatile unsigned int VEDU_CURLD_OSD3_ADDR; + volatile unsigned int VEDU_CURLD_OSD4_ADDR; + volatile unsigned int VEDU_CURLD_OSD5_ADDR; + volatile unsigned int VEDU_CURLD_OSD6_ADDR; + volatile unsigned int VEDU_CURLD_OSD7_ADDR; + volatile U_VEDU_CURLD_OSD01_STRIDE VEDU_CURLD_OSD01_STRIDE; + volatile U_VEDU_CURLD_OSD23_STRIDE VEDU_CURLD_OSD23_STRIDE; + volatile U_VEDU_CURLD_OSD45_STRIDE VEDU_CURLD_OSD45_STRIDE; + volatile U_VEDU_CURLD_OSD67_STRIDE VEDU_CURLD_OSD67_STRIDE; + volatile U_VEDU_CURLD_CLIP_THR VEDU_CURLD_CLIP_THR; + volatile U_VEDU_CURLD_HOR_FILTER VEDU_CURLD_HOR_FILTER; + volatile U_VEDU_CURLD_VER_FILTER VEDU_CURLD_VER_FILTER; + volatile U_VEDU_CURLD_ARGB_YUV_0COEFF VEDU_CURLD_ARGB_YUV_0COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_1COEFF VEDU_CURLD_ARGB_YUV_1COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_2COEFF VEDU_CURLD_ARGB_YUV_2COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_3COEFF VEDU_CURLD_ARGB_YUV_3COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_4COEFF VEDU_CURLD_ARGB_YUV_4COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_5COEFF VEDU_CURLD_ARGB_YUV_5COEFF; + volatile U_VEDU_CURLD_ARGB_YUV_6COEFF VEDU_CURLD_ARGB_YUV_6COEFF; + volatile U_VEDU_CURLD_ARGB_CLIP VEDU_CURLD_ARGB_CLIP; + volatile U_VEDU_CURLD_NARROW_EN VEDU_CURLD_NARROW_EN; + volatile U_VEDU_CURLD_SRCH_STRIDE VEDU_CURLD_SRCH_STRIDE; + volatile U_VEDU_CURLD_HFBCD VEDU_CURLD_HFBCD; + volatile U_VEDU_PME_SW_ADAPT_EN VEDU_PME_SW_ADAPT_EN; + volatile U_VEDU_PME_SW_THR0 VEDU_PME_SW_THR0; + volatile U_VEDU_PME_SW_THR1 VEDU_PME_SW_THR1; + volatile U_VEDU_PME_SW_THR2 VEDU_PME_SW_THR2; + volatile U_VEDU_PME_SKIP_PRE VEDU_PME_SKIP_PRE; + volatile U_VEDU_PME_TR_WEIGHTX VEDU_PME_TR_WEIGHTX; + volatile U_VEDU_PME_TR_WEIGHTY VEDU_PME_TR_WEIGHTY; + volatile U_VEDU_PME_SR_WEIGHT VEDU_PME_SR_WEIGHT; + volatile U_VEDU_PME_INTRABLK_DET VEDU_PME_INTRABLK_DET; + volatile U_VEDU_PME_INTRABLK_DET_THR VEDU_PME_INTRABLK_DET_THR; + volatile U_VEDU_PME_SKIN_THR VEDU_PME_SKIN_THR; + volatile U_VEDU_PME_INTRA_LOWPOW VEDU_PME_INTRA_LOWPOW; + volatile U_VEDU_PME_IBLK_COST_THR VEDU_PME_IBLK_COST_THR; + volatile U_VEDU_PME_STRONG_EDGE VEDU_PME_STRONG_EDGE; + volatile U_VEDU_PME_LARGE_MOVE_THR VEDU_PME_LARGE_MOVE_THR; + volatile U_VEDU_PME_INTER_STRONG_EDGE VEDU_PME_INTER_STRONG_EDGE; + volatile U_VEDU_PME_NEW_COST VEDU_PME_NEW_COST; + volatile U_VEDU_PME_WINDOW_SIZE0_L0 VEDU_PME_WINDOW_SIZE0_L0; + volatile U_VEDU_PME_WINDOW_SIZE1_L0 VEDU_PME_WINDOW_SIZE1_L0; + volatile U_VEDU_PME_WINDOW_SIZE2_L0 VEDU_PME_WINDOW_SIZE2_L0; + volatile U_VEDU_PME_WINDOW_SIZE3_L0 VEDU_PME_WINDOW_SIZE3_L0; + volatile U_VEDU_PME_WINDOW_SIZE0_L1 VEDU_PME_WINDOW_SIZE0_L1; + volatile U_VEDU_PME_WINDOW_SIZE1_L1 VEDU_PME_WINDOW_SIZE1_L1; + volatile U_VEDU_PME_WINDOW_SIZE2_L1 VEDU_PME_WINDOW_SIZE2_L1; + volatile U_VEDU_PME_WINDOW_SIZE3_L1 VEDU_PME_WINDOW_SIZE3_L1; + volatile U_VEDU_PME_COST_OFFSET VEDU_PME_COST_OFFSET; + volatile U_VEDU_PME_SAFE_CFG VEDU_PME_SAFE_CFG; + volatile U_VEDU_PME_IBLK_REFRESH VEDU_PME_IBLK_REFRESH; + volatile U_VEDU_PME_IBLK_REFRESH_NUM VEDU_PME_IBLK_REFRESH_NUM; + volatile U_VEDU_PME_QPG_RC_THR0 VEDU_PME_QPG_RC_THR0; + volatile U_VEDU_PME_QPG_RC_THR1 VEDU_PME_QPG_RC_THR1; + volatile U_VEDU_PME_LOW_LUMA_THR VEDU_PME_LOW_LUMA_THR; + volatile U_VEDU_PME_PBLK_PRE1 VEDU_PME_PBLK_PRE1; + volatile U_VEDU_PME_CHROMA_FLAT VEDU_PME_CHROMA_FLAT; + volatile U_VEDU_PME_LUMA_FLAT VEDU_PME_LUMA_FLAT; + volatile U_VEDU_PME_MADI_FLAT VEDU_PME_MADI_FLAT; + volatile U_VEDU_PME_SKIP_LARGE_RES VEDU_PME_SKIP_LARGE_RES; + volatile U_VEDU_QPG_MAX_MIN_QP VEDU_QPG_MAX_MIN_QP; + volatile U_VEDU_QPG_ROW_TARGET_BITS VEDU_QPG_ROW_TARGET_BITS; + volatile U_VEDU_QPG_AVERAGE_LCU_BITS VEDU_QPG_AVERAGE_LCU_BITS; + volatile U_VEDU_QPG_LOWLUMA VEDU_QPG_LOWLUMA; + volatile U_VEDU_QPG_HEDGE VEDU_QPG_HEDGE; + volatile U_VEDU_QPG_HEDGE_MOVE VEDU_QPG_HEDGE_MOVE; + volatile U_VEDU_QPG_LARGE_MOVE VEDU_QPG_LARGE_MOVE; + volatile U_VEDU_QPG_SKIN VEDU_QPG_SKIN; + volatile U_VEDU_QPG_INTRA_DET VEDU_QPG_INTRA_DET; + volatile U_VEDU_QPG_H264_SMOOTH VEDU_QPG_H264_SMOOTH; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG0 VEDU_QPG_CU_QP_DELTA_THRESH_REG0; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG1 VEDU_QPG_CU_QP_DELTA_THRESH_REG1; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG2 VEDU_QPG_CU_QP_DELTA_THRESH_REG2; + volatile U_VEDU_QPG_CU_QP_DELTA_THRESH_REG3 VEDU_QPG_CU_QP_DELTA_THRESH_REG3; + volatile U_VEDU_QPG_DELTA_LEVEL VEDU_QPG_DELTA_LEVEL; + volatile U_VEDU_QPG_MADI_SWITCH_THR VEDU_QPG_MADI_SWITCH_THR; + volatile U_VEDU_QPG_CU32_DELTA VEDU_QPG_CU32_DELTA; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG00 VEDU_QPG_QP_LAMBDA_CTRL_REG00; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG01 VEDU_QPG_QP_LAMBDA_CTRL_REG01; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG02 VEDU_QPG_QP_LAMBDA_CTRL_REG02; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG03 VEDU_QPG_QP_LAMBDA_CTRL_REG03; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG04 VEDU_QPG_QP_LAMBDA_CTRL_REG04; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG05 VEDU_QPG_QP_LAMBDA_CTRL_REG05; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG06 VEDU_QPG_QP_LAMBDA_CTRL_REG06; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG07 VEDU_QPG_QP_LAMBDA_CTRL_REG07; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG08 VEDU_QPG_QP_LAMBDA_CTRL_REG08; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG09 VEDU_QPG_QP_LAMBDA_CTRL_REG09; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG10 VEDU_QPG_QP_LAMBDA_CTRL_REG10; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG11 VEDU_QPG_QP_LAMBDA_CTRL_REG11; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG12 VEDU_QPG_QP_LAMBDA_CTRL_REG12; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG13 VEDU_QPG_QP_LAMBDA_CTRL_REG13; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG14 VEDU_QPG_QP_LAMBDA_CTRL_REG14; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG15 VEDU_QPG_QP_LAMBDA_CTRL_REG15; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG16 VEDU_QPG_QP_LAMBDA_CTRL_REG16; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG17 VEDU_QPG_QP_LAMBDA_CTRL_REG17; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG18 VEDU_QPG_QP_LAMBDA_CTRL_REG18; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG19 VEDU_QPG_QP_LAMBDA_CTRL_REG19; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG20 VEDU_QPG_QP_LAMBDA_CTRL_REG20; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG21 VEDU_QPG_QP_LAMBDA_CTRL_REG21; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG22 VEDU_QPG_QP_LAMBDA_CTRL_REG22; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG23 VEDU_QPG_QP_LAMBDA_CTRL_REG23; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG24 VEDU_QPG_QP_LAMBDA_CTRL_REG24; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG25 VEDU_QPG_QP_LAMBDA_CTRL_REG25; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG26 VEDU_QPG_QP_LAMBDA_CTRL_REG26; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG27 VEDU_QPG_QP_LAMBDA_CTRL_REG27; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG28 VEDU_QPG_QP_LAMBDA_CTRL_REG28; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG29 VEDU_QPG_QP_LAMBDA_CTRL_REG29; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG30 VEDU_QPG_QP_LAMBDA_CTRL_REG30; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG31 VEDU_QPG_QP_LAMBDA_CTRL_REG31; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG32 VEDU_QPG_QP_LAMBDA_CTRL_REG32; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG33 VEDU_QPG_QP_LAMBDA_CTRL_REG33; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG34 VEDU_QPG_QP_LAMBDA_CTRL_REG34; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG35 VEDU_QPG_QP_LAMBDA_CTRL_REG35; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG36 VEDU_QPG_QP_LAMBDA_CTRL_REG36; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG37 VEDU_QPG_QP_LAMBDA_CTRL_REG37; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG38 VEDU_QPG_QP_LAMBDA_CTRL_REG38; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG39 VEDU_QPG_QP_LAMBDA_CTRL_REG39; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG40 VEDU_QPG_QP_LAMBDA_CTRL_REG40; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG41 VEDU_QPG_QP_LAMBDA_CTRL_REG41; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG42 VEDU_QPG_QP_LAMBDA_CTRL_REG42; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG43 VEDU_QPG_QP_LAMBDA_CTRL_REG43; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG44 VEDU_QPG_QP_LAMBDA_CTRL_REG44; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG45 VEDU_QPG_QP_LAMBDA_CTRL_REG45; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG46 VEDU_QPG_QP_LAMBDA_CTRL_REG46; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG47 VEDU_QPG_QP_LAMBDA_CTRL_REG47; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG48 VEDU_QPG_QP_LAMBDA_CTRL_REG48; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG49 VEDU_QPG_QP_LAMBDA_CTRL_REG49; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG50 VEDU_QPG_QP_LAMBDA_CTRL_REG50; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG51 VEDU_QPG_QP_LAMBDA_CTRL_REG51; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG52 VEDU_QPG_QP_LAMBDA_CTRL_REG52; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG53 VEDU_QPG_QP_LAMBDA_CTRL_REG53; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG54 VEDU_QPG_QP_LAMBDA_CTRL_REG54; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG55 VEDU_QPG_QP_LAMBDA_CTRL_REG55; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG56 VEDU_QPG_QP_LAMBDA_CTRL_REG56; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG57 VEDU_QPG_QP_LAMBDA_CTRL_REG57; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG58 VEDU_QPG_QP_LAMBDA_CTRL_REG58; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG59 VEDU_QPG_QP_LAMBDA_CTRL_REG59; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG60 VEDU_QPG_QP_LAMBDA_CTRL_REG60; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG61 VEDU_QPG_QP_LAMBDA_CTRL_REG61; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG62 VEDU_QPG_QP_LAMBDA_CTRL_REG62; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG63 VEDU_QPG_QP_LAMBDA_CTRL_REG63; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG64 VEDU_QPG_QP_LAMBDA_CTRL_REG64; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG65 VEDU_QPG_QP_LAMBDA_CTRL_REG65; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG66 VEDU_QPG_QP_LAMBDA_CTRL_REG66; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG67 VEDU_QPG_QP_LAMBDA_CTRL_REG67; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG68 VEDU_QPG_QP_LAMBDA_CTRL_REG68; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG69 VEDU_QPG_QP_LAMBDA_CTRL_REG69; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG70 VEDU_QPG_QP_LAMBDA_CTRL_REG70; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG71 VEDU_QPG_QP_LAMBDA_CTRL_REG71; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG72 VEDU_QPG_QP_LAMBDA_CTRL_REG72; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG73 VEDU_QPG_QP_LAMBDA_CTRL_REG73; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG74 VEDU_QPG_QP_LAMBDA_CTRL_REG74; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG75 VEDU_QPG_QP_LAMBDA_CTRL_REG75; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG76 VEDU_QPG_QP_LAMBDA_CTRL_REG76; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG77 VEDU_QPG_QP_LAMBDA_CTRL_REG77; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG78 VEDU_QPG_QP_LAMBDA_CTRL_REG78; + volatile U_VEDU_QPG_QP_LAMBDA_CTRL_REG79 VEDU_QPG_QP_LAMBDA_CTRL_REG79; + volatile U_VEDU_QPG_LAMBDA_MODE VEDU_QPG_LAMBDA_MODE; + volatile U_VEDU_QPG_QP_RESTRAIN VEDU_QPG_QP_RESTRAIN; + volatile unsigned int VEDU_QPG_CU_MIN_SAD_THRESH_0; + volatile unsigned int VEDU_QPG_CU_MIN_SAD_THRESH_1; + volatile U_VEDU_QPG_CU_MIN_SAD_REG VEDU_QPG_CU_MIN_SAD_REG; + volatile U_VEDU_QPG_SMART_REG VEDU_QPG_SMART_REG; + volatile U_VEDU_QPG_FLAT_REGION VEDU_QPG_FLAT_REGION; + volatile U_VEDU_IME_INTER_MODE VEDU_IME_INTER_MODE; + volatile U_VEDU_IME_RDOCFG VEDU_IME_RDOCFG; + volatile U_VEDU_IME_FME_LPOW_THR VEDU_IME_FME_LPOW_THR; + volatile U_VEDU_IME_LAYER3TO2_THR VEDU_IME_LAYER3TO2_THR; + volatile U_VEDU_IME_LAYER3TO2_THR1 VEDU_IME_LAYER3TO2_THR1; + volatile U_VEDU_IME_LAYER3TO1_THR VEDU_IME_LAYER3TO1_THR; + volatile U_VEDU_IME_LAYER3TO1_THR1 VEDU_IME_LAYER3TO1_THR1; + volatile U_VEDU_FME_BIAS_COST0 VEDU_FME_BIAS_COST0; + volatile U_VEDU_FME_BIAS_COST1 VEDU_FME_BIAS_COST1; + volatile U_VEDU_FME_PU64_LWP VEDU_FME_PU64_LWP; + volatile U_VEDU_MRG_FORCE_ZERO_EN VEDU_MRG_FORCE_ZERO_EN; + volatile U_VEDU_MRG_FORCE_SKIP_EN VEDU_MRG_FORCE_SKIP_EN; + volatile U_VEDU_MRG_BIAS_COST0 VEDU_MRG_BIAS_COST0; + volatile U_VEDU_MRG_BIAS_COST1 VEDU_MRG_BIAS_COST1; + volatile U_VEDU_MRG_ABS_OFFSET0 VEDU_MRG_ABS_OFFSET0; + volatile U_VEDU_MRG_ABS_OFFSET1 VEDU_MRG_ABS_OFFSET1; + volatile U_VEDU_MRG_ADJ_WEIGHT VEDU_MRG_ADJ_WEIGHT; + volatile U_VEDU_INTRA_CFG VEDU_INTRA_CFG; + volatile U_VEDU_INTRA_SMOOTH VEDU_INTRA_SMOOTH; + volatile U_VEDU_INTRA_BIT_WEIGHT VEDU_INTRA_BIT_WEIGHT; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_0 VEDU_INTRA_RDO_COST_OFFSET_0; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_1 VEDU_INTRA_RDO_COST_OFFSET_1; + volatile U_VEDU_INTRA_NO_DC_COST_OFFSET_0 VEDU_INTRA_NO_DC_COST_OFFSET_0; + volatile U_VEDU_INTRA_NO_DC_COST_OFFSET_1 VEDU_INTRA_NO_DC_COST_OFFSET_1; + volatile U_VEDU_INTRA_CHNL4_ANG_0EN VEDU_INTRA_CHNL4_ANG_0EN; + volatile U_VEDU_INTRA_CHNL4_ANG_1EN VEDU_INTRA_CHNL4_ANG_1EN; + volatile U_VEDU_INTRA_CHNL8_ANG_0EN VEDU_INTRA_CHNL8_ANG_0EN; + volatile U_VEDU_INTRA_CHNL8_ANG_1EN VEDU_INTRA_CHNL8_ANG_1EN; + volatile U_VEDU_INTRA_CHNL16_ANG_0EN VEDU_INTRA_CHNL16_ANG_0EN; + volatile U_VEDU_INTRA_CHNL16_ANG_1EN VEDU_INTRA_CHNL16_ANG_1EN; + volatile U_VEDU_INTRA_CHNL32_ANG_0EN VEDU_INTRA_CHNL32_ANG_0EN; + volatile U_VEDU_INTRA_CHNL32_ANG_1EN VEDU_INTRA_CHNL32_ANG_1EN; + volatile U_VEDU_INTRA_RDO_COST_OFFSET_3 VEDU_INTRA_RDO_COST_OFFSET_3; + volatile unsigned int VEDU_PMV_POC_0; + volatile unsigned int VEDU_PMV_POC_1; + volatile unsigned int VEDU_PMV_POC_2; + volatile unsigned int VEDU_PMV_POC_3; + volatile unsigned int VEDU_PMV_POC_4; + volatile unsigned int VEDU_PMV_POC_5; + volatile U_VEDU_PMV_TMV_EN VEDU_PMV_TMV_EN; + volatile U_VEDU_TQITQ_DEADZONE VEDU_TQITQ_DEADZONE; + volatile U_VEDU_SEL_OFFSET_STRENGTH VEDU_SEL_OFFSET_STRENGTH; + volatile U_VEDU_SEL_CU32_DC_AC_TH_OFFSET VEDU_SEL_CU32_DC_AC_TH_OFFSET; + volatile U_VEDU_SEL_CU32_QP_TH VEDU_SEL_CU32_QP_TH; + volatile U_VEDU_SEL_RES_DC_AC_TH VEDU_SEL_RES_DC_AC_TH; + volatile unsigned int VEDU_SAO_SSD_AERA0; + volatile unsigned int VEDU_SAO_SSD_AERA1; + volatile unsigned int VEDU_SAO_SSD_AERA2; + volatile unsigned int VEDU_SAO_SSD_AERA3; + volatile unsigned int VEDU_SAO_SSD_AERA4; + volatile unsigned int VEDU_SAO_SSD_AERA5; + volatile unsigned int VEDU_SAO_SSD_AERA6; + volatile unsigned int VEDU_SAO_SSD_AERA7; + volatile U_VEDU_EMAR_WAIT_TIM_OUT VEDU_EMAR_WAIT_TIM_OUT; + volatile U_VEDU_EMAR_RCH_RPT_TH0 VEDU_EMAR_RCH_RPT_TH0; + volatile U_VEDU_EMAR_RCH_RPT_TH1 VEDU_EMAR_RCH_RPT_TH1; + volatile U_VEDU_EMAR_RCH_RPT_TH2 VEDU_EMAR_RCH_RPT_TH2; + volatile U_VEDU_EMAR_WCH_RPT_TH0 VEDU_EMAR_WCH_RPT_TH0; + volatile U_VEDU_EMAR_WCH_RPT_TH1 VEDU_EMAR_WCH_RPT_TH1; + volatile U_VEDU_EMAR_WCH_RPT_TH2 VEDU_EMAR_WCH_RPT_TH2; + volatile U_VEDU_EMAR_SCRAMBLE_TYPE VEDU_EMAR_SCRAMBLE_TYPE; + volatile unsigned int VEDU_PACK_SYNTAX_CONFIG; + volatile U_VEDU_PACK_CU_PARAMETER VEDU_PACK_CU_PARAMETER; + volatile U_VEDU_PACK_PCM_PARAMETER VEDU_PACK_PCM_PARAMETER; + volatile U_VEDU_PACK_TF_SKIP_FLAG VEDU_PACK_TF_SKIP_FLAG; + volatile U_VEDU_CABAC_GLB_CFG VEDU_CABAC_GLB_CFG; + volatile U_VEDU_CABAC_SLCHDR_SIZE VEDU_CABAC_SLCHDR_SIZE; + volatile U_VEDU_CABAC_SLCHDR_PART1 VEDU_CABAC_SLCHDR_PART1; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG1; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG2; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG3; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG4; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG5; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG6; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG7; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG8; + volatile U_VEDU_CABAC_SLCHDR_SIZE_I VEDU_CABAC_SLCHDR_SIZE_I; + volatile U_VEDU_CABAC_SLCHDR_PART1_I VEDU_CABAC_SLCHDR_PART1_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG1_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG2_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG3_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG4_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG5_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG6_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG7_I; + volatile unsigned int VEDU_CABAC_SLCHDR_PART2_SEG8_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM0; + volatile unsigned int VEDU_VLC_SLCHDRSTRM1; + volatile unsigned int VEDU_VLC_SLCHDRSTRM2; + volatile unsigned int VEDU_VLC_SLCHDRSTRM3; + volatile unsigned int VEDU_VLC_REORDERSTRM0; + volatile unsigned int VEDU_VLC_REORDERSTRM1; + volatile unsigned int VEDU_VLC_MARKINGSTRM0; + volatile unsigned int VEDU_VLC_MARKINGSTRM1; + volatile U_VEDU_VLC_SLCHDRPARA VEDU_VLC_SLCHDRPARA; + volatile U_VEDU_VLC_SVC VEDU_VLC_SVC; + volatile unsigned int VEDU_VLC_SLCHDRSTRM0_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM1_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM2_I; + volatile unsigned int VEDU_VLC_SLCHDRSTRM3_I; + volatile unsigned int VEDU_VLC_REORDERSTRM0_I; + volatile unsigned int VEDU_VLC_REORDERSTRM1_I; + volatile unsigned int VEDU_VLC_MARKINGSTRM0_I; + volatile unsigned int VEDU_VLC_MARKINGSTRM1_I; + volatile U_VEDU_VLC_SLCHDRPARA_I VEDU_VLC_SLCHDRPARA_I; + volatile U_VEDU_VLCST_PTBITS_EN VEDU_VLCST_PTBITS_EN; + volatile unsigned int VEDU_VLCST_PTBITS; + volatile unsigned int VEDU_VLCST_STRMBUFLEN0; + volatile unsigned int VEDU_VLCST_STRMBUFLEN1; + volatile unsigned int VEDU_VLCST_STRMBUFLEN2; + volatile unsigned int VEDU_VLCST_STRMBUFLEN3; + volatile unsigned int VEDU_VLCST_STRMBUFLEN4; + volatile unsigned int VEDU_VLCST_STRMBUFLEN5; + volatile unsigned int VEDU_VLCST_STRMBUFLEN6; + volatile unsigned int VEDU_VLCST_STRMBUFLEN7; + volatile unsigned int VEDU_VLCST_STRMBUFLEN8; + volatile unsigned int VEDU_VLCST_STRMBUFLEN9; + volatile unsigned int VEDU_VLCST_STRMBUFLEN10; + volatile unsigned int VEDU_VLCST_STRMBUFLEN11; + volatile unsigned int VEDU_VLCST_STRMBUFLEN12; + volatile unsigned int VEDU_VLCST_STRMBUFLEN13; + volatile unsigned int VEDU_VLCST_STRMBUFLEN14; + volatile unsigned int VEDU_VLCST_STRMBUFLEN15; + volatile unsigned int VEDU_VLCST_STRMADDR0; + volatile unsigned int VEDU_VLCST_STRMADDR1; + volatile unsigned int VEDU_VLCST_STRMADDR2; + volatile unsigned int VEDU_VLCST_STRMADDR3; + volatile unsigned int VEDU_VLCST_STRMADDR4; + volatile unsigned int VEDU_VLCST_STRMADDR5; + volatile unsigned int VEDU_VLCST_STRMADDR6; + volatile unsigned int VEDU_VLCST_STRMADDR7; + volatile unsigned int VEDU_VLCST_STRMADDR8; + volatile unsigned int VEDU_VLCST_STRMADDR9; + volatile unsigned int VEDU_VLCST_STRMADDR10; + volatile unsigned int VEDU_VLCST_STRMADDR11; + volatile unsigned int VEDU_VLCST_STRMADDR12; + volatile unsigned int VEDU_VLCST_STRMADDR13; + volatile unsigned int VEDU_VLCST_STRMADDR14; + volatile unsigned int VEDU_VLCST_STRMADDR15; + volatile unsigned int VEDU_VLCST_PARA_ADDR; + volatile U_VEDU_VLCST_PARAMETER VEDU_VLCST_PARAMETER; + volatile unsigned int VEDU_VLCST_PARA_DATA0; + volatile unsigned int VEDU_VLCST_PARA_DATA1; + volatile unsigned int VEDU_VLCST_PARA_DATA2; + volatile unsigned int VEDU_VLCST_PARA_DATA3; + volatile unsigned int VEDU_VLCST_PARA_DATA4; + volatile unsigned int VEDU_VLCST_PARA_DATA5; + volatile unsigned int VEDU_VLCST_PARA_DATA6; + volatile unsigned int VEDU_VLCST_PARA_DATA7; + volatile unsigned int VEDU_VLCST_PARA_DATA8; + volatile unsigned int VEDU_VLCST_PARA_DATA9; + volatile unsigned int VEDU_VLCST_PARA_DATA10; + volatile unsigned int VEDU_VLCST_PARA_DATA11; + volatile unsigned int VEDU_VLCST_PARA_DATA12; + volatile unsigned int VEDU_VLCST_PARA_DATA13; + volatile unsigned int VEDU_VLCST_PARA_DATA14; + volatile unsigned int VEDU_VLCST_PARA_DATA15; + volatile unsigned int VEDU_VLCST_PARA_DATA16; + volatile unsigned int VEDU_VLCST_PARA_DATA17; + volatile unsigned int VEDU_VLCST_PARA_DATA18; + volatile unsigned int VEDU_VLCST_PARA_DATA19; + volatile unsigned int VEDU_VLCST_PARA_DATA20; + volatile unsigned int VEDU_VLCST_PARA_DATA21; + volatile unsigned int VEDU_VLCST_PARA_DATA22; + volatile unsigned int VEDU_VLCST_PARA_DATA23; + volatile unsigned int VEDU_VLCST_PARA_DATA24; + volatile unsigned int VEDU_VLCST_PARA_DATA25; + volatile unsigned int VEDU_VLCST_PARA_DATA26; + volatile unsigned int VEDU_VLCST_PARA_DATA27; + volatile unsigned int VEDU_VLCST_PARA_DATA28; + volatile unsigned int VEDU_VLCST_PARA_DATA29; + volatile unsigned int VEDU_VLCST_PARA_DATA30; + volatile unsigned int VEDU_VLCST_PARA_DATA31; + volatile unsigned int VEDU_VLCST_PARA_DATA32; + volatile unsigned int VEDU_VLCST_PARA_DATA33; + volatile unsigned int VEDU_VLCST_PARA_DATA34; + volatile unsigned int VEDU_VLCST_PARA_DATA35; + volatile unsigned int VEDU_VLCST_PARA_DATA36; + volatile unsigned int VEDU_VLCST_PARA_DATA37; + volatile unsigned int VEDU_VLCST_PARA_DATA38; + volatile unsigned int VEDU_VLCST_PARA_DATA39; + volatile unsigned int VEDU_VLCST_PARA_DATA40; + volatile unsigned int VEDU_VLCST_PARA_DATA41; + volatile unsigned int VEDU_VLCST_PARA_DATA42; + volatile unsigned int VEDU_VLCST_PARA_DATA43; + volatile unsigned int VEDU_VLCST_PARA_DATA44; + volatile unsigned int VEDU_VLCST_PARA_DATA45; + volatile unsigned int VEDU_VLCST_PARA_DATA46; + volatile unsigned int VEDU_VLCST_PARA_DATA47; + volatile unsigned int VEDU_PPFD_ST_ADDR0; + volatile unsigned int VEDU_PPFD_ST_ADDR1; + volatile unsigned int VEDU_PPFD_ST_LEN0; + volatile unsigned int VEDU_PPFD_ST_LEN1; + volatile U_VEDU_PPFD_ST_CFG VEDU_PPFD_ST_CFG; + volatile U_VEDU_ENV_CHN VEDU_ENV_CHN; + volatile U_FUNC_VCPI_INTSTAT FUNC_VCPI_INTSTAT; + volatile U_FUNC_VCPI_RAWINT FUNC_VCPI_RAWINT; + volatile unsigned int FUNC_VCPI_VEDU_TIMER; + volatile unsigned int FUNC_VCPI_IDLE_TIMER; + volatile U_FUNC_VCPI_INTSTAT_S FUNC_VCPI_INTSTAT_S; + volatile U_FUNC_VCPI_RAWINT_S FUNC_VCPI_RAWINT_S; + volatile U_FUNC_PME_MADI_SUM FUNC_PME_MADI_SUM; + volatile U_FUNC_PME_MADP_SUM FUNC_PME_MADP_SUM; + volatile U_FUNC_PME_MADI_NUM FUNC_PME_MADI_NUM; + volatile U_FUNC_PME_MADP_NUM FUNC_PME_MADP_NUM; + volatile U_FUNC_BGGEN_BLOCK_COUNT FUNC_BGGEN_BLOCK_COUNT; + volatile U_FUNC_BGGEN_FRAME_BGM_DIST FUNC_BGGEN_FRAME_BGM_DIST; + volatile unsigned int FUNC_CABAC_PIC_STRMSIZE; + volatile unsigned int FUNC_CABAC_BIT_NUM; + volatile unsigned int VLC_SLC_TTBITS; + volatile unsigned int VLC_PIC_TTBITS; + volatile unsigned int FUNC_VLCST_SLC_LEN_CNT; + volatile U_FUNC_VLCST_DSRPTR00 FUNC_VLCST_DSRPTR00; + volatile U_FUNC_VLCST_DSRPTR01 FUNC_VLCST_DSRPTR01; + volatile U_FUNC_VLCST_DSRPTR10 FUNC_VLCST_DSRPTR10; + volatile U_FUNC_VLCST_DSRPTR11 FUNC_VLCST_DSRPTR11; + volatile U_FUNC_VLCST_DSRPTR20 FUNC_VLCST_DSRPTR20; + volatile U_FUNC_VLCST_DSRPTR21 FUNC_VLCST_DSRPTR21; + volatile U_FUNC_VLCST_DSRPTR30 FUNC_VLCST_DSRPTR30; + volatile U_FUNC_VLCST_DSRPTR31 FUNC_VLCST_DSRPTR31; + volatile U_FUNC_VLCST_DSRPTR40 FUNC_VLCST_DSRPTR40; + volatile U_FUNC_VLCST_DSRPTR41 FUNC_VLCST_DSRPTR41; + volatile U_FUNC_VLCST_DSRPTR50 FUNC_VLCST_DSRPTR50; + volatile U_FUNC_VLCST_DSRPTR51 FUNC_VLCST_DSRPTR51; + volatile U_FUNC_VLCST_DSRPTR60 FUNC_VLCST_DSRPTR60; + volatile U_FUNC_VLCST_DSRPTR61 FUNC_VLCST_DSRPTR61; + volatile U_FUNC_VLCST_DSRPTR70 FUNC_VLCST_DSRPTR70; + volatile U_FUNC_VLCST_DSRPTR71 FUNC_VLCST_DSRPTR71; + volatile U_FUNC_VLCST_DSRPTR80 FUNC_VLCST_DSRPTR80; + volatile U_FUNC_VLCST_DSRPTR81 FUNC_VLCST_DSRPTR81; + volatile U_FUNC_VLCST_DSRPTR90 FUNC_VLCST_DSRPTR90; + volatile U_FUNC_VLCST_DSRPTR91 FUNC_VLCST_DSRPTR91; + volatile U_FUNC_VLCST_DSRPTR100 FUNC_VLCST_DSRPTR100; + volatile U_FUNC_VLCST_DSRPTR101 FUNC_VLCST_DSRPTR101; + volatile U_FUNC_VLCST_DSRPTR110 FUNC_VLCST_DSRPTR110; + volatile U_FUNC_VLCST_DSRPTR111 FUNC_VLCST_DSRPTR111; + volatile U_FUNC_VLCST_DSRPTR120 FUNC_VLCST_DSRPTR120; + volatile U_FUNC_VLCST_DSRPTR121 FUNC_VLCST_DSRPTR121; + volatile U_FUNC_VLCST_DSRPTR130 FUNC_VLCST_DSRPTR130; + volatile U_FUNC_VLCST_DSRPTR131 FUNC_VLCST_DSRPTR131; + volatile U_FUNC_VLCST_DSRPTR140 FUNC_VLCST_DSRPTR140; + volatile U_FUNC_VLCST_DSRPTR141 FUNC_VLCST_DSRPTR141; + volatile U_FUNC_VLCST_DSRPTR150 FUNC_VLCST_DSRPTR150; + volatile U_FUNC_VLCST_DSRPTR151 FUNC_VLCST_DSRPTR151; + volatile U_FUNC_SEL_OPT_8X8_CNT FUNC_SEL_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_OPT_8X8_CNT FUNC_SEL_INTRA_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTRA_PCM_OPT_8X8_CNT FUNC_SEL_INTRA_PCM_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_OPT_8X8_CNT FUNC_SEL_INTER_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_8X8_CNT FUNC_SEL_INTER_FME_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_8X8_CNT FUNC_SEL_INTER_MERGE_OPT_8X8_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_8X8_CNT FUNC_SEL_INTER_SKIP_OPT_8X8_CNT; + volatile U_FUNC_SEL_OPT_16X16_CNT FUNC_SEL_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTRA_OPT_16X16_CNT FUNC_SEL_INTRA_OPT_16X16_CNT; + volatile U_FUNC_SEL_OPT_4X4_CNT FUNC_SEL_OPT_4X4_CNT; + volatile unsigned int RESERVED0_FUNC_SEL; + volatile U_FUNC_SEL_INTER_OPT_16X16_CNT FUNC_SEL_INTER_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_16X16_CNT FUNC_SEL_INTER_FME_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_16X16_CNT FUNC_SEL_INTER_MERGE_OPT_16X16_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_16X16_CNT FUNC_SEL_INTER_SKIP_OPT_16X16_CNT; + volatile U_FUNC_SEL_OPT_32X32_CNT FUNC_SEL_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTRA_OPT_32X32_CNT FUNC_SEL_INTRA_OPT_32X32_CNT; + volatile unsigned int RESERVED1_FUNC_SEL; + volatile U_FUNC_SEL_INTER_OPT_32X32_CNT FUNC_SEL_INTER_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_32X32_CNT FUNC_SEL_INTER_FME_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_32X32_CNT FUNC_SEL_INTER_MERGE_OPT_32X32_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_32X32_CNT FUNC_SEL_INTER_SKIP_OPT_32X32_CNT; + volatile U_FUNC_SEL_OPT_64X64_CNT FUNC_SEL_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_FME_OPT_64X64_CNT FUNC_SEL_INTER_FME_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_MERGE_OPT_64X64_CNT FUNC_SEL_INTER_MERGE_OPT_64X64_CNT; + volatile U_FUNC_SEL_INTER_SKIP_OPT_64X64_CNT FUNC_SEL_INTER_SKIP_OPT_64X64_CNT; + volatile U_FUNC_SEL_TOTAL_LUMA_QP FUNC_SEL_TOTAL_LUMA_QP; + volatile U_FUNC_SEL_MAX_MIN_LUMA_QP FUNC_SEL_MAX_MIN_LUMA_QP; + volatile U_FUNC_SEL_LUMA_QP0_CNT FUNC_SEL_LUMA_QP0_CNT; + volatile U_FUNC_SEL_LUMA_QP1_CNT FUNC_SEL_LUMA_QP1_CNT; + volatile U_FUNC_SEL_LUMA_QP2_CNT FUNC_SEL_LUMA_QP2_CNT; + volatile U_FUNC_SEL_LUMA_QP3_CNT FUNC_SEL_LUMA_QP3_CNT; + volatile U_FUNC_SEL_LUMA_QP4_CNT FUNC_SEL_LUMA_QP4_CNT; + volatile U_FUNC_SEL_LUMA_QP5_CNT FUNC_SEL_LUMA_QP5_CNT; + volatile U_FUNC_SEL_LUMA_QP6_CNT FUNC_SEL_LUMA_QP6_CNT; + volatile U_FUNC_SEL_LUMA_QP7_CNT FUNC_SEL_LUMA_QP7_CNT; + volatile U_FUNC_SEL_LUMA_QP8_CNT FUNC_SEL_LUMA_QP8_CNT; + volatile U_FUNC_SEL_LUMA_QP9_CNT FUNC_SEL_LUMA_QP9_CNT; + volatile U_FUNC_SEL_LUMA_QP10_CNT FUNC_SEL_LUMA_QP10_CNT; + volatile U_FUNC_SEL_LUMA_QP11_CNT FUNC_SEL_LUMA_QP11_CNT; + volatile U_FUNC_SEL_LUMA_QP12_CNT FUNC_SEL_LUMA_QP12_CNT; + volatile U_FUNC_SEL_LUMA_QP13_CNT FUNC_SEL_LUMA_QP13_CNT; + volatile U_FUNC_SEL_LUMA_QP14_CNT FUNC_SEL_LUMA_QP14_CNT; + volatile U_FUNC_SEL_LUMA_QP15_CNT FUNC_SEL_LUMA_QP15_CNT; + volatile U_FUNC_SEL_LUMA_QP16_CNT FUNC_SEL_LUMA_QP16_CNT; + volatile U_FUNC_SEL_LUMA_QP17_CNT FUNC_SEL_LUMA_QP17_CNT; + volatile U_FUNC_SEL_LUMA_QP18_CNT FUNC_SEL_LUMA_QP18_CNT; + volatile U_FUNC_SEL_LUMA_QP19_CNT FUNC_SEL_LUMA_QP19_CNT; + volatile U_FUNC_SEL_LUMA_QP20_CNT FUNC_SEL_LUMA_QP20_CNT; + volatile U_FUNC_SEL_LUMA_QP21_CNT FUNC_SEL_LUMA_QP21_CNT; + volatile U_FUNC_SEL_LUMA_QP22_CNT FUNC_SEL_LUMA_QP22_CNT; + volatile U_FUNC_SEL_LUMA_QP23_CNT FUNC_SEL_LUMA_QP23_CNT; + volatile U_FUNC_SEL_LUMA_QP24_CNT FUNC_SEL_LUMA_QP24_CNT; + volatile U_FUNC_SEL_LUMA_QP25_CNT FUNC_SEL_LUMA_QP25_CNT; + volatile U_FUNC_SEL_LUMA_QP26_CNT FUNC_SEL_LUMA_QP26_CNT; + volatile U_FUNC_SEL_LUMA_QP27_CNT FUNC_SEL_LUMA_QP27_CNT; + volatile U_FUNC_SEL_LUMA_QP28_CNT FUNC_SEL_LUMA_QP28_CNT; + volatile U_FUNC_SEL_LUMA_QP29_CNT FUNC_SEL_LUMA_QP29_CNT; + volatile U_FUNC_SEL_LUMA_QP30_CNT FUNC_SEL_LUMA_QP30_CNT; + volatile U_FUNC_SEL_LUMA_QP31_CNT FUNC_SEL_LUMA_QP31_CNT; + volatile U_FUNC_SEL_LUMA_QP32_CNT FUNC_SEL_LUMA_QP32_CNT; + volatile U_FUNC_SEL_LUMA_QP33_CNT FUNC_SEL_LUMA_QP33_CNT; + volatile U_FUNC_SEL_LUMA_QP34_CNT FUNC_SEL_LUMA_QP34_CNT; + volatile U_FUNC_SEL_LUMA_QP35_CNT FUNC_SEL_LUMA_QP35_CNT; + volatile U_FUNC_SEL_LUMA_QP36_CNT FUNC_SEL_LUMA_QP36_CNT; + volatile U_FUNC_SEL_LUMA_QP37_CNT FUNC_SEL_LUMA_QP37_CNT; + volatile U_FUNC_SEL_LUMA_QP38_CNT FUNC_SEL_LUMA_QP38_CNT; + volatile U_FUNC_SEL_LUMA_QP39_CNT FUNC_SEL_LUMA_QP39_CNT; + volatile U_FUNC_SEL_LUMA_QP40_CNT FUNC_SEL_LUMA_QP40_CNT; + volatile U_FUNC_SEL_LUMA_QP41_CNT FUNC_SEL_LUMA_QP41_CNT; + volatile U_FUNC_SEL_LUMA_QP42_CNT FUNC_SEL_LUMA_QP42_CNT; + volatile U_FUNC_SEL_LUMA_QP43_CNT FUNC_SEL_LUMA_QP43_CNT; + volatile U_FUNC_SEL_LUMA_QP44_CNT FUNC_SEL_LUMA_QP44_CNT; + volatile U_FUNC_SEL_LUMA_QP45_CNT FUNC_SEL_LUMA_QP45_CNT; + volatile U_FUNC_SEL_LUMA_QP46_CNT FUNC_SEL_LUMA_QP46_CNT; + volatile U_FUNC_SEL_LUMA_QP47_CNT FUNC_SEL_LUMA_QP47_CNT; + volatile U_FUNC_SEL_LUMA_QP48_CNT FUNC_SEL_LUMA_QP48_CNT; + volatile U_FUNC_SEL_LUMA_QP49_CNT FUNC_SEL_LUMA_QP49_CNT; + volatile U_FUNC_SEL_LUMA_QP50_CNT FUNC_SEL_LUMA_QP50_CNT; + volatile U_FUNC_SEL_LUMA_QP51_CNT FUNC_SEL_LUMA_QP51_CNT; + volatile unsigned int FUNC_SAO_MSE_SUM; + volatile U_FUNC_SAO_MSE_CNT FUNC_SAO_MSE_CNT; + volatile U_FUNC_SAO_MSE_MAX FUNC_SAO_MSE_MAX; + volatile unsigned int FUNC_SAO_SSD_AERA0_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA1_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA2_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA3_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA4_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA5_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA6_SUM; + volatile unsigned int FUNC_SAO_SSD_AERA7_SUM; + volatile U_FUNC_SAO_OFF_NUM FUNC_SAO_OFF_NUM; + volatile U_FUNC_SAO_LCU_CNT FUNC_SAO_LCU_CNT; + + volatile U_MMU_PRE_GLB_SCR MMU_PRE_GLB_SCR; //8000 + + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVST_ADDR_END; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_STR; + volatile unsigned int MMU_PRE_NBI_MVLD_ADDR_END; + volatile unsigned int MMU_PRE_PMEST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEST_ADDR_END; + volatile unsigned int MMU_PRE_PMELD_ADDR_STR; + volatile unsigned int MMU_PRE_PMELD_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOST_ADDR_END; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD0_ADDR_END; + + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_STR; + volatile unsigned int MMU_PRE_PMEINFOLD1_ADDR_END; + volatile unsigned int MMU_PRE_QPGLD_ADDR_STR; + volatile unsigned int MMU_PRE_QPGLD_ADDR_END; + volatile unsigned int MMU_PRE_REC_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_YH_ADDR_END; + volatile unsigned int MMU_PRE_REC_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REC_CH_ADDR_END; + volatile unsigned int MMU_PRE_REC_YADDR_STR; + volatile unsigned int MMU_PRE_REC_YADDR_END; + volatile unsigned int MMU_PRE_REC_CADDR_STR; + volatile unsigned int MMU_PRE_REC_CADDR_END; + volatile unsigned int MMU_PRE_REF_YH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_YH_ADDR_END; + volatile unsigned int MMU_PRE_REF_CH_ADDR_STR; + volatile unsigned int MMU_PRE_REF_CH_ADDR_END; + volatile unsigned int MMU_PRE_REF_YADDR_STR; + volatile unsigned int MMU_PRE_REF_YADDR_END; + volatile unsigned int MMU_PRE_REF_CADDR_STR; + volatile unsigned int MMU_PRE_REF_CADDR_END; + volatile unsigned int MMU_PRE_SRC_YHADDR_STR; + volatile unsigned int MMU_PRE_SRC_YHADDR_END; + volatile unsigned int MMU_PRE_SRC_CHADDR_STR; + volatile unsigned int MMU_PRE_SRC_CHADDR_END; + volatile unsigned int MMU_PRE_SRC_YADDR_STR; + volatile unsigned int MMU_PRE_SRC_YADDR_END; + volatile unsigned int MMU_PRE_SRC_CADDR_STR; + volatile unsigned int MMU_PRE_SRC_CADDR_END; + volatile unsigned int MMU_PRE_SRC_VADDR_STR; + volatile unsigned int MMU_PRE_SRC_VADDR_END; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_STR; + volatile unsigned int MMU_PRE_LOWDLY_ADDR_END; + volatile unsigned int MMU_PRE_PPS_ADDR_STR; + volatile unsigned int MMU_PRE_PPS_ADDR_END; + volatile unsigned int MMU_PRE_STRMADDR0_STR; + volatile unsigned int MMU_PRE_STRMADDR0_END; + volatile unsigned int MMU_PRE_STRMADDR1_STR; + volatile unsigned int MMU_PRE_STRMADDR1_END; + volatile unsigned int MMU_PRE_STRMADDR2_STR; + volatile unsigned int MMU_PRE_STRMADDR2_END; + volatile unsigned int MMU_PRE_STRMADDR3_STR; + volatile unsigned int MMU_PRE_STRMADDR3_END; + volatile unsigned int MMU_PRE_STRMADDR4_STR; + volatile unsigned int MMU_PRE_STRMADDR4_END; + volatile unsigned int MMU_PRE_STRMADDR5_STR; + volatile unsigned int MMU_PRE_STRMADDR5_END; + volatile unsigned int MMU_PRE_STRMADDR6_STR; + volatile unsigned int MMU_PRE_STRMADDR6_END; + volatile unsigned int MMU_PRE_STRMADDR7_STR; + volatile unsigned int MMU_PRE_STRMADDR7_END; + volatile unsigned int MMU_PRE_STRMADDR8_STR; + volatile unsigned int MMU_PRE_STRMADDR8_END; + volatile unsigned int MMU_PRE_STRMADDR9_STR; + volatile unsigned int MMU_PRE_STRMADDR9_END; + volatile unsigned int MMU_PRE_STRMADDR10_STR; + volatile unsigned int MMU_PRE_STRMADDR10_END; + volatile unsigned int MMU_PRE_STRMADDR11_STR; + volatile unsigned int MMU_PRE_STRMADDR11_END; + volatile unsigned int MMU_PRE_STRMADDR12_STR; + volatile unsigned int MMU_PRE_STRMADDR12_END; + volatile unsigned int MMU_PRE_STRMADDR13_STR; + volatile unsigned int MMU_PRE_STRMADDR13_END; + volatile unsigned int MMU_PRE_STRMADDR14_STR; + volatile unsigned int MMU_PRE_STRMADDR14_END; + volatile unsigned int MMU_PRE_STRMADDR15_STR; + volatile unsigned int MMU_PRE_STRMADDR15_END; + volatile U_MMU_PRE_DFX_ARERR_FLAG MMU_PRE_DFX_ARERR_FLAG; + volatile U_MMU_PRE_DFX_ARERR_ID MMU_PRE_DFX_ARERR_ID; + volatile unsigned int MMU_PRE_DFX_ARERR_ADDR; + volatile unsigned int MST_PRE_RESERVED_2; + volatile U_MMU_PRE_DFX_AWERR_FLAG MMU_PRE_DFX_AWERR_FLAG; + volatile U_MMU_PRE_DFX_AWERR_ID MMU_PRE_DFX_AWERR_ID; + volatile unsigned int MMU_PRE_DFX_AWERR_ADDR; + + volatile U_AXIDFX_ERR AXIDFX_ERR; //9000 + + volatile U_AXIDFX_AR_R_CNT AXIDFX_AR_R_CNT; + volatile U_AXIDFX_AW_W_CNT AXIDFX_AW_W_CNT; + volatile U_AXIDFX_AW_B_CNT AXIDFX_AW_B_CNT; + volatile U_AXIDFX_AR_R_ID_ERR AXIDFX_AR_R_ID_ERR; + volatile U_AXIDFX_ERR_ARID AXIDFX_ERR_ARID; + volatile U_AXIDFX_ERR_RID AXIDFX_ERR_RID; + volatile U_AXIDFX_AW_W_B_ID_ERR AXIDFX_AW_W_B_ID_ERR; + volatile U_AXIDFX_ERR_AWID AXIDFX_ERR_AWID; + volatile U_AXIDFX_ERR_WID AXIDFX_ERR_WID; + volatile U_AXIDFX_ERR_BID AXIDFX_ERR_BID; + volatile U_AXIDFX_ARID_TX_0ERR AXIDFX_ARID_TX_0ERR; + volatile U_AXIDFX_ARID_TX_1ERR AXIDFX_ARID_TX_1ERR; + volatile U_AXIDFX_ARID_TX_2ERR AXIDFX_ARID_TX_2ERR; + volatile U_AXIDFX_RID_RX_0ERR AXIDFX_RID_RX_0ERR; + volatile U_AXIDFX_RID_RX_1ERR AXIDFX_RID_RX_1ERR; + volatile U_AXIDFX_RID_RX_2ERR AXIDFX_RID_RX_2ERR; + volatile U_AXIDFX_ARID_RX_0ERR AXIDFX_ARID_RX_0ERR; + volatile U_AXIDFX_BID_RX_ERR AXIDFX_BID_RX_ERR; + volatile U_AXIDFX_ARID_LEN_0ERR AXIDFX_ARID_LEN_0ERR; + volatile U_AXIDFX_ARID_LEN_1ERR AXIDFX_ARID_LEN_1ERR; + volatile U_AXIDFX_ARID_LEN_2ERR AXIDFX_ARID_LEN_2ERR; + volatile unsigned int AXIDFX_AWLEN_CNT; + volatile unsigned int AXIDFX_WLEN_CNT; + volatile U_AXIDFX_RESP_ERR AXIDFX_RESP_ERR; + volatile U_AXIDFX_ERR_RESP AXIDFX_ERR_RESP; + volatile U_AXIDFX_LEN_ERR AXIDFX_LEN_ERR; + volatile U_AXIDFX_ERR_LEN AXIDFX_ERR_LEN; + volatile unsigned int AXIDFX_0RID_FLAG; + volatile unsigned int AXIDFX_1RID_FLAG; + volatile U_AXIDFX_2RID_FLAG AXIDFX_2RID_FLAG; + volatile U_AXIDFX_WID_FLAG AXIDFX_WID_FLAG; + volatile U_AXIDFX_AXI_ST AXIDFX_AXI_ST; + volatile U_AXIDFX_SOFT_RST_REQ AXIDFX_SOFT_RST_REQ; + volatile U_AXIDFX_SOFT_RST_ACK AXIDFX_SOFT_RST_ACK; + volatile U_AXIDFX_SOFT_RST_FORCE_REQ_ACK AXIDFX_SOFT_RST_FORCE_REQ_ACK; + volatile unsigned int AXIDFX_SOFT_RST_STATE0; + volatile unsigned int AXIDFX_SOFT_RST_STATE1; + + volatile U_SMMU_MSTR_GLB_BYPASS SMMU_MSTR_GLB_BYPASS; //30000 + volatile U_SMMU_MSTR_DEBUG_MODE SMMU_MSTR_DEBUG_MODE; + volatile U_SMMU_MSTR_MEM_CTRL SMMU_MSTR_MEM_CTRL; + volatile U_SMMU_MSTR_CLK_EN SMMU_MSTR_CLK_EN; + volatile unsigned int SMMU_MSTR_END_REQ_0; + volatile unsigned int SMMU_MSTR_END_REQ_1; + volatile U_SMMU_MSTR_END_REQ_2 SMMU_MSTR_END_REQ_2; + volatile unsigned int SMMU_MSTR_END_ACK_0; + volatile unsigned int SMMU_MSTR_END_ACK_1; + volatile U_SMMU_MSTR_END_ACK_2 SMMU_MSTR_END_ACK_2; + volatile unsigned int SMMU_MSTR_SMRX_START_0; + volatile unsigned int SMMU_MSTR_SMRX_START_1; + volatile U_SMMU_MSTR_SMRX_START_2 SMMU_MSTR_SMRX_START_2; + volatile U_SMMU_MSTR_INPT_SEL SMMU_MSTR_INPT_SEL; + volatile U_SMMU_MSTR_INTMASK SMMU_MSTR_INTMASK; + volatile U_SMMU_MSTR_INTRAW SMMU_MSTR_INTRAW; + volatile U_SMMU_MSTR_INTSTAT SMMU_MSTR_INTSTAT; + volatile U_SMMU_MSTR_INTCLR SMMU_MSTR_INTCLR; + volatile U_SMMU_MSTR_DBG_0 SMMU_MSTR_DBG_0; + volatile unsigned int SMMU_MSTR_DBG_1; + volatile U_SMMU_MSTR_DBG_2 SMMU_MSTR_DBG_2; + volatile unsigned int SMMU_MSTR_DBG_3; + volatile U_SMMU_MSTR_DBG_4 SMMU_MSTR_DBG_4; + volatile unsigned int SMMU_MSTR_DBG_5; + volatile U_SMMU_MSTR_DBG_PORT_IN_0 SMMU_MSTR_DBG_PORT_IN_0; + volatile unsigned int SMMU_MSTR_DBG_PORT_IN_1; + volatile unsigned int SMMU_MSTR_DBG_PORT_OUT; + volatile U_SMMU_MSTR_SMRX_0 SMMU_MSTR_SMRX_0[88]; + volatile U_SMMU_MSTR_SMRX_1 SMMU_MSTR_SMRX_1[88]; + volatile U_SMMU_MSTR_SMRX_2 SMMU_MSTR_SMRX_2[144]; + volatile unsigned int RD_CMD_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_MISS_CNT[88]; + volatile unsigned int RD_DATA_TOTAL_CNT[88]; + volatile unsigned int RD_CMD_CASE_CNT[6]; + volatile U_RD_CMD_TRANS_LATENCY RD_CMD_TRANS_LATENCY[50]; + volatile unsigned int WR_CMD_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_MISS_CNT[88]; + volatile unsigned int WR_DATA_TOTAL_CNT[88]; + volatile unsigned int WR_CMD_CASE_CNT[6]; + volatile U_WR_CMD_TRANS_LATENCY WR_CMD_TRANS_LATENCY[50]; + volatile U_SMMU_SCR SMMU_SCR; //40000 + volatile U_SMMU_MEMCTRL SMMU_MEMCTRL; + volatile U_SMMU_LP_CTRL SMMU_LP_CTRL; + volatile U_SMMU_PRESS_REMAP SMMU_PRESS_REMAP; + volatile U_SMMU_INTMASK_NS SMMU_INTMASK_NS; + volatile U_SMMU_INTRAW_NS SMMU_INTRAW_NS; + volatile U_SMMU_INTSTAT_NS SMMU_INTSTAT_NS; + volatile U_SMMU_INTCLR_NS SMMU_INTCLR_NS; + volatile U_SMMU_SMRX_NS SMMU_SMRX_NS[88]; + volatile unsigned int SMMU_RLD_EN0_NS; + volatile unsigned int SMMU_RLD_EN1_NS; + volatile U_SMMU_RLD_EN2_NS SMMU_RLD_EN2_NS[2]; + volatile U_SMMU_CB_SCTRL SMMU_CB_SCTRL; + volatile unsigned int SMMU_CB_TTBR0; + volatile unsigned int SMMU_CB_TTBR1; + volatile U_SMMU_CB_TTBCR SMMU_CB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_NS SMMU_OFFSET_ADDR_NS; + volatile U_SMMU_SCACHEI_ALL SMMU_SCACHEI_ALL; + volatile U_SMMU_SCACHEI_L1 SMMU_SCACHEI_L1; + volatile U_SMMU_SCACHEI_L2L3 SMMU_SCACHEI_L2L3; + volatile U_SMMU_FAMA_CTRL0_NS SMMU_FAMA_CTRL0_NS; + volatile U_SMMU_FAMA_CTRL1_NS SMMU_FAMA_CTRL1_NS; + volatile U_SMMU_ADDR_MSB SMMU_ADDR_MSB; + volatile unsigned int SMMU_ERR_RDADDR; + volatile unsigned int SMMU_ERR_WRADDR; + volatile unsigned int SMMU_FAULT_ADDR_TCU; + volatile U_SMMU_FAULT_ID_TCU SMMU_FAULT_ID_TCU[3]; + volatile unsigned int SMMU_FAULT_ADDR_TBUX; + volatile U_SMMU_FAULT_ID_TBUX SMMU_FAULT_ID_TBUX; + volatile U_SMMU_FAULT_INFOX SMMU_FAULT_INFOX[22]; + volatile U_SMMU_DBGRPTR_TLB SMMU_DBGRPTR_TLB; + volatile U_SMMU_DBGRDATA_TLB SMMU_DBGRDATA_TLB; + volatile U_SMMU_DBGRPTR_CACHE SMMU_DBGRPTR_CACHE; + volatile U_SMMU_DBGRDATA0_CACHE SMMU_DBGRDATA0_CACHE; + volatile U_SMMU_DBGRDATA1_CACHE SMMU_DBGRDATA1_CACHE; + volatile U_SMMU_DBGAXI_CTRL SMMU_DBGAXI_CTRL; + volatile unsigned int SMMU_OVA_ADDR; + volatile U_SMMU_OPA_ADDR SMMU_OPA_ADDR; + volatile U_SMMU_OVA_CTRL SMMU_OVA_CTRL; + volatile unsigned int SMMU_OPREF_ADDR; + volatile U_SMMU_OPREF_CTRL SMMU_OPREF_CTRL; + volatile unsigned int SMMU_OPREF_CNT[85]; + volatile U_SMMU_SMRX_S SMMU_SMRX_S[88]; + volatile unsigned int SMMU_RLD_EN0_S; + volatile unsigned int SMMU_RLD_EN1_S; + volatile U_SMMU_RLD_EN2_S SMMU_RLD_EN2_S[2]; + volatile U_SMMU_INTMAS_S SMMU_INTMAS_S; + volatile U_SMMU_INTRAW_S SMMU_INTRAW_S; + volatile U_SMMU_INTSTAT_S SMMU_INTSTAT_S; + volatile U_SMMU_INTCLR_S SMMU_INTCLR_S; + volatile U_SMMU_SCR_S SMMU_SCR_S; + volatile U_SMMU_SCB_SCTRL SMMU_SCB_SCTRL; + volatile unsigned int SMMU_SCB_TTBR; + volatile U_SMMU_SCB_TTBCR SMMU_SCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_S SMMU_OFFSET_ADDR_S; + volatile U_SMMU_FAMA_CTRL0_S SMMU_FAMA_CTRL0_S; + volatile U_SMMU_FAMA_CTRL1_S SMMU_FAMA_CTRL1_S; + volatile U_SMMU_DBGRPTR_TLB_S SMMU_DBGRPTR_TLB_S; + volatile U_SMMU_DBGRPTR_CACHE_S SMMU_DBGRPTR_CACHE_S; + volatile U_SMMU_OVERRIDE_CTRL_S SMMU_OVERRIDE_CTRL_S; + volatile U_SMMU_SMRX_P SMMU_SMRX_P[88]; + volatile unsigned int SMMU_RLD_EN0_P; + volatile unsigned int SMMU_RLD_EN1_P; + volatile U_SMMU_RLD_EN2_P SMMU_RLD_EN2_P[2]; + volatile U_SMMU_INTMAS_P SMMU_INTMAS_P; + volatile U_SMMU_INTRAW_P SMMU_INTRAW_P; + volatile U_SMMU_INTSTAT_P SMMU_INTSTAT_P; + volatile U_SMMU_INTCLR_P SMMU_INTCLR_P; + volatile U_SMMU_SCR_P SMMU_SCR_P; + volatile U_SMMU_PCB_SCTRL SMMU_PCB_SCTRL; + volatile unsigned int SMMU_PCB_TTBR; + volatile U_SMMU_PCB_TTBCR SMMU_PCB_TTBCR; + volatile U_SMMU_OFFSET_ADDR_P SMMU_OFFSET_ADDR_P; + volatile U_SMMU_FAMA_CTRL0_P SMMU_FAMA_CTRL0_P; + volatile U_SMMU_FAMA_CTRL1_P SMMU_FAMA_CTRL1_P; + +} S_HEVC_AVC_REGS_TYPE_CFG; + +#endif diff --git a/drivers/vcodec/venc_hivna/drv_venc.c b/drivers/vcodec/venc_hivna/drv_venc.c new file mode 100755 index 000000000000..d02409e13d51 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc.c @@ -0,0 +1,48 @@ +/* +* Copyright (C), 2004-2050, Hisilicon Tech. Co., Ltd. +* +* File Name : drv_venc.c +* Version : Initial Draft +* Author : Hisilicon multimedia software group +* Created : 2010/04/07 +* Last Modified : +* Description : +* Function List : +* +* History : +* 1.Date : +* Author : j00131665 +* Modification : Created file +*/ +#include "drv_venc.h" +#include "venc_regulator.h" +#include "drv_venc_osal.h" + +unsigned int b_Regular_down_flag = 1; + +/* Íâ±ß¸´Î»vedu, ²¢ÉèÖÃʱÖÓ£¬³·Ïú¸´Î»l00214825 */ +int VENC_DRV_BoardInit(void) +{ + int ret = 0; + HI_DBG_VENC("enter %s()\n", __func__); + + ret = Venc_Regulator_Enable();/*lint !e838 */ + if (ret != 0){ + HI_INFO_VENC("enable regulator failed\n", __func__); + return HI_FAILURE; + } + + HI_DBG_VENC("exit %s ()\n", __func__); + return HI_SUCCESS; +} + +void VENC_DRV_BoardDeinit(void) +{ + HI_DBG_VENC("enter %s ()\n", __func__); + + Venc_Regulator_Disable(); + + HI_DBG_VENC("exit %s ()\n", __func__); +} + + diff --git a/drivers/vcodec/venc_hivna/drv_venc.h b/drivers/vcodec/venc_hivna/drv_venc.h new file mode 100755 index 000000000000..52d95ef73fb4 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc.h @@ -0,0 +1,85 @@ +#ifndef __DRV_VENC_H__ +#define __DRV_VENC_H__ + +#include "Vedu_RegAll_Kirin970.h" +#include "drv_venc_efl.h" +#include +#include +#include +#include + +#ifndef _M_IX86 +typedef unsigned long long HI_U64; +#else +typedef __int64 HI_U64; +#endif + +#ifndef NULL +#define NULL 0L +#endif +#define HI_SUCCESS (0) +#define HI_FAILURE (-1) +#define MAX_STREAMBUF_NUM (16) +#define IOC_TYPE_VENC 'V' + +extern unsigned int b_Regular_down_flag; + +typedef enum +{ + VENC_SET_CFGREG = 100, + VENC_SET_CFGREGSIMPLE +}CMD_TYPE; + +typedef enum { + VENC_CLK_RATE_LOW = 0, + VENC_CLK_RATE_NORMAL, + VENC_CLK_RATE_HIGH, +} VENC_CLK_TYPE; + +typedef struct +{ + int InteralShareFd; + int ImageShareFd; + int StreamShareFd[MAX_STREAMBUF_NUM]; + int StreamHeadShareFd; +}VENC_MEM_INFO_S; + +typedef struct +{ + CMD_TYPE cmd; + + int bResetReg; + int bClkCfg; + int bFirstNal2Send; + unsigned int bSecureFlag; + U_FUNC_VCPI_RAWINT hw_done_type; + S_HEVC_AVC_REGS_TYPE_CFG all_reg; + VENC_CLK_TYPE clk_type; + VENC_MEM_INFO_S mem_info; +}VENC_REG_INFO_S; + +#define CMD_VENC_START_ENCODE _IOWR(IOC_TYPE_VENC, 0x32, VENC_REG_INFO_S) + +int VENC_DRV_BoardInit(void); +void VENC_DRV_BoardDeinit(void); +int VENC_DRV_MemProcAdd(void); +void VENC_DRV_MemProcDel(void); + +void VENC_HAL_ClrAllInt(S_HEVC_AVC_REGS_TYPE * pVeduReg); +void VENC_HAL_DisableAllInt(S_HEVC_AVC_REGS_TYPE * pVeduReg); +int VENC_HAL_ResetReg(void); +void VENC_HAL_StartEncode(S_HEVC_AVC_REGS_TYPE * pVeduReg); +void VENC_HAL_Get_CfgRegSimple(VENC_REG_INFO_S * pVeduReg); +void VENC_HAL_Get_Reg_Venc(VENC_REG_INFO_S * pVeduReg); +void VeduHal_CfgReg_IntraSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_LambdaSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_QpgmapSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_AddrSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_SlcHeadSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_SMMUSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg_PREMMUSet(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgRegSimple(VENC_REG_INFO_S * channelcfg); +void VeduHal_CfgReg(VENC_REG_INFO_S * regcfginfo); +void VENC_HAL_SetSmmuAddr(S_HEVC_AVC_REGS_TYPE * pVeduReg); +#endif //__DRV_VENC_H__ + diff --git a/drivers/vcodec/venc_hivna/drv_venc_config.cfg b/drivers/vcodec/venc_hivna/drv_venc_config.cfg new file mode 100755 index 000000000000..18e9ff4011d1 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_config.cfg @@ -0,0 +1,65 @@ +############################################################## +# VENC DRV CFG # +############################################################## + +############## VENC_SIMULATE ####################### +#VENC_SIMULATE = YES +VENC_SIMULATE = NO + +############## TEST_TIME ########################### +#TEST_TIME = YES +TEST_TIME = NO + +############## SLICE_INT_EN ######################## +#SLICE_INT_EN = YES +SLICE_INT_EN = NO + +############## RE_ENCODE_EN ######################## +#RE_ENCODE_EN = YES +RE_ENCODE_EN = NO + +############## SPLIT_SPS_PPS ####################### +SPLIT_SPS_PPS = YES +#SPLIT_SPS_PPS = NO + +############## SHUTDOWN_REGULATOR_EN ############### +#SHUTDOWN_REGULATOR_EN = YES +SHUTDOWN_REGULATOR_EN = NO + +############## IRQ_EN ############################## +IRQ_EN = YES +#IRQ_EN = NO + +############## MD5_WC_EN ########################### +#MD5_WC_EN = YES +MD5_WC_EN = NO + +############## RCN_DBG_EN ########################### +#RCN_DBG_EN = YES +RCN_DBG_EN = NO + +############## HARDWARE_SPLIT_SPS_PPS_EN ########### +#HARDWARE_SPLIT_SPS_PPS_EN = YES +HARDWARE_SPLIT_SPS_PPS_EN = NO + +############## OUTPUT_LOWDELAY_EN ################## +#OUTPUT_LOWDELAY_EN = YES +OUTPUT_LOWDELAY_EN = NO + +############## SAO_LOWPOWER_EN ##################### +#SAO_LOWPOWER_EN = YES +SAO_LOWPOWER_EN = NO + +############## VENC_VOLT_HOLD ##################### +#VENC_VOLT_HOLD = YES +VENC_VOLT_HOLD = NO + + +############## VENC_SMMU_QOS_PRINT ##################### +#VENC_SMMU_QOS_PRINT = YES +VENC_SMMU_QOS_PRINT = NO + +############## VENC_TIMER_ENABLE ##################### +#VENC_TIMER_ENABLE = YES +VENC_TIMER_ENABLE = NO + diff --git a/drivers/vcodec/venc_hivna/drv_venc_efl.c b/drivers/vcodec/venc_hivna/drv_venc_efl.c new file mode 100755 index 000000000000..df9f8dedebae --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_efl.c @@ -0,0 +1,196 @@ +#include "drv_venc_efl.h" +#include "drv_venc_osal.h" +#include "hi_drv_mem.h" + + +/*lint -e774 -e697 -e838*/ +/*lint -e685 -e568 -e687 -e701 -e713 -e574 -e702 -e737*/ +unsigned int gVencIsFPGA = 0; +unsigned int gVeduIrqNumNorm = 0; +unsigned int gVeduIrqNumPort = 0; +unsigned int gVeduIrqNumSafe = 0; +unsigned int gVencRegBaseAddr = 0; +unsigned int gVencRegRange = 0; +HI_U64 gSmmuPageBaseAddr = 0; + +U_FUNC_VCPI_RAWINT g_hw_done_type ; +VEDU_OSAL_EVENT g_hw_done_event; + +/*******************************************************************/ +VeduEfl_IpCtx_S VeduIpCtx; + +int VENC_SetDtsConfig(VeduEfl_DTS_CONFIG_S *pDtsConfig) +{ + if (!pDtsConfig){ + HI_FATAL_VENC("pDtsConfig is NULL\n"); + return HI_FAILURE; + } + + if (pDtsConfig->VeduIrqNumNorm == 0 || pDtsConfig->VeduIrqNumProt == 0 || pDtsConfig->VeduIrqNumSafe == 0 || pDtsConfig->VencRegBaseAddr == 0 || + pDtsConfig->VencRegRange == 0 || pDtsConfig->SmmuPageBaseAddr == 0){ + HI_ERR_VENC("invalid param, VeduIrqNumNorm:%d, VeduIrqNumProt:%d, VeduIrqNumSafe:%d, VencRegBaseAddr:%pK, VencRegRange:%d, SmmuPageBaseAddr:%pK\n", + pDtsConfig->VeduIrqNumNorm, pDtsConfig->VeduIrqNumProt, pDtsConfig->VeduIrqNumSafe, (void *)(uintptr_t)(pDtsConfig->VencRegBaseAddr), pDtsConfig->VencRegRange, (void *)(uintptr_t)(pDtsConfig->SmmuPageBaseAddr)); + return HI_FAILURE; + } + gVencIsFPGA = pDtsConfig->IsFPGA; + gVeduIrqNumNorm = pDtsConfig->VeduIrqNumNorm; + gVeduIrqNumPort = pDtsConfig->VeduIrqNumProt; + gVeduIrqNumSafe = pDtsConfig->VeduIrqNumSafe; + + gVencRegBaseAddr = pDtsConfig->VencRegBaseAddr; + gVencRegRange = pDtsConfig->VencRegRange; + gSmmuPageBaseAddr = pDtsConfig->SmmuPageBaseAddr; + + return HI_SUCCESS; +} + +static void Venc_ISR(void) +{ + unsigned int *pINTCLR = NULL; + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + HI_DBG_VENC("enter %s ()\n", __func__); + + if (!VeduIpCtx.pRegBase) { + HI_ERR_VENC("VeduIpCtx.pRegBase invalid"); + return ; + } + pAllReg = (S_HEVC_AVC_REGS_TYPE *)VeduIpCtx.pRegBase;/*lint !e826 */ + pINTCLR = (unsigned int *)&(pAllReg->VEDU_VCPI_INTCLR.u32); + + g_hw_done_type.bits.vcpi_rint_vedu_timeout = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_vedu_timeout; + g_hw_done_type.bits.vcpi_rint_vedu_slice_end = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_vedu_slice_end; + g_hw_done_type.bits.vcpi_rint_ve_eop = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop; + +#ifdef VENC_SIMULATE + pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop = 0; +#endif + if (g_hw_done_type.bits.vcpi_rint_vedu_timeout + || g_hw_done_type.bits.vcpi_rint_ve_eop) { + *pINTCLR = 0xFFFFFFFF; + VENC_DRV_OsalGiveEvent(&g_hw_done_event); + } else { + *pINTCLR = 0xFFFFFFBE; + } + + HI_DBG_VENC("out %s ()\n", __func__); +} + +/****************************************************************************** +Function : +Description: IP-VEDU & IP-JPGE Open & Close +Calls : +Input : +Output : +Return : +Others : +******************************************************************************/ +int VENC_DRV_EflOpenVedu(void) +{ + HI_DBG_VENC("enter %s()\n", __func__); + + HiMemSet((void *)&VeduIpCtx, 0, sizeof(VeduIpCtx)); + + if (VENC_DRV_OsalLockCreate( &VeduIpCtx.pChnLock ) == HI_FAILURE){ + HI_ERR_VENC("VENC_DRV_OsalLockCreate failed\n"); + return HI_FAILURE; + } + + VeduIpCtx.pRegBase = (unsigned int *)HiMmap(gVencRegBaseAddr, gVencRegRange); + + if (!VeduIpCtx.pRegBase){ + HI_ERR_VENC("ioremap failed\n"); + VENC_DRV_OsalLockDestroy( VeduIpCtx.pChnLock ); + return HI_FAILURE; + } + + HI_DBG_VENC("HI_DDR_MEM_Init\n"); + if (HI_SUCCESS != DRV_MEM_INIT()) { + HI_ERR_VENC("DRV_MEM_INIT failed\n"); + VENC_DRV_OsalLockDestroy( VeduIpCtx.pChnLock ); + HiMunmap(VeduIpCtx.pRegBase); + return HI_FAILURE; + } + + VeduIpCtx.IpFree = 1; + VENC_HAL_SetSmmuAddr((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + VENC_HAL_DisableAllInt((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + VENC_HAL_ClrAllInt ((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ +#ifdef IRQ_EN + if (VENC_DRV_OsalIrqInit(gVeduIrqNumNorm, Venc_ISR) == HI_FAILURE){ + HI_ERR_VENC("VENC_DRV_OsalIrqInit failed\n"); + VENC_DRV_OsalLockDestroy( VeduIpCtx.pChnLock ); + HiMunmap(VeduIpCtx.pRegBase); + DRV_MEM_EXIT(); + return HI_FAILURE; + } +#endif + /* creat thread to manage channel */ + VeduIpCtx.StopTask = 0; + VeduIpCtx.TaskRunning = 0; + + VENC_DRV_OsalInitEvent(&g_hw_done_event, 0); + + HI_DBG_VENC("exit %s()\n", __func__); + return HI_SUCCESS; +} + +int VENC_DRV_EflCloseVedu( void ) +{ + unsigned int TimeOutCnt = 0; +#ifdef MD5_WC_EN + int i = 0; + unsigned char digesttmp[16] ; + unsigned char digesttmp2[100] ; + HiMemSet(digesttmp, 0, 16); + HiMemSet(digesttmp2, 0, 100); +#endif + HI_DBG_VENC("enter %s()\n", __func__); + VeduIpCtx.StopTask = 1; + + while ((VeduIpCtx.TaskRunning) && (TimeOutCnt < 100)) { + HiSleepMs(1); + TimeOutCnt ++; + } + + VENC_HAL_DisableAllInt((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + VENC_HAL_ClrAllInt((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + +#ifdef IRQ_EN + VENC_DRV_OsalIrqFree(gVeduIrqNumNorm); +#endif + HiMunmap(VeduIpCtx.pRegBase); + DRV_MEM_EXIT(); + VENC_DRV_OsalLockDestroy( VeduIpCtx.pChnLock ); + + HI_DBG_VENC("exit %s()\n", __func__); + return HI_SUCCESS; +} + +int VENC_DRV_EflSuspendVedu(void) +{ + unsigned int TimeOutCnt = 0; + HI_INFO_VENC("enter %s()\n", __func__); + + VeduIpCtx.StopTask = 1; + + while ((VeduIpCtx.TaskRunning) && (TimeOutCnt < 100)) { + HiSleepMs(1); + TimeOutCnt ++; + } + + HI_INFO_VENC("exit %s()\n", __func__); + return HI_SUCCESS; +} + +int VENC_DRV_EflResumeVedu(void) +{ + HI_INFO_VENC("enter %s()\n", __func__); + + VeduIpCtx.StopTask = 0; + VeduIpCtx.TaskRunning = 0; + + HI_INFO_VENC("exit %s()\n", __func__); + return HI_SUCCESS; +} + diff --git a/drivers/vcodec/venc_hivna/drv_venc_efl.h b/drivers/vcodec/venc_hivna/drv_venc_efl.h new file mode 100755 index 000000000000..d52c79c3fc51 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_efl.h @@ -0,0 +1,47 @@ +#ifndef __DRV_VENC_EFL_H__ +#define __DRV_VENC_EFL_H__ + +#include "hi_drv_mem.h" +#include "drv_venc.h" + +enum { + VEDU_H265 = 0, + VEDU_H264 = 1 +}; + +typedef struct { + unsigned int IpFree; /* for channel control */ + unsigned long long CurrHandle;//HI_U64 CurrHandle; /* used in ISR */ + unsigned int *pRegBase; + void *pChnLock; /* lock ChnCtx[MAX_CHN] */ + void *pTask_Frame; /* for both venc & omxvenc */ + void *pTask_Stream; /* juse for omxvenc */ + unsigned int StopTask; + unsigned int TaskRunning; /* to block Close IP */ + unsigned int bReEncode; +} VeduEfl_IpCtx_S; + +typedef struct { + unsigned int IsFPGA; + unsigned int VeduIrqNumNorm; + unsigned int VeduIrqNumProt; + unsigned int VeduIrqNumSafe; + unsigned int VencRegBaseAddr; + unsigned int VencRegRange; + unsigned int normalRate; + unsigned int highRate; + unsigned int lowRate; + unsigned long long SmmuPageBaseAddr;//HI_U64 SmmuPageBaseAddr; +} VeduEfl_DTS_CONFIG_S; + +int VENC_DRV_EflOpenVedu(void); +int VENC_DRV_EflCloseVedu(void); +int VENC_DRV_EflResumeVedu(void); +int VENC_DRV_EflSuspendVedu(void); +int VENC_SetDtsConfig(VeduEfl_DTS_CONFIG_S* info); + +/*************************************************************************************/ + + +#endif //__DRV_VENC_EFL_H__ + diff --git a/drivers/vcodec/venc_hivna/drv_venc_intf.c b/drivers/vcodec/venc_hivna/drv_venc_intf.c new file mode 100755 index 000000000000..e302d12ea509 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_intf.c @@ -0,0 +1,534 @@ + +/* +* Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd. +* +* File Name : viu.c +* Version : Initial Draft +* Author : Hisilicon multimedia software group +* Created : +* Description : +* +* History : +* 1.Date : 2010/03/17 +* Author : j00131665 +* Modification: Created file +*/ +#include +#include +#include +#include +#include + +#include "drv_venc_osal.h" +#include "drv_venc.h" +#include "venc_regulator.h" +#include "drv_venc.h" +#define VERSION_STRING "1234" +#define PCTRL_PERI 0xE8A090A4 +#define PCTRL_PERI_SATA0 (0xE8A090BC) +#define MAX_OPEN_COUNT 3 +/*lint -e750 -e838 -e715*/ +#ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/ +# define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP) +#endif + +/*============Deviece===============*/ +typedef struct { + dev_t dev; + struct device* venc_device; + //struct device* venc_device_2; + struct cdev cdev; + struct class* venc_class; +}VENC_ENTRY; + +typedef enum { + KIRIN_960, + KIRIN_970_ES, + KIRIN_970_CS, +}KIRIN_PLATFORM_E; + +typedef struct { + MEM_BUFFER_S internalbuffer; + MEM_BUFFER_S imagebuffer; + MEM_BUFFER_S streambuffer[MAX_STREAMBUF_NUM]; + MEM_BUFFER_S streamheadbuffer; +}VENC_MEM_INFO; + +struct semaphore g_VencMutex; + +static int g_vencOpenFlag = 0; +static int g_vencDevDetected = 0; + +//VENC device open times +atomic_t g_VencCount = ATOMIC_INIT(0); + +int VENC_DRV_Resume(struct platform_device *pltdev); +int VENC_DRV_Suspend(struct platform_device *pltdev, pm_message_t state); + +static int VENC_DRV_SetupCdev(VENC_ENTRY *venc, const struct file_operations *fops); +static int VENC_DRV_CleanupCdev(VENC_ENTRY *venc); +static int VENC_DRV_Probe(struct platform_device * pltdev); +static int VENC_DRV_Remove(struct platform_device *pltdev); + +extern VeduEfl_IpCtx_S VeduIpCtx; +extern U_FUNC_VCPI_RAWINT g_hw_done_type; +extern VEDU_OSAL_EVENT g_hw_done_event; +extern unsigned int gVencIsFPGA; + +static int venc_drv_waithwdone(U_FUNC_VCPI_RAWINT *hw_done_type) +{ + int Ret = HI_FAILURE; + + Ret = VENC_DRV_OsalWaitEvent(&g_hw_done_event, msecs_to_jiffies(500));/*lint !e712 !e747 */ + + if (Ret != 0) { + hw_done_type->u32 = 0; + HI_ERR_VENC("wait timeout, Ret value is %d\n", Ret); + return Ret; + } + + *hw_done_type = g_hw_done_type; + return Ret; +} + +static int venc_drv_register_info(VENC_REG_INFO_S *regcfginfo) +{ + int Ret = HI_SUCCESS; + CMD_TYPE cmd = regcfginfo->cmd; + switch (cmd) { + case VENC_SET_CFGREG: + if (regcfginfo->bResetReg == 1) + { + Ret = VENC_HAL_ResetReg(); + if (Ret != HI_SUCCESS) + { + HI_ERR_VENC("reset venc hal reset reg, Ret:%d\n", Ret); + break; + } + } + + VeduHal_CfgReg(regcfginfo); + + VENC_HAL_StartEncode((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + + Ret = venc_drv_waithwdone(®cfginfo->hw_done_type) ; + + if((Ret == HI_SUCCESS ) && (!regcfginfo->hw_done_type.bits.vcpi_rint_vedu_timeout)) + { + VENC_HAL_Get_Reg_Venc(regcfginfo); + HI_DBG_VENC("get venc hal reg info\n"); + } + break; + case VENC_SET_CFGREGSIMPLE: + VeduHal_CfgRegSimple(regcfginfo); + + VENC_HAL_StartEncode((S_HEVC_AVC_REGS_TYPE*)(VeduIpCtx.pRegBase));/*lint !e826 */ + + Ret = venc_drv_waithwdone(®cfginfo->hw_done_type) ; + + if((Ret == HI_SUCCESS ) && (!regcfginfo->hw_done_type.bits.vcpi_rint_vedu_timeout)) + { + VENC_HAL_Get_Reg_Venc(regcfginfo); + HI_DBG_VENC("get venc hal reg info\n"); + } + break; + default: + HI_ERR_VENC("cmd type unknown:0x%x in default case\n", cmd); + Ret = HI_FAILURE; + break; + } + return Ret; +} +static int VENC_DRV_Open(struct inode *finode, struct file *ffile) +{ + int Ret = 0; + + Ret = HiVENC_DOWN_INTERRUPTIBLE(&g_VencMutex); + if (Ret) { + HI_FATAL_VENC("Open down interruptible failed\n"); + return HI_FAILURE; + } + + if (atomic_read(&g_VencCount) == MAX_OPEN_COUNT) { + HI_FATAL_VENC("open venc too much\n"); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return -EAGAIN; + } + + if (atomic_inc_return(&g_VencCount) == 1) { + Ret = VENC_DRV_BoardInit(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("board init failed, ret value is %d\n", Ret); + atomic_dec(&g_VencCount); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + Ret = VENC_DRV_EflOpenVedu(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("venc firmware layer open failed, ret value is %d\n", Ret); + atomic_dec(&g_VencCount); + VENC_DRV_BoardDeinit(); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + } + + g_vencOpenFlag = 1; + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + + HI_INFO_VENC("Open venc device successfully\n"); + return HI_SUCCESS; +} + +static int VENC_DRV_Close(struct inode *finode, struct file *ffile) +{ + int Ret = 0; + + Ret = HiVENC_DOWN_INTERRUPTIBLE(&g_VencMutex); + if (Ret) { + HI_FATAL_VENC("Close down interruptible failed\n"); + return HI_FAILURE; + } + + if (atomic_dec_and_test(&g_VencCount)) { + Ret = VENC_DRV_EflCloseVedu(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("venc firmware layer close failed, ret value is %d\n", Ret); + VENC_DRV_BoardDeinit(); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + + VENC_DRV_BoardDeinit(); + g_vencOpenFlag = 0; + } + + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + + HI_INFO_VENC("Close venc device successfully\n"); + return HI_SUCCESS; +} + +int VENC_DRV_Suspend(struct platform_device *pltdev, pm_message_t state) +{ + int Ret = 0; + HI_INFO_VENC("enter\n"); + + Ret = HiVENC_DOWN_INTERRUPTIBLE(&g_VencMutex); + if (Ret) { + HI_ERR_VENC("Suspend down interruptible failed\n"); + return HI_FAILURE; + } + + if (!g_vencOpenFlag) { + HI_INFO_VENC("venc device already suspend\n"); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_SUCCESS; + } + + Ret = VENC_DRV_EflSuspendVedu(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("venc firmware layer suspend failed, ret value is %d\n", Ret); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + + VENC_DRV_BoardDeinit(); + g_hw_done_event.flag = 0; + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + + HI_INFO_VENC("exit\n"); + return HI_SUCCESS; +}/*lint !e715*/ + +int VENC_DRV_Resume(struct platform_device *pltdev) +{ + int Ret = 0; + HI_INFO_VENC("enter\n"); + + Ret = HiVENC_DOWN_INTERRUPTIBLE(&g_VencMutex); + if (Ret) { + HI_FATAL_VENC("Resume down interruptible failed\n"); + return HI_FAILURE; + } + + if (!g_vencOpenFlag) { + HI_INFO_VENC("venc device already resume\n"); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return 0; + } + Ret = VENC_DRV_BoardInit(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("board init failed, ret value is %d\n", Ret); + atomic_dec(&g_VencCount); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + Ret = VENC_DRV_EflResumeVedu(); + if (Ret != HI_SUCCESS) { + HI_FATAL_VENC("venc firmware layer resume failed, ret value is %d\n", Ret); + atomic_dec(&g_VencCount); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return HI_FAILURE; + } + + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + HI_INFO_VENC("exit\n"); + return HI_SUCCESS; +}/*lint !e715*/ + +static long VENC_Ioctl(struct file *file, unsigned int ucmd, unsigned long uarg) +{ + int Ret; + int cmd = (int)ucmd; + void *arg = (void *)uarg; + VENC_REG_INFO_S *regcfginfo = NULL; + VENC_MEM_INFO VencMapInfo; + + if (!arg) { + //HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + HI_FATAL_VENC("uarg is NULL\n"); + return HI_FAILURE; + } + + switch (cmd) { + case CMD_VENC_START_ENCODE:/*lint !e30 !e142*/ + VeduIpCtx.TaskRunning = 1; + regcfginfo = (VENC_REG_INFO_S *)arg; + HiMemSet((void*)&VencMapInfo, 0, sizeof(VencMapInfo)); + + VENC_DRV_OsalInitEvent(&g_hw_done_event, 0); + + Ret = venc_drv_register_info(regcfginfo); + VeduIpCtx.TaskRunning = 0; + HI_DBG_VENC("venc cfg reg info, Ret:%d\n", Ret); + break; + default: + HI_ERR_VENC("venc cmd unknown:0x%x\n", ucmd); + Ret = HI_FAILURE; + break; + } + //HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return Ret; +} +static long VENC_DRV_Ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long Ret; + + Ret = HiVENC_DOWN_INTERRUPTIBLE(&g_VencMutex); + if (Ret != 0) + { + HI_FATAL_VENC("Ioctl, down interruptible failed\n"); + return Ret; + } + Ret = (long)HI_DRV_UserCopy(file, cmd, arg, VENC_Ioctl); + HiVENC_UP_INTERRUPTIBLE(&g_VencMutex); + return Ret; +} + +static struct file_operations VENC_FOPS = +{ + .owner = THIS_MODULE,/*lint !e64 */ + .open = VENC_DRV_Open, + .unlocked_ioctl = VENC_DRV_Ioctl, + .compat_ioctl = VENC_DRV_Ioctl, + .release = VENC_DRV_Close, +};/*lint !e785 */ + +static const struct of_device_id venc_of_match[] = { + { .compatible = "hisi,kirin970-venc", },/*lint !e785 */ + { }/*lint !e785 */ +}; + +static struct platform_driver Venc_driver = { + .probe = VENC_DRV_Probe, + .remove = VENC_DRV_Remove, + .suspend = VENC_DRV_Suspend, + .resume = VENC_DRV_Resume, + .driver = { + .name = "hi_venc", + .owner = THIS_MODULE,/*lint !e64 */ + .of_match_table = venc_of_match + },/*lint !e785 */ +};/*lint !e785 */ + +static struct platform_device Venc_device = { + .name = "hi_venc", + .id = -1, + .dev = { + .platform_data = NULL, + .release = NULL, + },/*lint !e785 */ +};/*lint !e785 */ + +static int VENC_DRV_SetupCdev(VENC_ENTRY *venc, const struct file_operations *fops) +{ + int err = 0; + + HI_INFO_VENC("enter %s()\n", __func__); + err = alloc_chrdev_region(&venc->dev, 0, 1, "hi_venc"); + if (err < 0) { + return HI_FAILURE; + } + + HiMemSet((void*)&(venc->cdev), 0, sizeof(struct cdev)); + cdev_init(&(venc->cdev), &VENC_FOPS); + + venc->cdev.owner = THIS_MODULE;/*lint !e64 */ + venc->cdev.ops = &VENC_FOPS; + err = cdev_add(&(venc->cdev), venc->dev, 1); + + /*ÔÚ/sys/class/Ŀ¼Ï´´½¨É豸Àà±ðĿ¼hi_venc*/ + venc->venc_class = class_create(THIS_MODULE, "hi_venc");/*lint !e64 */ + if (IS_ERR(venc->venc_class)) { + err = PTR_ERR(venc->venc_class);/*lint !e712 */ + HI_ERR_VENC("Fail to create hi_venc class\n"); + goto unregister_region; + //return HI_FAILURE;/*lint !e438 */ + } + + /*ÔÚ/dev/Ŀ¼ºÍ/sys/class/hi_vencĿ¼Ï·ֱ𴴽¨É豸Îļþhi_venc*/ + venc->venc_device = device_create(venc->venc_class, NULL, venc->dev, "%s", "hi_venc"); + if (IS_ERR(venc->venc_device)) { + err = PTR_ERR(venc->venc_device);/*lint !e712 */ + HI_ERR_VENC("Fail to create hi_venc device\n"); + goto cls_destroy; + //return HI_FAILURE;/*lint !e438 */ + } + + HI_INFO_VENC("exit %s()\n", __func__); + return HI_SUCCESS; + +cls_destroy: + class_destroy(venc->venc_class); + venc->venc_class = NULL; +unregister_region: + unregister_chrdev_region(venc->dev, 1); + return 0; +}/*lint !e550 */ + +static int VENC_DRV_CleanupCdev(VENC_ENTRY *venc) +{ + /*Ïú»ÙÉ豸Àà±ðºÍÉ豸*/ + if (venc->venc_class) { + device_destroy(venc->venc_class,venc->dev); + class_destroy(venc->venc_class); + } + + cdev_del(&(venc->cdev)); + unregister_chrdev_region(venc->dev,1); + + return 0; +} + +static int VENC_DRV_Probe(struct platform_device * pltdev) +{ + int ret = HI_FAILURE; + VENC_ENTRY *venc = NULL; + + HI_INFO_VENC("omxvenc prepare to probe\n"); + HiVENC_INIT_MUTEX(&g_VencMutex); + if (g_vencDevDetected) { + HI_INFO_VENC("venc device detected already\n"); + return HI_SUCCESS; + } + + venc = HiMemVAlloc(sizeof(VENC_ENTRY));/*lint !e747 */ + if (!venc) { + HI_FATAL_VENC("call vmalloc failed\n"); + return ret; + } + + HiMemSet((void *)venc, 0, sizeof(VENC_ENTRY)); + ret = VENC_DRV_SetupCdev(venc, &VENC_FOPS); + if (ret < 0) { + HI_ERR_VENC("setup char device failed\n"); + goto free; + } + + platform_set_drvdata(pltdev, venc); + g_vencDevDetected = 1; + + ret = Venc_Regulator_Init(pltdev); + if (ret < 0) { + HI_FATAL_VENC("init regulator failed\n"); + goto cleanup; + } + + HI_INFO_VENC("omxvenc probe successfully\n"); + return ret; + +cleanup: + VENC_DRV_CleanupCdev(venc); +free: + HiMemVFree(venc); + return ret; +} + +static int VENC_DRV_Remove(struct platform_device *pltdev) +{ + VENC_ENTRY *venc = NULL; + HI_INFO_VENC("omxvenc prepare to remove\n"); + + venc = platform_get_drvdata(pltdev); + if (venc) { + VENC_DRV_CleanupCdev(venc); + Venc_Regulator_Deinit(pltdev); + } + else { + HI_ERR_VENC("get platform drvdata err\n"); + } + + platform_set_drvdata(pltdev,NULL); + HiMemVFree(venc); + g_vencDevDetected = 0; + + HI_INFO_VENC("remove omxvenc successfully\n"); + return 0; +} + +int __init VENC_DRV_ModInit(void) +{ + int ret = 0; + HI_INFO_VENC("enter %s()\n", __func__); + + ret = platform_device_register(&Venc_device); + if (ret < 0) { + HI_ERR_VENC("regist platform device failed\n"); + return ret; + } + + ret = platform_driver_register(&Venc_driver);/*lint !e64 */ + if (ret < 0) { + HI_ERR_VENC("regist platform driver failed\n"); + goto exit; + } + HI_INFO_VENC("success\n"); +#ifdef MODULE + HI_INFO_VENC("Load hi_venc.ko success\t(%s)\n", VERSION_STRING); +#endif + HI_INFO_VENC("exit %s()\n", __func__); + return HI_SUCCESS; +exit: + platform_device_unregister(&Venc_device); +#ifdef MODULE + HI_ERR_VENC("Load hi_venc.ko failed\t(%s)\n", VERSION_STRING); +#endif + return ret; +} + +void VENC_DRV_ModExit(void) +{ + HI_INFO_VENC("enter %s()\n", __func__); + platform_driver_unregister(&Venc_driver); + platform_device_unregister(&Venc_device); + + HI_INFO_VENC("exit %s()\n", __func__); + return; +} +/*lint -e528*/ +module_init(VENC_DRV_ModInit); /*lint !e528*/ +module_exit(VENC_DRV_ModExit); /*lint !e528*/ +/*lint -e753*/ +MODULE_LICENSE("Dual BSD/GPL"); /*lint !e753*/ + diff --git a/drivers/vcodec/venc_hivna/drv_venc_make.cfg b/drivers/vcodec/venc_hivna/drv_venc_make.cfg new file mode 100755 index 000000000000..6658c9611bd2 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_make.cfg @@ -0,0 +1,82 @@ +########################################################## +# VENC DRV MAKE CONFIG # +########################################################## + +include drivers/vcodec/venc_hivna/drv_venc_config.cfg + +############## VENC_SIMULATE ####################### +ifeq ($(VENC_SIMULATE),YES) +VENC_CFLAGS := -DVENC_SIMULATE +endif + +############## TEST_TIME ########################### +ifeq ($(TEST_TIME),YES) +VENC_CFLAGS += -DTEST_TIME +endif + +############## SLICE_INT_EN ######################## +ifeq ($(SLICE_INT_EN),YES) +VENC_CFLAGS += -DSLICE_INT_EN +endif + +############## RE_ENCODE_EN ######################## +ifeq ($(RE_ENCODE_EN),YES) +VENC_CFLAGS += -DRE_ENCODE_EN +endif + +############## SPLIT_SPS_PPS ####################### +ifeq ($(SPLIT_SPS_PPS),YES) +VENC_CFLAGS += -DSPLIT_SPS_PPS +endif + +############## SHUTDOWN_REGULATOR_EN ############### +ifeq ($(SHUTDOWN_REGULATOR_EN),YES) +VENC_CFLAGS += -DSHUTDOWN_REGULATOR_EN +endif + +############## IRQ_EN ############################## +ifeq ($(IRQ_EN),YES) +VENC_CFLAGS += -DIRQ_EN +endif + +############## MD5_WC_EN ########################### +ifeq ($(MD5_WC_EN),YES) +VENC_CFLAGS += -DMD5_WC_EN +endif + +############## RCN_DBG_EN ########################### +ifeq ($(RCN_DBG_EN),YES) +VENC_CFLAGS += -DRCN_DBG_EN +endif + +############## HARDWARE_SPLIT_SPS_PPS_EN ########### +ifeq ($(HARDWARE_SPLIT_SPS_PPS_EN), YES) +VENC_CFLAGS += -DHARDWARE_SPLIT_SPS_PPS_EN +endif + +############## OUTPUT_LOWDELAY_EN ################## +ifeq ($(OUTPUT_LOWDELAY_EN),YES) +VENC_CFLAGS += -DOUTPUT_LOWDELAY_EN +endif + +############## SAO_LOWPOWER_EN ##################### +ifeq ($(SAO_LOWPOWER_EN),YES) +VENC_CFLAGS += -DSAO_LOWPOWER_EN +endif + +############## VENC_VOLT_HOLD ###################### +ifeq ($(VENC_VOLT_HOLD),YES) +VENC_CFLAGS += -DVENC_VOLT_HOLD +endif + + +############## VENC_SMMU_QOS_PRINT ###################### +ifeq ($(VENC_SMMU_QOS_PRINT),YES) +VENC_CFLAGS += -DVENC_SMMU_QOS_PRINT +endif + +############## VENC_TIMER_ENABLE ##################### +ifeq ($(VENC_TIMER_ENABLE),YES) +VENC_CFLAGS += -DVENC_TIMER_ENABLE +endif + diff --git a/drivers/vcodec/venc_hivna/drv_venc_osal.c b/drivers/vcodec/venc_hivna/drv_venc_osal.c new file mode 100755 index 000000000000..cf2b8fbf481b --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_osal.c @@ -0,0 +1,258 @@ +#include +#include + +#include "drv_venc_osal.h" +#include "hi_drv_mem.h" + +#define TIME_PERIOD(begin, end) ((end >= begin) ? (end - begin) : (0xffffffff - begin + end)) + +/*lint -e747 -e712 -e732 -e715 -e774 -e845 -e438 -e838*/ +unsigned int g_VencPrintEnable = 0xf; + +char *pszMsg[((char)VENC_ALW) + 1] = {"FATAL","ERR","WARN","IFO","DBG"}; /*lint !e785 */ +char g_VencPrintMsg[1024]; + +static void (*ptrVencCallBack)(void); + +static irqreturn_t VENC_DRV_OsalVencISR(int Irq, void *DevID) +{ + (*ptrVencCallBack)(); + return IRQ_HANDLED; +} + +int VENC_DRV_OsalIrqInit( unsigned int Irq, void (*ptrCallBack)(void)) +{ + int ret = 0; + + if (Irq != 0) { + ptrVencCallBack = ptrCallBack; + ret = request_irq(Irq, VENC_DRV_OsalVencISR, 0, "DT_device", NULL); + } else { + HI_FATAL_VENC("params is invaild\n"); + ret = HI_FAILURE; + } + + if (ret == 0) { + return HI_SUCCESS; + } else { + HI_FATAL_VENC("request irq failed\n"); + return HI_FAILURE; + } +} + +void VENC_DRV_OsalIrqFree(unsigned int Irq) +{ + free_irq(Irq, NULL); +} + +int VENC_DRV_OsalLockCreate(void **phLock) +{ + spinlock_t *pLock = NULL; + + pLock = (spinlock_t *)vmalloc(sizeof(spinlock_t)); + + if (!pLock) { + HI_FATAL_VENC("vmalloc failed\n"); + return HI_FAILURE; + } + + spin_lock_init( pLock ); + *phLock = pLock; + + return HI_SUCCESS; +} + +void VENC_DRV_OsalLockDestroy( void* hLock ) +{ + if (hLock) { + vfree((void *)hLock); + //hLock = NULL; + } +} + +/************************************************************************/ +/* ³õʼ»¯Ê¼þ */ +/************************************************************************/ +int VENC_DRV_OsalInitEvent(VEDU_OSAL_EVENT *pEvent, int InitVal) +{ + pEvent->flag = InitVal; + init_waitqueue_head(&(pEvent->queue_head)); + return HI_SUCCESS; +} + +/************************************************************************/ +/* ·¢³öʼþ»½ÐÑ */ +/************************************************************************/ +int VENC_DRV_OsalGiveEvent(VEDU_OSAL_EVENT *pEvent) +{ + pEvent->flag = 1; + wake_up(&(pEvent->queue_head)); + return HI_SUCCESS; +} + +HI_U64 get_sys_time(void) +{ + HI_U64 sys_time; + + sys_time = sched_clock(); + do_div(sys_time, 1000000); + + return sys_time; +} + +/************************************************************************/ +/* µÈ´ýʼþ */ +/* ʼþ·¢Éú·µ»ØOSAL_OK£¬³¬Ê±·µ»ØOSAL_ERR Èôcondition²»Âú×ã¾Í×èÈûµÈ´ý */ +/* ±»»½ÐÑ·µ»Ø 0 £¬³¬Ê±·µ»Ø·Ç-1 */ +/************************************************************************/ +int VENC_DRV_OsalWaitEvent(VEDU_OSAL_EVENT *pEvent, unsigned int msWaitTime) +{ + int l_ret = 0; + unsigned int cnt = 0; + + HI_U64 start_time, cur_time; + start_time = get_sys_time(); + + do { + l_ret = wait_event_interruptible_timeout((pEvent->queue_head), (pEvent->flag != 0), (msecs_to_jiffies(msWaitTime))); /*lint !e665 !e666 !e40 !e713 !e578*/ + if (l_ret < 0) { + cur_time = get_sys_time(); + if (TIME_PERIOD(start_time, cur_time) > (HI_U64)msWaitTime) { + HI_FATAL_VENC("wait event time out, time : %lld, cnt: %d\n", TIME_PERIOD(start_time, cur_time), cnt); + l_ret = 0; + break; + } + } + cnt++; + } while ((pEvent->flag == 0) && (l_ret < 0)); + + if (cnt > 100) { + HI_FATAL_VENC("the max cnt of wait_event interrupts by singal is %d\n", cnt); + } + + if (l_ret == 0) { + HI_FATAL_VENC("wait pEvent signal timeout\n"); + } + + pEvent->flag = 0;//(pEvent->flag>0)? (pEvent->flag-1): 0; + return (l_ret != 0) ? HI_SUCCESS : HI_FAILURE; +} + +int HiMemCpy(void*a_pHiDstMem, void *a_pHiSrcMem, size_t a_Size) +{ + if ((!a_pHiDstMem) || (!a_pHiSrcMem)) { + HI_FATAL_VENC("params is invaild\n"); + return HI_FAILURE; + } + + memcpy((void *)a_pHiDstMem, (void *)a_pHiSrcMem, a_Size); /* unsafe_function_ignore: memcpy */ + return HI_SUCCESS; +} + +int HiMemSet(void *a_pHiDstMem, int a_Value, size_t a_Size) +{ + if (!a_pHiDstMem) { + HI_FATAL_VENC("params is invaild\n"); + return HI_FAILURE; + } + + memset((void *)a_pHiDstMem, a_Value, a_Size); /* unsafe_function_ignore: memset */ + + return HI_SUCCESS; +} + +void HiSleepMs(unsigned int a_MilliSec) +{ + msleep(a_MilliSec); +} + +unsigned int* HiMmap(unsigned int Addr ,unsigned int Range) +{ + unsigned int *res_addr = NULL; + res_addr = (unsigned int *)ioremap(Addr, Range); + return res_addr; +} + +void HiMunmap(unsigned int * pMemAddr) +{ + if (!pMemAddr) { + HI_FATAL_VENC("params is invaild\n"); + return; + } + + iounmap(pMemAddr); +} + +int HiStrNCmp(const char* pStrName,const char* pDstName,int nSize) +{ + int ret = 0; + if (pStrName && pDstName) { + ret = strncmp(pStrName,pDstName,nSize); + return ret; + } + + return HI_FAILURE; +} + +void *HiMemVAlloc(unsigned int nMemSize) +{ + void * memaddr = NULL; + if (nMemSize) { + memaddr = vmalloc(nMemSize); + } + return memaddr; + } + +void HiMemVFree(void *pMemAddr) +{ + if (pMemAddr) { + vfree((void *)pMemAddr); + } +} + +void HiVENC_INIT_MUTEX(void *pSem) +{ + if (pSem) { + sema_init((struct semaphore *)pSem, 1); + } +} + +int HiVENC_DOWN_INTERRUPTIBLE(void *pSem) +{ + int Ret = -1; + if (pSem) { + Ret = down_interruptible((struct semaphore *)pSem); + } + return Ret; +} + +void HiVENC_UP_INTERRUPTIBLE(void *pSem) +{ + if (pSem) { + up((struct semaphore *)pSem); + } +} + +void HI_PRINT(unsigned int type,char *file, int line , char *function, char *msg, ... ) +{ + va_list args; + unsigned int uTotalChar; + + if ( ((1 << type) & g_VencPrintEnable) == 0 && (type != VENC_ALW) ) /*lint !e701 */ + return ; + + va_start(args, msg); + + uTotalChar = vsnprintf(g_VencPrintMsg, sizeof(g_VencPrintMsg), msg, args); /* unsafe_function_ignore: vsnprintf */ + g_VencPrintMsg[sizeof(g_VencPrintMsg) - 1] = '\0'; + + va_end(args); + + if (uTotalChar <= 0 || uTotalChar >= 1023) /*lint !e775 */ + return; + + printk(KERN_ALERT "%s:<%d:%s>%s \n", pszMsg[type], line, function, g_VencPrintMsg); + return; +} + + diff --git a/drivers/vcodec/venc_hivna/drv_venc_osal.h b/drivers/vcodec/venc_hivna/drv_venc_osal.h new file mode 100755 index 000000000000..f192b33d0c45 --- /dev/null +++ b/drivers/vcodec/venc_hivna/drv_venc_osal.h @@ -0,0 +1,59 @@ +#ifndef __DRV_VENC_OSAL_H__ +#define __DRV_VENC_OSAL_H__ + +#include + +typedef struct hiKERN_EVENT_S +{ + wait_queue_head_t queue_head; + int flag; +} KERN_EVENT_S; + +typedef KERN_EVENT_S VEDU_OSAL_EVENT; +typedef unsigned long VEDU_LOCK_FLAG; + +#define MESCS_TO_JIFFIES(time) msecs_to_jiffies(time) +#define HiWaitEvent( pEvent, flag) wait_event_interruptible((pEvent), (flag)) +#define HiWaitEventTimeOut( pEvent, flag, msWaitTime) wait_event_interruptible_timeout((pEvent), (flag), (msWaitTime)) + +extern unsigned int g_VencPrintEnable; + +typedef enum { + VENC_FATAL = 0, + VENC_ERR, + VENC_WARN, + VENC_INFO, + VENC_DBG, + VENC_ALW, +}VENC_PRINT_TYPE; + +#define HI_FATAL_VENC(fmt,...) HI_PRINT(VENC_FATAL,(char *)__FILE__, (int)__LINE__, (char *)__FUNCTION__, fmt, ##__VA_ARGS__) +#define HI_ERR_VENC(fmt,...) HI_PRINT(VENC_ERR,(char *)__FILE__, (int)__LINE__, (char *)__FUNCTION__, fmt, ##__VA_ARGS__) +#define HI_WARN_VENC(fmt,...) HI_PRINT(VENC_WARN,(char *)__FILE__, (int)__LINE__, (char *)__FUNCTION__, fmt,##__VA_ARGS__) +#define HI_INFO_VENC(fmt,...) HI_PRINT(VENC_INFO,(char *)__FILE__, (int)__LINE__, (char *)__FUNCTION__, fmt,##__VA_ARGS__) +#define HI_DBG_VENC(fmt,...) HI_PRINT(VENC_DBG,(char *)__FILE__, (int)__LINE__, (char *)__FUNCTION__, fmt,##__VA_ARGS__) + +void HI_PRINT(unsigned int type, char *file, int line, char *function, char *msg, ... ); +unsigned int* HiMmap(unsigned int Addr ,unsigned int Range); +void HiMunmap(unsigned int * pMemAddr); +int HiStrNCmp(const char* pStrName,const char* pDstName,int nSize); +void HiSleepMs(unsigned int a_MilliSec); +void* HiMemVAlloc(unsigned int nMemSize); +void HiMemVFree(void * pMemAddr); +int HiMemSet(void * a_pHiDstMem, int a_Value, size_t a_Size); +int HiMemCpy(void * a_pHiDstMem, void * a_pHiSrcMem, size_t a_Size); +void HiVENC_INIT_MUTEX(void* pSem); +int HiVENC_DOWN_INTERRUPTIBLE(void* pSem); +void HiVENC_UP_INTERRUPTIBLE(void* pSem); +int VENC_DRV_OsalIrqInit(unsigned int Irq, void(*ptrCallBack)(void)); +void VENC_DRV_OsalIrqFree(unsigned int Irq); +int VENC_DRV_OsalLockCreate (void** phLock); +void VENC_DRV_OsalLockDestroy(void* hLock); +unsigned int GetTimeInUs(void); +int VENC_DRV_OsalInitEvent( VEDU_OSAL_EVENT *pEvent, int InitVal ); +int VENC_DRV_OsalGiveEvent( VEDU_OSAL_EVENT *pEvent ); +int VENC_DRV_OsalWaitEvent( VEDU_OSAL_EVENT *pEvent, unsigned int msWaitTime ); + + +#endif //__DRV_VENC_OSAL_H__ + diff --git a/drivers/vcodec/venc_hivna/hal_venc.c b/drivers/vcodec/venc_hivna/hal_venc.c new file mode 100755 index 000000000000..963363c8adbe --- /dev/null +++ b/drivers/vcodec/venc_hivna/hal_venc.c @@ -0,0 +1,3296 @@ +#include "venc_regulator.h" +#include "drv_venc_efl.h" +#include "drv_venc_osal.h" +#include "hi_drv_mem.h" +#include "drv_venc.h" +#include +#include + + +/*lint -e438 -e838 -e826*/ + +#define DIST_PROTOCOL(protocol, value1, value2) ((VEDU_H265 == protocol) ? (value1) : (value2)) + +extern VENC_SMMU_ERR_ADDR g_smmu_err_mem; +extern VeduEfl_IpCtx_S VeduIpCtx; +extern struct iommu_domain* g_hisi_mmu_domain; + +void VENC_HAL_ClrAllInt(S_HEVC_AVC_REGS_TYPE *pVeduReg) +{ + pVeduReg->VEDU_VCPI_INTCLR.u32 = 0xFFFFFFFF; +} + +void VENC_HAL_DisableAllInt(S_HEVC_AVC_REGS_TYPE *pVeduReg) +{ + pVeduReg->VEDU_VCPI_INTMASK.u32 = 0; +} + +int VENC_HAL_ResetReg() +{ +#if 0// del by xwx495457 + int s32Ret = HI_FAILURE; + s32Ret = Venc_Regulator_Disable(); + s32Ret |= Venc_Regulator_Enable(); + return s32Ret; +#endif + return HI_SUCCESS; +} + +void VENC_HAL_SetSmmuAddr(S_HEVC_AVC_REGS_TYPE *pVeduReg) +{ + pVeduReg->SMMU_ERR_RDADDR = g_smmu_err_mem.RdAddr & 0xFFFFFFFF;//config alloc phyaddr,in order system don't dump + pVeduReg->SMMU_ADDR_MSB.bits.msb_errrd = (g_smmu_err_mem.RdAddr >> 32)&0x7F; + pVeduReg->SMMU_ERR_WRADDR[0] = g_smmu_err_mem.WrAddr & 0xFFFFFFFF; + pVeduReg->SMMU_ADDR_MSB.bits.msb_errwr = (g_smmu_err_mem.WrAddr >> 32)&0x7F; +} + +void VENC_HAL_StartEncode(S_HEVC_AVC_REGS_TYPE *pVeduReg) +{ + if (pVeduReg) { + pVeduReg->VEDU_VCPI_START.bits.vcpi_vstart = 0; + pVeduReg->VEDU_VCPI_START.bits.vcpi_vstart = 1; + } +} + +void VENC_HAL_Get_CfgRegSimple(VENC_REG_INFO_S *pVeduReg) +{ + S_HEVC_AVC_REGS_TYPE * pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + pVeduReg->all_reg.FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop; + pVeduReg->all_reg.FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_buffull = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_buffull; + + pVeduReg->all_reg.FUNC_VLCST_DSRPTR00.bits.slc_len0 = pAllReg->FUNC_VLCST_DSRPTR00.bits.slc_len0; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR10.bits.slc_len1 = pAllReg->FUNC_VLCST_DSRPTR10.bits.slc_len1; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR20.bits.slc_len2 = pAllReg->FUNC_VLCST_DSRPTR20.bits.slc_len2; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR30.bits.slc_len3 = pAllReg->FUNC_VLCST_DSRPTR30.bits.slc_len3; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR40.bits.slc_len4 = pAllReg->FUNC_VLCST_DSRPTR40.bits.slc_len4; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR50.bits.slc_len5 = pAllReg->FUNC_VLCST_DSRPTR50.bits.slc_len5; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR60.bits.slc_len6 = pAllReg->FUNC_VLCST_DSRPTR60.bits.slc_len6; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR70.bits.slc_len7 = pAllReg->FUNC_VLCST_DSRPTR70.bits.slc_len7; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR80.bits.slc_len8 = pAllReg->FUNC_VLCST_DSRPTR80.bits.slc_len8; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR90.bits.slc_len9 = pAllReg->FUNC_VLCST_DSRPTR90.bits.slc_len9; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR100.bits.slc_len10 = pAllReg->FUNC_VLCST_DSRPTR100.bits.slc_len10; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR110.bits.slc_len11 = pAllReg->FUNC_VLCST_DSRPTR110.bits.slc_len11; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR120.bits.slc_len12 = pAllReg->FUNC_VLCST_DSRPTR120.bits.slc_len12; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR130.bits.slc_len13 = pAllReg->FUNC_VLCST_DSRPTR130.bits.slc_len13; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR140.bits.slc_len14 = pAllReg->FUNC_VLCST_DSRPTR140.bits.slc_len14; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR150.bits.slc_len15 = pAllReg->FUNC_VLCST_DSRPTR150.bits.slc_len15; + + pVeduReg->all_reg.FUNC_VLCST_DSRPTR01.bits.invalidnum0 = pAllReg->FUNC_VLCST_DSRPTR01.bits.invalidnum0; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR11.bits.invalidnum1 = pAllReg->FUNC_VLCST_DSRPTR11.bits.invalidnum1; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR21.bits.invalidnum2 = pAllReg->FUNC_VLCST_DSRPTR21.bits.invalidnum2; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR31.bits.invalidnum3 = pAllReg->FUNC_VLCST_DSRPTR31.bits.invalidnum3; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR41.bits.invalidnum4 = pAllReg->FUNC_VLCST_DSRPTR41.bits.invalidnum4; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR51.bits.invalidnum5 = pAllReg->FUNC_VLCST_DSRPTR51.bits.invalidnum5; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR61.bits.invalidnum6 = pAllReg->FUNC_VLCST_DSRPTR61.bits.invalidnum6; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR71.bits.invalidnum7 = pAllReg->FUNC_VLCST_DSRPTR71.bits.invalidnum7; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR81.bits.invalidnum8 = pAllReg->FUNC_VLCST_DSRPTR81.bits.invalidnum8; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR91.bits.invalidnum9 = pAllReg->FUNC_VLCST_DSRPTR91.bits.invalidnum9; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR101.bits.invalidnum10 = pAllReg->FUNC_VLCST_DSRPTR101.bits.invalidnum10; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR111.bits.invalidnum11 = pAllReg->FUNC_VLCST_DSRPTR111.bits.invalidnum11; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR121.bits.invalidnum12 = pAllReg->FUNC_VLCST_DSRPTR121.bits.invalidnum12; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR131.bits.invalidnum13 = pAllReg->FUNC_VLCST_DSRPTR131.bits.invalidnum13 ; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR141.bits.invalidnum14 = pAllReg->FUNC_VLCST_DSRPTR141.bits.invalidnum14; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR151.bits.invalidnum15 = pAllReg->FUNC_VLCST_DSRPTR151.bits.invalidnum15; +} + +void VENC_HAL_Get_Reg_Venc(VENC_REG_INFO_S *pVeduReg) +{ + S_HEVC_AVC_REGS_TYPE * pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase;/*lint !e826 */ + + pVeduReg->all_reg.FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_eop; + pVeduReg->all_reg.FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_buffull = pAllReg->FUNC_VCPI_RAWINT.bits.vcpi_rint_ve_buffull; + + pVeduReg->all_reg.FUNC_CABAC_PIC_STRMSIZE = pAllReg->FUNC_CABAC_PIC_STRMSIZE; + pVeduReg->all_reg.FUNC_SEL_OPT_4X4_CNT.bits.opt_4x4_cnt = pAllReg->FUNC_SEL_OPT_4X4_CNT.bits.opt_4x4_cnt; + pVeduReg->all_reg.FUNC_SEL_INTRA_OPT_8X8_CNT.bits.intra_opt_8x8_cnt = pAllReg->FUNC_SEL_INTRA_OPT_8X8_CNT.bits.intra_opt_8x8_cnt; + pVeduReg->all_reg.FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT.bits.intra_normal_opt_8x8_cnt = pAllReg->FUNC_SEL_INTRA_NORMAL_OPT_8X8_CNT.bits.intra_normal_opt_8x8_cnt; + pVeduReg->all_reg.FUNC_SEL_INTRA_OPT_16X16_CNT.bits.intra_opt_16x16_cnt = pAllReg->FUNC_SEL_INTRA_OPT_16X16_CNT.bits.intra_opt_16x16_cnt; + pVeduReg->all_reg.FUNC_SEL_INTRA_OPT_32X32_CNT.bits.intra_opt_32x32_cnt = pAllReg->FUNC_SEL_INTRA_OPT_32X32_CNT.bits.intra_opt_32x32_cnt; + + pVeduReg->all_reg.VLC_PIC_TTBITS = pAllReg->VLC_PIC_TTBITS; + pVeduReg->all_reg.FUNC_SEL_INTRA_PCM_OPT_8X8_CNT.bits.pcm_opt_8x8_cnt = pAllReg->FUNC_SEL_INTRA_PCM_OPT_8X8_CNT.bits.pcm_opt_8x8_cnt; + //pVeduReg->all_reg.FUNC_SEL_INTRA_OPT_16X16_CNT.bits.intra_opt_16x16_cnt = pAllReg->FUNC_SEL_INTRA_OPT_16X16_CNT.bits.intra_opt_16x16_cnt;//?ظ? + pVeduReg->all_reg.FUNC_PME_MADI_SUM = pAllReg->FUNC_PME_MADI_SUM; + + pVeduReg->all_reg.FUNC_VLCST_DSRPTR00.bits.slc_len0 = pAllReg->FUNC_VLCST_DSRPTR00.bits.slc_len0; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR10.bits.slc_len1 = pAllReg->FUNC_VLCST_DSRPTR10.bits.slc_len1; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR20.bits.slc_len2 = pAllReg->FUNC_VLCST_DSRPTR20.bits.slc_len2; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR30.bits.slc_len3 = pAllReg->FUNC_VLCST_DSRPTR30.bits.slc_len3; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR40.bits.slc_len4 = pAllReg->FUNC_VLCST_DSRPTR40.bits.slc_len4; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR50.bits.slc_len5 = pAllReg->FUNC_VLCST_DSRPTR50.bits.slc_len5; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR60.bits.slc_len6 = pAllReg->FUNC_VLCST_DSRPTR60.bits.slc_len6; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR70.bits.slc_len7 = pAllReg->FUNC_VLCST_DSRPTR70.bits.slc_len7; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR80.bits.slc_len8 = pAllReg->FUNC_VLCST_DSRPTR80.bits.slc_len8; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR90.bits.slc_len9 = pAllReg->FUNC_VLCST_DSRPTR90.bits.slc_len9; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR100.bits.slc_len10 = pAllReg->FUNC_VLCST_DSRPTR100.bits.slc_len10; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR110.bits.slc_len11 = pAllReg->FUNC_VLCST_DSRPTR110.bits.slc_len11; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR120.bits.slc_len12 = pAllReg->FUNC_VLCST_DSRPTR120.bits.slc_len12; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR130.bits.slc_len13 = pAllReg->FUNC_VLCST_DSRPTR130.bits.slc_len13; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR140.bits.slc_len14 = pAllReg->FUNC_VLCST_DSRPTR140.bits.slc_len14; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR150.bits.slc_len15 = pAllReg->FUNC_VLCST_DSRPTR150.bits.slc_len15; + + pVeduReg->all_reg.FUNC_VLCST_DSRPTR01.bits.invalidnum0 = pAllReg->FUNC_VLCST_DSRPTR01.bits.invalidnum0; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR11.bits.invalidnum1 = pAllReg->FUNC_VLCST_DSRPTR11.bits.invalidnum1; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR21.bits.invalidnum2 = pAllReg->FUNC_VLCST_DSRPTR21.bits.invalidnum2; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR31.bits.invalidnum3 = pAllReg->FUNC_VLCST_DSRPTR31.bits.invalidnum3; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR41.bits.invalidnum4 = pAllReg->FUNC_VLCST_DSRPTR41.bits.invalidnum4; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR51.bits.invalidnum5 = pAllReg->FUNC_VLCST_DSRPTR51.bits.invalidnum5; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR61.bits.invalidnum6 = pAllReg->FUNC_VLCST_DSRPTR61.bits.invalidnum6; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR71.bits.invalidnum7 = pAllReg->FUNC_VLCST_DSRPTR71.bits.invalidnum7; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR81.bits.invalidnum8 = pAllReg->FUNC_VLCST_DSRPTR81.bits.invalidnum8; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR91.bits.invalidnum9 = pAllReg->FUNC_VLCST_DSRPTR91.bits.invalidnum9; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR101.bits.invalidnum10 = pAllReg->FUNC_VLCST_DSRPTR101.bits.invalidnum10; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR111.bits.invalidnum11 = pAllReg->FUNC_VLCST_DSRPTR111.bits.invalidnum11; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR121.bits.invalidnum12 = pAllReg->FUNC_VLCST_DSRPTR121.bits.invalidnum12; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR131.bits.invalidnum13 = pAllReg->FUNC_VLCST_DSRPTR131.bits.invalidnum13 ; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR141.bits.invalidnum14 = pAllReg->FUNC_VLCST_DSRPTR141.bits.invalidnum14; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR151.bits.invalidnum15 = pAllReg->FUNC_VLCST_DSRPTR151.bits.invalidnum15; + + pVeduReg->all_reg.FUNC_VLCST_DSRPTR01.bits.islastslc0 = pAllReg->FUNC_VLCST_DSRPTR01.bits.islastslc0; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR11.bits.islastslc1 = pAllReg->FUNC_VLCST_DSRPTR11.bits.islastslc1; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR21.bits.islastslc2 = pAllReg->FUNC_VLCST_DSRPTR21.bits.islastslc2; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR31.bits.islastslc3 = pAllReg->FUNC_VLCST_DSRPTR31.bits.islastslc3; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR41.bits.islastslc4 = pAllReg->FUNC_VLCST_DSRPTR41.bits.islastslc4; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR51.bits.islastslc5 = pAllReg->FUNC_VLCST_DSRPTR51.bits.islastslc5; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR61.bits.islastslc6 = pAllReg->FUNC_VLCST_DSRPTR61.bits.islastslc6; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR71.bits.islastslc7 = pAllReg->FUNC_VLCST_DSRPTR71.bits.islastslc7; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR81.bits.islastslc8 = pAllReg->FUNC_VLCST_DSRPTR81.bits.islastslc8; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR91.bits.islastslc9 = pAllReg->FUNC_VLCST_DSRPTR91.bits.islastslc9; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR101.bits.islastslc10 = pAllReg->FUNC_VLCST_DSRPTR101.bits.islastslc10; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR111.bits.islastslc11 = pAllReg->FUNC_VLCST_DSRPTR111.bits.islastslc11; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR121.bits.islastslc12 = pAllReg->FUNC_VLCST_DSRPTR121.bits.islastslc12; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR131.bits.islastslc13 = pAllReg->FUNC_VLCST_DSRPTR131.bits.islastslc13; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR141.bits.islastslc14 = pAllReg->FUNC_VLCST_DSRPTR141.bits.islastslc14; + pVeduReg->all_reg.FUNC_VLCST_DSRPTR151.bits.islastslc15 = pAllReg->FUNC_VLCST_DSRPTR151.bits.islastslc15; + + pVeduReg->all_reg.FUNC_SAO_LCU_CNT.bits.sao_lcu_cnt = pAllReg->FUNC_SAO_LCU_CNT.bits.sao_lcu_cnt; + pVeduReg->all_reg.FUNC_SAO_OFF_NUM.bits.saooff_chroma_num = pAllReg->FUNC_SAO_OFF_NUM.bits.saooff_chroma_num; + pVeduReg->all_reg.FUNC_SAO_OFF_NUM.bits.saooff_luma_num = pAllReg->FUNC_SAO_OFF_NUM.bits.saooff_luma_num; + + pVeduReg->all_reg.FUNC_VCPI_VEDU_TIMER = pAllReg->FUNC_VCPI_VEDU_TIMER; + pVeduReg->all_reg.FUNC_VCPI_IDLE_TIMER = pAllReg->FUNC_VCPI_IDLE_TIMER; + +} +void VeduHal_CfgReg_IntraSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_0.u32 = channelcfg->all_reg.VEDU_VCTRL_INTRA_RDO_FACTOR_0.u32; + + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_1.u32 = channelcfg->all_reg.VEDU_VCTRL_INTRA_RDO_FACTOR_1.u32; + + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_2.u32 = channelcfg->all_reg.VEDU_VCTRL_INTRA_RDO_FACTOR_2.u32; + + pAllReg->VEDU_PME_NEW_COST.bits.pme_new_cost_en = channelcfg->all_reg.VEDU_PME_NEW_COST.bits.pme_new_cost_en; + +} + +void VeduHal_CfgReg_LambdaSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + //lambd reg cfg set + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG00.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG00.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG01.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG01.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG02.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG02.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG03.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG03.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG04.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG04.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG05.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG05.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG06.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG06.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG07.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG07.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG08.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG08.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG09.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG09.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG10.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG10.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG11.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG11.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG12.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG12.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG13.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG13.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG14.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG14.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG15.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG15.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG16.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG16.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG17.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG17.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG18.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG18.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG19.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG19.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG20.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG20.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG21.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG21.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG22.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG22.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG23.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG23.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG24.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG24.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG25.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG25.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG26.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG26.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG27.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG27.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG28.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG28.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG29.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG29.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG30.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG30.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG31.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG31.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG32.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG32.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG33.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG33.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG34.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG34.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG35.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG35.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG36.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG36.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG37.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG37.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG38.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG38.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG39.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG39.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG40.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG40.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG41.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG41.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG42.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG42.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG43.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG43.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG44.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG44.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG45.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG45.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG46.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG46.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG47.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG47.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG48.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG48.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG49.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG49.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG50.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG50.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG51.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG51.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG52.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG52.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG53.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG53.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG54.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG54.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG55.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG55.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG56.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG56.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG57.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG57.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG58.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG58.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG59.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG59.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG60.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG60.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG61.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG61.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG62.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG62.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG63.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG63.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG64.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG64.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG65.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG65.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG66.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG66.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG67.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG67.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG68.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG68.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG69.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG69.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG70.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG70.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG71.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG71.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG72.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG72.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG73.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG73.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG74.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG74.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG75.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG75.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG76.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG76.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG77.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG77.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG78.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG78.u32; + } + + { + pAllReg->VEDU_QPG_QP_LAMBDA_CTRL_REG79.u32 = channelcfg->all_reg.VEDU_QPG_QP_LAMBDA_CTRL_REG79.u32; + } + +} +void VeduHal_CfgReg_QpgmapSet(VENC_REG_INFO_S *channelcfg ) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + { + pAllReg->VEDU_VCTRL_ROI_CFG0.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_CFG0.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_CFG1.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_CFG1.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_CFG2.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_CFG2.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_0.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_0.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_1.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_1.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_2.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_2.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_3.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_3.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_4.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_4.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_5.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_5.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_6.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_6.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_SIZE_7.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_SIZE_7.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_0.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_0.u32; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_1.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_1.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_2.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_2.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_3.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_3.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_4.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_4.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_5.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_5.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_6.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_6.u32;; + } + + { + pAllReg->VEDU_VCTRL_ROI_START_7.u32 = channelcfg->all_reg.VEDU_VCTRL_ROI_START_7.u32;; + } + + { + pAllReg->VEDU_VCPI_RC_ENABLE.u32 = channelcfg->all_reg.VEDU_VCPI_RC_ENABLE.u32; + } + + { + pAllReg->VEDU_QPG_SMART_REG.u32 = channelcfg->all_reg.VEDU_QPG_SMART_REG.u32; + } + +} +void VeduHal_CfgReg_AddrSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + HI_DBG_VENC("set Vedu Hal cfg reg addr\n"); + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + //Col_frm_flag PMC_POC And So On; I P B All need to Cfg + { + pAllReg->VEDU_VCPI_STRFMT.u32 = channelcfg->all_reg.VEDU_VCPI_STRFMT.u32; + } + + { + pAllReg->VEDU_VCPI_REF_FLAG.u32 = channelcfg->all_reg.VEDU_VCPI_REF_FLAG.u32; + } + + { + pAllReg->VEDU_PMV_POC_0 = channelcfg->all_reg.VEDU_PMV_POC_0; + } + { + pAllReg->VEDU_PMV_POC_1 = channelcfg->all_reg.VEDU_PMV_POC_1; + } + { + pAllReg->VEDU_PMV_POC_2 = channelcfg->all_reg.VEDU_PMV_POC_2; + } + { + pAllReg->VEDU_PMV_POC_3 = channelcfg->all_reg.VEDU_PMV_POC_3; + } + { + pAllReg->VEDU_PMV_POC_4 = channelcfg->all_reg.VEDU_PMV_POC_4; + } + { + pAllReg->VEDU_PMV_POC_5 = channelcfg->all_reg.VEDU_PMV_POC_5; + } + + pAllReg->VEDU_VCPI_TUNLCELL_ADDR = channelcfg->all_reg.VEDU_VCPI_TUNLCELL_ADDR;//pEncPara_channel->VEDU_SRC_YADDR;//pEncPara->vcpi_curld_tunlcell_addr; + pAllReg->VEDU_VCPI_SRC_YADDR = channelcfg->all_reg.VEDU_VCPI_SRC_YADDR;//pEncPara_channel->VEDU_SRC_YADDR;//pEncPara->vcpi_curld_y_addr; + pAllReg->VEDU_VCPI_SRC_CADDR = channelcfg->all_reg.VEDU_VCPI_SRC_CADDR;//pEncPara_channel->VEDU_SRC_CADDR;//pEncPara->vcpi_curld_c_addr; + pAllReg->VEDU_VCPI_SRC_VADDR = channelcfg->all_reg.VEDU_VCPI_SRC_VADDR;//pEncPara_channel->VEDU_SRC_VADDR;//pEncPara->vcpi_curld_v_addr; + + { + pAllReg->VEDU_VCPI_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_STRIDE.u32; + } + HI_DBG_VENC("reg VEDU_VCPI_SRC_YADDR:%pK\n", (void *)(uintptr_t)(channelcfg->all_reg.VEDU_VCPI_SRC_YADDR)); + HI_DBG_VENC("reg VEDU_VCPI_SRC_CADDR:%pK\n", (void *)(uintptr_t)(channelcfg->all_reg.VEDU_VCPI_SRC_CADDR)); + HI_DBG_VENC("reg VEDU_VCPI_SRC_VADDR:%pK\n", (void *)(uintptr_t)(channelcfg->all_reg.VEDU_VCPI_SRC_VADDR)); + HI_DBG_VENC("reg vcpi_curld_c_stride:%x\n", channelcfg->all_reg.VEDU_VCPI_STRIDE.bits.vcpi_curld_c_stride); + HI_DBG_VENC("reg vcpi_curld_y_stride:%x\n", channelcfg->all_reg.VEDU_VCPI_STRIDE.bits.vcpi_curld_y_stride); + if(channelcfg->all_reg.VEDU_VCPI_STRFMT.bits.vcpi_str_fmt == 10) + { + pAllReg->VEDU_VCPI_YH_ADDR = channelcfg->all_reg.VEDU_VCPI_YH_ADDR;//pEncPara->vcpi_curld_yh_addr; + pAllReg->VEDU_VCPI_CH_ADDR = channelcfg->all_reg.VEDU_VCPI_CH_ADDR;//pEncPara->vcpi_curld_ch_addr; + { + pAllReg->VEDU_CURLD_SRCH_STRIDE.u32 = channelcfg->all_reg.VEDU_CURLD_SRCH_STRIDE.u32; + } + + { + pAllReg->VEDU_CURLD_HFBCD.u32 = channelcfg->all_reg.VEDU_CURLD_HFBCD.u32; + } + HI_DBG_VENC("reg VEDU_VCPI_CH_ADDR=%pK\n", (void *)(uintptr_t)(channelcfg->all_reg.VEDU_VCPI_YH_ADDR)); + HI_DBG_VENC("reg VEDU_VCPI_CH_ADDR=%pK\n", (void *)(uintptr_t)(channelcfg->all_reg.VEDU_VCPI_CH_ADDR)); + HI_DBG_VENC("reg vcpi_curld_srcch_stride=%x\n", channelcfg->all_reg.VEDU_CURLD_SRCH_STRIDE.bits.vcpi_curld_srcch_stride); + HI_DBG_VENC("reg vcpi_curld_srcyh_stride=%x\n", channelcfg->all_reg.VEDU_CURLD_SRCH_STRIDE.bits.vcpi_curld_srcyh_stride); + } + + //----------------------------------------------------------------------------------------- + //-------------------REC,REF0,REF1,PME0,PME1,NBI Relate ADDR Stide----------------------- + // + //REC-------------------REC-----------------REC-------------------------------------------- + pAllReg->VEDU_VCPI_REC_YADDR = channelcfg->all_reg.VEDU_VCPI_REC_YADDR;//pEncPara->vcpi_recst_yaddr; + pAllReg->VEDU_VCPI_REC_CADDR = channelcfg->all_reg.VEDU_VCPI_REC_CADDR;//pEncPara->vcpi_recst_caddr; + { + pAllReg->VEDU_VCPI_REC_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REC_STRIDE.u32; + } + + pAllReg->VEDU_VCPI_REC_YH_ADDR = channelcfg->all_reg.VEDU_VCPI_REC_YH_ADDR;//pEncPara->vcpi_recst_yh_addr; + pAllReg->VEDU_VCPI_REC_CH_ADDR = channelcfg->all_reg.VEDU_VCPI_REC_CH_ADDR;//pEncPara->vcpi_recst_ch_addr; + { + pAllReg->VEDU_VCPI_REC_HEAD_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REC_HEAD_STRIDE.u32; + } + // + //REF-------------------REF-----------------REF-------------------------------------------- + //REF0 + + pAllReg->VEDU_VCPI_REFY_L0_ADDR = channelcfg->all_reg.VEDU_VCPI_REFY_L0_ADDR; + pAllReg->VEDU_VCPI_REFC_L0_ADDR = channelcfg->all_reg.VEDU_VCPI_REFC_L0_ADDR; + { + pAllReg->VEDU_VCPI_REF_L0_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REF_L0_STRIDE.u32; + } + pAllReg->VEDU_VCPI_REFYH_L0_ADDR = channelcfg->all_reg.VEDU_VCPI_REFYH_L0_ADDR; + pAllReg->VEDU_VCPI_REFCH_L0_ADDR = channelcfg->all_reg.VEDU_VCPI_REFCH_L0_ADDR; + + { + pAllReg->VEDU_VCPI_REFH_L0_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REFH_L0_STRIDE.u32; + } + + pAllReg->VEDU_VCPI_PMELD_L0_ADDR = channelcfg->all_reg.VEDU_VCPI_PMELD_L0_ADDR; + //REF1 + + pAllReg->VEDU_VCPI_REFY_L1_ADDR = channelcfg->all_reg.VEDU_VCPI_REFY_L1_ADDR;//pEncPara_channel->VEDU_REFY_L1_ADDR; + pAllReg->VEDU_VCPI_REFC_L1_ADDR = channelcfg->all_reg.VEDU_VCPI_REFC_L1_ADDR;//pEncPara_channel->VEDU_REFC_L1_ADDR; + { + pAllReg->VEDU_VCPI_REF_L1_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REF_L1_STRIDE.u32; + } + + pAllReg->VEDU_VCPI_REFYH_L1_ADDR = channelcfg->all_reg.VEDU_VCPI_REFYH_L1_ADDR;//pEncPara_channel->VEDU_REFYH_L1_ADDR; + pAllReg->VEDU_VCPI_REFCH_L1_ADDR = channelcfg->all_reg.VEDU_VCPI_REFCH_L1_ADDR;//pEncPara_channel->VEDU_REFCH_L1_ADDR; + + { + pAllReg->VEDU_VCPI_REFH_L1_STRIDE.u32 = channelcfg->all_reg.VEDU_VCPI_REFH_L1_STRIDE.u32; + } + pAllReg->VEDU_VCPI_PMELD_L1_ADDR = channelcfg->all_reg.VEDU_VCPI_PMELD_L1_ADDR;//pEncPara_channel->VEDU_PMELD_L1_ADDR; + + //PME NBI + + pAllReg->VEDU_VCPI_PMEST_ADDR = channelcfg->all_reg.VEDU_VCPI_PMEST_ADDR;//pEncPara->vcpi_pmest_addr; + + pAllReg->VEDU_VCPI_PMEST_STRIDE = channelcfg->all_reg.VEDU_VCPI_PMEST_STRIDE; + + pAllReg->VEDU_VCPI_PMELD_STRIDE = channelcfg->all_reg.VEDU_VCPI_PMELD_STRIDE; + + //NBI + //{ + // U_VEDU_VCPI_NBI_UPST_ADDR D32; + // D32.bits.vcpi_upst_address = pEncPara->vcpi_upst_address; + // pAllReg->VEDU_VCPI_NBI_UPST_ADDR = channelcfg->all_reg..u32; + //} + + pAllReg->VEDU_VCPI_NBI_MVST_ADDR = channelcfg->all_reg.VEDU_VCPI_NBI_MVST_ADDR;//pEncPara->vcpi_mvst_address; + pAllReg->VEDU_VCPI_NBI_MVLD_ADDR = channelcfg->all_reg.VEDU_VCPI_NBI_MVLD_ADDR;//pEncPara->vcpi_mvld_address; + // + //PMEINFO + pAllReg->VEDU_VCPI_PMEINFO_ST_ADDR = channelcfg->all_reg.VEDU_VCPI_PMEINFO_ST_ADDR;//pEncPara->vcpi_pmest_info_addr; + pAllReg->VEDU_VCPI_PMEINFO_LD0_ADDR = channelcfg->all_reg.VEDU_VCPI_PMEINFO_LD0_ADDR;//pEncPara->vcpi_pmeinfo_ld_0_addr; + pAllReg->VEDU_VCPI_PMEINFO_LD1_ADDR = channelcfg->all_reg.VEDU_VCPI_PMEINFO_LD1_ADDR;//pEncPara_channel->VEDU_PMEINFO_LD1_ADDR;//pEncPara->vcpi_pmeinfo_ld_1_addr; + //QPGLD + pAllReg->VEDU_VCPI_QPGLD_INF_ADDR = channelcfg->all_reg.VEDU_VCPI_QPGLD_INF_ADDR;//pEncPara->vcpi_qpgld_inf_addr; + // + // +} +// +// +void VeduHal_CfgReg_SlcHeadSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + HI_DBG_VENC("set Vedu Hal SlcHead\n"); + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + //----------------------------Stream head info------------------------------------------ + pAllReg->VEDU_VLCST_STRMBUFLEN0 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN0; + pAllReg->VEDU_VLCST_STRMBUFLEN1 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN1; + pAllReg->VEDU_VLCST_STRMBUFLEN2 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN2; + pAllReg->VEDU_VLCST_STRMBUFLEN3 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN3; + pAllReg->VEDU_VLCST_STRMBUFLEN4 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN4; + pAllReg->VEDU_VLCST_STRMBUFLEN5 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN5; + pAllReg->VEDU_VLCST_STRMBUFLEN6 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN6; + pAllReg->VEDU_VLCST_STRMBUFLEN7 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN7; + pAllReg->VEDU_VLCST_STRMBUFLEN8 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN8; + pAllReg->VEDU_VLCST_STRMBUFLEN9 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN9; + pAllReg->VEDU_VLCST_STRMBUFLEN10 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN10; + pAllReg->VEDU_VLCST_STRMBUFLEN11 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN11; + pAllReg->VEDU_VLCST_STRMBUFLEN12 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN12; + pAllReg->VEDU_VLCST_STRMBUFLEN13 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN13; + pAllReg->VEDU_VLCST_STRMBUFLEN14 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN14; + pAllReg->VEDU_VLCST_STRMBUFLEN15 = channelcfg->all_reg.VEDU_VLCST_STRMBUFLEN15; + pAllReg->VEDU_VLCST_STRMADDR0 = channelcfg->all_reg.VEDU_VLCST_STRMADDR0; + pAllReg->VEDU_VLCST_STRMADDR1 = channelcfg->all_reg.VEDU_VLCST_STRMADDR1; + pAllReg->VEDU_VLCST_STRMADDR2 = channelcfg->all_reg.VEDU_VLCST_STRMADDR2; + pAllReg->VEDU_VLCST_STRMADDR3 = channelcfg->all_reg.VEDU_VLCST_STRMADDR3; + pAllReg->VEDU_VLCST_STRMADDR4 = channelcfg->all_reg.VEDU_VLCST_STRMADDR4; + pAllReg->VEDU_VLCST_STRMADDR5 = channelcfg->all_reg.VEDU_VLCST_STRMADDR5; + pAllReg->VEDU_VLCST_STRMADDR6 = channelcfg->all_reg.VEDU_VLCST_STRMADDR6; + pAllReg->VEDU_VLCST_STRMADDR7 = channelcfg->all_reg.VEDU_VLCST_STRMADDR7; + pAllReg->VEDU_VLCST_STRMADDR8 = channelcfg->all_reg.VEDU_VLCST_STRMADDR8; + pAllReg->VEDU_VLCST_STRMADDR9 = channelcfg->all_reg.VEDU_VLCST_STRMADDR9; + pAllReg->VEDU_VLCST_STRMADDR10 = channelcfg->all_reg.VEDU_VLCST_STRMADDR10; + pAllReg->VEDU_VLCST_STRMADDR11 = channelcfg->all_reg.VEDU_VLCST_STRMADDR11; + pAllReg->VEDU_VLCST_STRMADDR12 = channelcfg->all_reg.VEDU_VLCST_STRMADDR12; + pAllReg->VEDU_VLCST_STRMADDR13 = channelcfg->all_reg.VEDU_VLCST_STRMADDR13; + pAllReg->VEDU_VLCST_STRMADDR14 = channelcfg->all_reg.VEDU_VLCST_STRMADDR14; + pAllReg->VEDU_VLCST_STRMADDR15 = channelcfg->all_reg.VEDU_VLCST_STRMADDR15; + + { + pAllReg->VEDU_CABAC_GLB_CFG.u32 = channelcfg->all_reg.VEDU_CABAC_GLB_CFG.u32; + } + + { + pAllReg->VEDU_CABAC_SLCHDR_SIZE.u32 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_SIZE.u32; + } + + pAllReg->VEDU_CABAC_SLCHDR_PART1.bits.cabac_slchdr_part1 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART1.bits.cabac_slchdr_part1; + + { + pAllReg->VEDU_VCPI_VLC_CONFIG.u32 = channelcfg->all_reg.VEDU_VCPI_VLC_CONFIG.u32; + } + + //if (pEncPara_channel->vcpi_protocol== VEDU_H265) //add by m00218451 + if (channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_protocol == VEDU_H265) //add by m00218451 + { + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG1 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG1; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG2 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG2; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG3 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG3; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG4 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG4; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG5 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG5; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG6 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG6; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG7 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG7; + pAllReg->VEDU_CABAC_SLCHDR_PART2_SEG8 = channelcfg->all_reg.VEDU_CABAC_SLCHDR_PART2_SEG8; + } + else + { + pAllReg->VEDU_VLC_SLCHDRSTRM0 = channelcfg->all_reg.VEDU_VLC_SLCHDRSTRM0; + pAllReg->VEDU_VLC_SLCHDRSTRM1 = channelcfg->all_reg.VEDU_VLC_SLCHDRSTRM1; + pAllReg->VEDU_VLC_SLCHDRSTRM2 = channelcfg->all_reg.VEDU_VLC_SLCHDRSTRM2; + pAllReg->VEDU_VLC_SLCHDRSTRM3 = channelcfg->all_reg.VEDU_VLC_SLCHDRSTRM3; + pAllReg->VEDU_VLC_REORDERSTRM0 = channelcfg->all_reg.VEDU_VLC_REORDERSTRM0; + pAllReg->VEDU_VLC_REORDERSTRM1 = channelcfg->all_reg.VEDU_VLC_REORDERSTRM1; + pAllReg->VEDU_VLC_MARKINGSTRM0 = channelcfg->all_reg.VEDU_VLC_MARKINGSTRM0; + pAllReg->VEDU_VLC_MARKINGSTRM1 = channelcfg->all_reg.VEDU_VLC_MARKINGSTRM1; + + { + pAllReg->VEDU_VLC_SLCHDRPARA.u32 = channelcfg->all_reg.VEDU_VLC_SLCHDRPARA.u32; + } + + { + pAllReg->VEDU_VLC_SVC.u32 = channelcfg->all_reg.VEDU_VLC_SVC.u32; + } + } + //----------------------------Cabac/Vlc Stream Head info end------------------------- + { +#ifdef HARDWARE_SPLIT_SPS_PPS_EN + if (channelcfg->bFirstNal2Send) + { + pAllReg->VEDU_VLCST_PARA_ADDR = channelcfg->all_reg.VEDU_VLCST_PARA_ADDR; + } +#endif + + pAllReg->VEDU_VLCST_PARAMETER.u32 = channelcfg->all_reg.VEDU_VLCST_PARAMETER.u32; + } + if (channelcfg->all_reg.VEDU_VLCST_PARAMETER.bits.vlcst_para_set_en == 1) + { + //pEncPara_channel->vlcst_para_set_en = 0; + pAllReg->VEDU_VLCST_PARA_DATA0 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA0; + pAllReg->VEDU_VLCST_PARA_DATA1 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA1; + pAllReg->VEDU_VLCST_PARA_DATA2 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA2; + pAllReg->VEDU_VLCST_PARA_DATA3 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA3; + pAllReg->VEDU_VLCST_PARA_DATA4 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA4; + pAllReg->VEDU_VLCST_PARA_DATA5 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA5; + pAllReg->VEDU_VLCST_PARA_DATA6 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA6; + pAllReg->VEDU_VLCST_PARA_DATA7 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA7; + pAllReg->VEDU_VLCST_PARA_DATA8 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA8; + HI_DBG_VENC("reg VLCST_PARA_DATA0:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA0); + HI_DBG_VENC("reg VLCST_PARA_DATA1:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA1); + HI_DBG_VENC("reg VLCST_PARA_DATA2:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA2); + HI_DBG_VENC("reg VLCST_PARA_DATA3:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA3); + HI_DBG_VENC("reg VLCST_PARA_DATA4:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA4); + HI_DBG_VENC("reg VLCST_PARA_DATA5:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA5); + HI_DBG_VENC("reg VLCST_PARA_DATA6:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA6); + HI_DBG_VENC("reg VLCST_PARA_DATA7:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA7); + HI_DBG_VENC("reg VLCST_PARA_DATA8:0x%x\n",pAllReg->VEDU_VLCST_PARA_DATA8); + pAllReg->VEDU_VLCST_PARA_DATA9 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA9; + pAllReg->VEDU_VLCST_PARA_DATA10 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA10; + pAllReg->VEDU_VLCST_PARA_DATA11 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA11; + pAllReg->VEDU_VLCST_PARA_DATA12 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA12; + pAllReg->VEDU_VLCST_PARA_DATA13 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA13; + pAllReg->VEDU_VLCST_PARA_DATA14 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA14; + pAllReg->VEDU_VLCST_PARA_DATA15 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA15; + pAllReg->VEDU_VLCST_PARA_DATA16 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA16; + pAllReg->VEDU_VLCST_PARA_DATA17 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA17; + pAllReg->VEDU_VLCST_PARA_DATA18 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA18; + pAllReg->VEDU_VLCST_PARA_DATA19 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA19; + pAllReg->VEDU_VLCST_PARA_DATA20 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA20; + pAllReg->VEDU_VLCST_PARA_DATA21 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA21; + pAllReg->VEDU_VLCST_PARA_DATA22 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA22; + pAllReg->VEDU_VLCST_PARA_DATA23 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA23; + pAllReg->VEDU_VLCST_PARA_DATA24 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA24; + pAllReg->VEDU_VLCST_PARA_DATA25 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA25; + pAllReg->VEDU_VLCST_PARA_DATA26 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA26; + pAllReg->VEDU_VLCST_PARA_DATA27 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA27; + pAllReg->VEDU_VLCST_PARA_DATA28 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA28; + pAllReg->VEDU_VLCST_PARA_DATA29 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA29; + pAllReg->VEDU_VLCST_PARA_DATA30 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA30; + pAllReg->VEDU_VLCST_PARA_DATA31 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA31; + pAllReg->VEDU_VLCST_PARA_DATA32 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA32; + pAllReg->VEDU_VLCST_PARA_DATA33 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA33; + pAllReg->VEDU_VLCST_PARA_DATA34 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA34; + pAllReg->VEDU_VLCST_PARA_DATA35 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA35; + pAllReg->VEDU_VLCST_PARA_DATA36 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA36; + pAllReg->VEDU_VLCST_PARA_DATA37 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA37; + pAllReg->VEDU_VLCST_PARA_DATA38 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA38; + pAllReg->VEDU_VLCST_PARA_DATA39 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA39; + pAllReg->VEDU_VLCST_PARA_DATA40 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA40; + pAllReg->VEDU_VLCST_PARA_DATA41 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA41; + pAllReg->VEDU_VLCST_PARA_DATA42 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA42; + pAllReg->VEDU_VLCST_PARA_DATA43 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA43; + pAllReg->VEDU_VLCST_PARA_DATA44 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA44; + pAllReg->VEDU_VLCST_PARA_DATA45 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA45; + pAllReg->VEDU_VLCST_PARA_DATA46 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA46; + pAllReg->VEDU_VLCST_PARA_DATA47 = channelcfg->all_reg.VEDU_VLCST_PARA_DATA47; + } +} + +void VeduHal_CfgReg_SMMUSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + HI_U64 phy_pgd_base; + struct iommu_domain_data* domain_data; + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + domain_data = (struct iommu_domain_data *)(g_hisi_mmu_domain->priv); + phy_pgd_base = (HI_U64)(domain_data->phy_pgd_base); + HI_DBG_VENC("phy_pgd_base:%pK\n", (void *)(uintptr_t)phy_pgd_base); + HI_DBG_VENC("(phy_pgd_base >> 32):%pK\n", (void *)(uintptr_t)(phy_pgd_base >> 32)); + //SMRX_0 + + //QOS + pAllReg->SMMU_SCR.bits.rqos_en = 1; + pAllReg->SMMU_SCR.bits.wqos_en = 1; + pAllReg->SMMU_SCR.bits.rqos = 0; + pAllReg->SMMU_SCR.bits.wqos = 0; + + pAllReg->SMMU_CB_SCTRL.bits.cb_bypass = channelcfg->all_reg.SMMU_CB_SCTRL.bits.cb_bypass; + pAllReg->SMMU_CB_TTBCR.bits.cb_ttbcr_des = 1;//channelcfg->all_reg.SMMU_CB_TTBCR.bits.cb_ttbcr_des; + pAllReg->SMMU_CB_TTBR0 = phy_pgd_base;/*lint !e712 */ + pAllReg->SMMU_CB_TTBR1 = phy_pgd_base;/*lint !e712 */ + pAllReg->SMMU_FAMA_CTRL1_NS[0].bits.fama_ptw_msb_ns = (phy_pgd_base >> 32); + +#if 1 + if(channelcfg->bSecureFlag == 1) + { //sec + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[0].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[1].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[2].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[3].u32 = D32.u32; + } + + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[4].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 3; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[5].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[6].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[7].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 72; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[8].u32 = D32.u32; + } + + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 36; + D32.bits.len = 4; + pAllReg->SMMU_MSTR_SMRX_0[9].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[10].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[11].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 48; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[12].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 8; + D32.bits.len = 2; + pAllReg->SMMU_MSTR_SMRX_0[13].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 8; + D32.bits.len = 2; + pAllReg->SMMU_MSTR_SMRX_0[14].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[30].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[31].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[32].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[33].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[34].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 18; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[35].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 9; + D32.bits.len = 4; + pAllReg->SMMU_MSTR_SMRX_0[36].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[37].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[38].u32 = D32.u32; + } + } + else + {//nosec + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[15].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[16].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[17].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[18].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[19].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 3; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[20].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[21].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[22].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 72; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[23].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 36; + D32.bits.len = 4; + pAllReg->SMMU_MSTR_SMRX_0[24].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[25].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[26].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 48; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[27].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 8; + D32.bits.len = 2; + pAllReg->SMMU_MSTR_SMRX_0[28].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 8; + D32.bits.len = 2; + pAllReg->SMMU_MSTR_SMRX_0[29].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[39].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[40].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 1; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[41].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[42].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[43].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 18; + D32.bits.len = 8; + pAllReg->SMMU_MSTR_SMRX_0[44].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 9; + D32.bits.len = 4; + pAllReg->SMMU_MSTR_SMRX_0[45].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[46].u32 = D32.u32; + } + { + U_SMMU_MSTR_SMRX_0 D32; + D32.bits.bypass = 0; + D32.bits.upwin = 0; + D32.bits.len = 1; + pAllReg->SMMU_MSTR_SMRX_0[47].u32 = D32.u32; + } + + } +#else + if(channelcfg->bSecureFlag == 1) + { //sec + for (i = 0; i < 15; i++) + { + pAllReg->SMMU_MSTR_SMRX_0[i].u32 = channelcfg->all_reg.SMMU_MSTR_SMRX_0[i].u32; + } + for (i = 30; i < 39; i++) + { + pAllReg->SMMU_MSTR_SMRX_0[i].u32 = channelcfg->all_reg.SMMU_MSTR_SMRX_0[i].u32; + } + } + else + {//nosec + for (i = 15; i < 30; i++) + { + pAllReg->SMMU_MSTR_SMRX_0[i].u32 = channelcfg->all_reg.SMMU_MSTR_SMRX_0[i].u32; + } + //nosec + for (i = 39; i < 48; i++) + { + pAllReg->SMMU_MSTR_SMRX_0[i].u32 = channelcfg->all_reg.SMMU_MSTR_SMRX_0[i].u32; + } + } +#endif + +} + +void VeduHal_CfgReg_PREMMUSet(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + HI_DBG_VENC("MMU RRE ADDR enter\n"); + HI_DBG_VENC("MMU_PRE_NBI_MVST_ADDR_STR:%pK, SMMU_MSTR_SMRX_1[0]:%pK, MMU_PRE_STRMADDR0_STR:%pK\n", (void *)(&(pAllReg->MMU_PRE_NBI_MVST_ADDR_STR)), + (&(pAllReg->SMMU_MSTR_SMRX_1[0])), (void *)(uintptr_t)(&(pAllReg->MMU_PRE_STRMADDR0_STR))); + HI_DBG_VENC("MMU_PRE_NBI_MVST_ADDR_STR:%pK, SMMU_MSTR_SMRX_1[0]:%pK, MMU_PRE_STRMADDR0_STR:%pK\n", (void *)(&(pAllReg->MMU_PRE_NBI_MVST_ADDR_STR)), + (&(pAllReg->SMMU_MSTR_SMRX_1[0])), (void *)(uintptr_t)(&(pAllReg->MMU_PRE_STRMADDR0_STR))); + HI_DBG_VENC("MMU_PRE_NBI_MVST_ADDR_STR:%pK, SMMU_MSTR_SMRX_2[0]:%pK, MMU_PRE_STRMADDR0_STR:%pK\n", (void *)(&(pAllReg->MMU_PRE_NBI_MVST_ADDR_STR)), + (&(pAllReg->SMMU_MSTR_SMRX_2[0])), (void *)(uintptr_t)(&(pAllReg->MMU_PRE_STRMADDR0_STR))); + //////PRE_ADDR + + pAllReg->MMU_PRE_NBI_MVST_ADDR_STR = channelcfg->all_reg.MMU_PRE_NBI_MVST_ADDR_STR; + pAllReg->MMU_PRE_NBI_MVST_ADDR_END = channelcfg->all_reg.MMU_PRE_NBI_MVST_ADDR_END; + + pAllReg->MMU_PRE_NBI_MVLD_ADDR_STR = channelcfg->all_reg.MMU_PRE_NBI_MVLD_ADDR_STR; + pAllReg->MMU_PRE_NBI_MVLD_ADDR_END = channelcfg->all_reg.MMU_PRE_NBI_MVLD_ADDR_END; + + pAllReg->MMU_PRE_PMEST_ADDR_STR = channelcfg->all_reg.MMU_PRE_PMEST_ADDR_STR; + pAllReg->MMU_PRE_PMEST_ADDR_END = channelcfg->all_reg.MMU_PRE_PMEST_ADDR_END; + + pAllReg->MMU_PRE_PMELD_ADDR_STR = channelcfg->all_reg.MMU_PRE_PMELD_ADDR_STR; + pAllReg->MMU_PRE_PMELD_ADDR_END = channelcfg->all_reg.MMU_PRE_PMELD_ADDR_END; + + pAllReg->MMU_PRE_PMEINFOST_ADDR_STR = channelcfg->all_reg.MMU_PRE_PMEINFOST_ADDR_STR; + pAllReg->MMU_PRE_PMEINFOST_ADDR_END = channelcfg->all_reg.MMU_PRE_PMEINFOST_ADDR_END; + + pAllReg->MMU_PRE_PMEINFOLD0_ADDR_STR = channelcfg->all_reg.MMU_PRE_PMEINFOLD0_ADDR_STR; + pAllReg->MMU_PRE_PMEINFOLD0_ADDR_END = channelcfg->all_reg.MMU_PRE_PMEINFOLD0_ADDR_END; + + pAllReg->MMU_PRE_PMEINFOLD1_ADDR_STR = channelcfg->all_reg.MMU_PRE_PMEINFOLD1_ADDR_STR; + pAllReg->MMU_PRE_PMEINFOLD1_ADDR_END = channelcfg->all_reg.MMU_PRE_PMEINFOLD1_ADDR_END; + + pAllReg->MMU_PRE_QPGLD_ADDR_STR = channelcfg->all_reg.MMU_PRE_QPGLD_ADDR_STR; + pAllReg->MMU_PRE_QPGLD_ADDR_END = channelcfg->all_reg.MMU_PRE_QPGLD_ADDR_END; + + ////REC + pAllReg->MMU_PRE_REC_YH_ADDR_STR = channelcfg->all_reg.MMU_PRE_REC_YH_ADDR_STR; + pAllReg->MMU_PRE_REC_YH_ADDR_END = channelcfg->all_reg.MMU_PRE_REC_YH_ADDR_END; + + pAllReg->MMU_PRE_REC_CH_ADDR_STR = channelcfg->all_reg.MMU_PRE_REC_CH_ADDR_STR; + pAllReg->MMU_PRE_REC_CH_ADDR_END = channelcfg->all_reg.MMU_PRE_REC_CH_ADDR_END; + + pAllReg->MMU_PRE_REC_YADDR_STR = channelcfg->all_reg.MMU_PRE_REC_YADDR_STR; + pAllReg->MMU_PRE_REC_YADDR_END = channelcfg->all_reg.MMU_PRE_REC_YADDR_END; + + pAllReg->MMU_PRE_REC_CADDR_STR = channelcfg->all_reg.MMU_PRE_REC_CADDR_STR; + pAllReg->MMU_PRE_REC_CADDR_END = channelcfg->all_reg.MMU_PRE_REC_CADDR_END; + + ////REF + pAllReg->MMU_PRE_REF_YH_ADDR_STR = channelcfg->all_reg.MMU_PRE_REF_YH_ADDR_STR; + pAllReg->MMU_PRE_REF_YH_ADDR_END = channelcfg->all_reg.MMU_PRE_REF_YH_ADDR_END; + + pAllReg->MMU_PRE_REF_CH_ADDR_STR = channelcfg->all_reg.MMU_PRE_REF_CH_ADDR_STR; + pAllReg->MMU_PRE_REF_CH_ADDR_END = channelcfg->all_reg.MMU_PRE_REF_CH_ADDR_END; + + pAllReg->MMU_PRE_REF_YADDR_STR = channelcfg->all_reg.MMU_PRE_REF_YADDR_STR; + pAllReg->MMU_PRE_REF_YADDR_END = channelcfg->all_reg.MMU_PRE_REF_YADDR_END; + + pAllReg->MMU_PRE_REF_CADDR_STR = channelcfg->all_reg.MMU_PRE_REF_CADDR_STR; + pAllReg->MMU_PRE_REF_CADDR_END = channelcfg->all_reg.MMU_PRE_REF_CADDR_END; + + ////SRC + if(channelcfg->all_reg.VEDU_VCPI_STRFMT.bits.vcpi_str_fmt == 10) + { + pAllReg->MMU_PRE_SRC_YHADDR_STR = channelcfg->all_reg.MMU_PRE_SRC_YHADDR_STR; + pAllReg->MMU_PRE_SRC_YHADDR_END = channelcfg->all_reg.MMU_PRE_SRC_YHADDR_END; + + pAllReg->MMU_PRE_SRC_CHADDR_STR = channelcfg->all_reg.MMU_PRE_SRC_CHADDR_STR; + pAllReg->MMU_PRE_SRC_CHADDR_END = channelcfg->all_reg.MMU_PRE_SRC_CHADDR_END; + } + pAllReg->MMU_PRE_SRC_YADDR_STR = channelcfg->all_reg.MMU_PRE_SRC_YADDR_STR; + pAllReg->MMU_PRE_SRC_YADDR_END = channelcfg->all_reg.MMU_PRE_SRC_YADDR_END; + + pAllReg->MMU_PRE_SRC_CADDR_STR = channelcfg->all_reg.MMU_PRE_SRC_CADDR_STR; + pAllReg->MMU_PRE_SRC_CADDR_END = channelcfg->all_reg.MMU_PRE_SRC_CADDR_END; + + pAllReg->MMU_PRE_SRC_VADDR_STR = channelcfg->all_reg.MMU_PRE_SRC_VADDR_STR; + pAllReg->MMU_PRE_SRC_VADDR_END = channelcfg->all_reg.MMU_PRE_SRC_VADDR_END; + + ////LOWDLY + pAllReg->MMU_PRE_LOWDLY_ADDR_STR = channelcfg->all_reg.MMU_PRE_LOWDLY_ADDR_STR; + pAllReg->MMU_PRE_LOWDLY_ADDR_END = channelcfg->all_reg.MMU_PRE_LOWDLY_ADDR_END; + ////PPS +#ifdef HARDWARE_SPLIT_SPS_PPS_EN + if (channelcfg->bFirstNal2Send) + { + pAllReg->MMU_PRE_PPS_ADDR_STR = channelcfg->all_reg.MMU_PRE_PPS_ADDR_STR; + pAllReg->MMU_PRE_PPS_ADDR_END = channelcfg->all_reg.MMU_PRE_PPS_ADDR_END; + HI_DBG_VENC("MMU_PRE_PPS_ADDR_STR:%pK, MMU_PRE_PPS_ADDR_END:%pK\n", (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_STR), (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_END)); + } +#endif + + ////STREAM + pAllReg->MMU_PRE_STRMADDR0_STR = channelcfg->all_reg.MMU_PRE_STRMADDR0_STR; + pAllReg->MMU_PRE_STRMADDR0_END = channelcfg->all_reg.MMU_PRE_STRMADDR0_END; + + pAllReg->MMU_PRE_STRMADDR1_STR = channelcfg->all_reg.MMU_PRE_STRMADDR1_STR; + pAllReg->MMU_PRE_STRMADDR1_END = channelcfg->all_reg.MMU_PRE_STRMADDR1_END; + + pAllReg->MMU_PRE_STRMADDR2_STR = channelcfg->all_reg.MMU_PRE_STRMADDR2_STR; + pAllReg->MMU_PRE_STRMADDR2_END = channelcfg->all_reg.MMU_PRE_STRMADDR2_END; + + pAllReg->MMU_PRE_STRMADDR3_STR = channelcfg->all_reg.MMU_PRE_STRMADDR3_STR; + pAllReg->MMU_PRE_STRMADDR3_END = channelcfg->all_reg.MMU_PRE_STRMADDR3_END; + + pAllReg->MMU_PRE_STRMADDR4_STR = channelcfg->all_reg.MMU_PRE_STRMADDR4_STR; + pAllReg->MMU_PRE_STRMADDR4_END = channelcfg->all_reg.MMU_PRE_STRMADDR4_END; + + pAllReg->MMU_PRE_STRMADDR5_STR = channelcfg->all_reg.MMU_PRE_STRMADDR5_STR; + pAllReg->MMU_PRE_STRMADDR5_END = channelcfg->all_reg.MMU_PRE_STRMADDR5_END; + + pAllReg->MMU_PRE_STRMADDR6_STR = channelcfg->all_reg.MMU_PRE_STRMADDR6_STR; + pAllReg->MMU_PRE_STRMADDR6_END = channelcfg->all_reg.MMU_PRE_STRMADDR6_END; + + pAllReg->MMU_PRE_STRMADDR7_STR = channelcfg->all_reg.MMU_PRE_STRMADDR7_STR; + pAllReg->MMU_PRE_STRMADDR7_END = channelcfg->all_reg.MMU_PRE_STRMADDR7_END; + + pAllReg->MMU_PRE_STRMADDR8_STR = channelcfg->all_reg.MMU_PRE_STRMADDR8_STR; + pAllReg->MMU_PRE_STRMADDR8_END = channelcfg->all_reg.MMU_PRE_STRMADDR8_END; + + pAllReg->MMU_PRE_STRMADDR9_STR = channelcfg->all_reg.MMU_PRE_STRMADDR9_STR; + pAllReg->MMU_PRE_STRMADDR9_END = channelcfg->all_reg.MMU_PRE_STRMADDR9_END; + + pAllReg->MMU_PRE_STRMADDR10_STR = channelcfg->all_reg.MMU_PRE_STRMADDR10_STR; + pAllReg->MMU_PRE_STRMADDR10_END = channelcfg->all_reg.MMU_PRE_STRMADDR10_END; + + pAllReg->MMU_PRE_STRMADDR11_STR = channelcfg->all_reg.MMU_PRE_STRMADDR11_STR; + pAllReg->MMU_PRE_STRMADDR11_END = channelcfg->all_reg.MMU_PRE_STRMADDR11_END; + + pAllReg->MMU_PRE_STRMADDR12_STR = channelcfg->all_reg.MMU_PRE_STRMADDR12_STR; + pAllReg->MMU_PRE_STRMADDR12_END = channelcfg->all_reg.MMU_PRE_STRMADDR12_END; + + pAllReg->MMU_PRE_STRMADDR13_STR = channelcfg->all_reg.MMU_PRE_STRMADDR13_STR; + pAllReg->MMU_PRE_STRMADDR13_END = channelcfg->all_reg.MMU_PRE_STRMADDR13_END; + + pAllReg->MMU_PRE_STRMADDR14_STR = channelcfg->all_reg.MMU_PRE_STRMADDR14_STR; + pAllReg->MMU_PRE_STRMADDR14_END = channelcfg->all_reg.MMU_PRE_STRMADDR14_END; + + pAllReg->MMU_PRE_STRMADDR15_STR = channelcfg->all_reg.MMU_PRE_STRMADDR15_STR; + pAllReg->MMU_PRE_STRMADDR15_END = channelcfg->all_reg.MMU_PRE_STRMADDR15_END; + + ////smmu_mstr + ////mstr1 mstr2 + +#if 1 + if(channelcfg->bSecureFlag == 1){ //sec + + pAllReg->SMMU_MSTR_SMRX_1[0].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[0].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[0].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[0].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[1].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[1].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[1].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[1].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[2].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[2].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[2].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[2].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[3].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[3].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[3].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[3].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[4].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[4].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[4].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[4].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[5].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[5].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[5].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[5].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[6].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[6].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[6].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[6].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[7].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[7].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[7].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[7].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[8].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[8].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[8].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[8].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[9].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[9].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[9].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[9].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[10].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[10].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[10].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[10].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[11].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[11].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[11].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[11].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[12].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[12].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[12].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[12].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[13].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[13].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[13].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[13].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[14].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[14].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[14].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[14].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[30].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[30].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[30].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[30].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[31].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[31].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[31].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[31].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[32].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[32].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[32].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[32].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[33].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[33].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[33].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[33].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[34].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[34].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[34].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[34].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[35].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[35].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[35].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[35].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[36].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[36].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[36].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[36].bits.va_end; + +#ifdef HARDWARE_SPLIT_SPS_PPS_EN + if (channelcfg->bFirstNal2Send) + { + pAllReg->SMMU_MSTR_SMRX_1[37].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[37].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[37].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[37].bits.va_end; + HI_DBG_VENC("MMU_PRE_PPS_ADDR_STR:%pK, MMU_PRE_PPS_ADDR_END:%pK\n", (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_STR), (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_END)); + } +#endif + } + else{ + + pAllReg->SMMU_MSTR_SMRX_1[15].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[15].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[15].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[15].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[16].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[16].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[16].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[16].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[17].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[17].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[17].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[17].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[18].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[18].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[18].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[18].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[19].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[19].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[19].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[19].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[20].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[20].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[20].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[20].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[21].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[21].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[21].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[21].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[22].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[22].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[22].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[22].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[23].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[23].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[23].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[23].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[24].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[24].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[24].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[24].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[25].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[25].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[25].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[25].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[26].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[26].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[26].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[26].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[27].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[27].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[27].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[27].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[28].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[28].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[28].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[28].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[29].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[29].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[29].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[29].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[39].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[39].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[39].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[39].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[40].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[40].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[40].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[40].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[41].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[41].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[41].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[41].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[42].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[42].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[42].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[42].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[43].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[43].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[43].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[43].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[44].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[44].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[44].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[44].bits.va_end; + + pAllReg->SMMU_MSTR_SMRX_1[45].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[45].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[45].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[45].bits.va_end; + +#ifdef HARDWARE_SPLIT_SPS_PPS_EN + if (channelcfg->bFirstNal2Send) + { + pAllReg->SMMU_MSTR_SMRX_1[46].bits.va_str = channelcfg->all_reg.SMMU_MSTR_SMRX_1[46].bits.va_str; + pAllReg->SMMU_MSTR_SMRX_2[46].bits.va_end = channelcfg->all_reg.SMMU_MSTR_SMRX_2[46].bits.va_end; + HI_DBG_VENC("MMU_PRE_PPS_ADDR_STR:%pK, MMU_PRE_PPS_ADDR_END:%pK\n", (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_STR), (void *)(uintptr_t)(pAllReg->MMU_PRE_PPS_ADDR_END)); + } +#endif + } +#endif + +} + +//---------------------------------------- + +void VeduHal_CfgRegSimple(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + + { + U_VEDU_QPG_MAX_MIN_QP D32; + D32.bits.qpg_min_qp = channelcfg->all_reg.VEDU_QPG_MAX_MIN_QP.bits.qpg_min_qp; + D32.bits.qpg_max_qp = channelcfg->all_reg.VEDU_QPG_MAX_MIN_QP.bits.qpg_max_qp; + D32.bits.qpg_cu_qp_delta_enable_flag = 1; + pAllReg->VEDU_QPG_MAX_MIN_QP.u32 = D32.u32; + } + pAllReg->VEDU_VCPI_MODE.bits.vcpi_idr_pic = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_idr_pic ; + + pAllReg->VEDU_VCPI_MODE.bits.vcpi_frame_type = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_frame_type; + pAllReg->VEDU_VCPI_MODE.bits.vcpi_ref_num = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_ref_num; + + pAllReg->VEDU_VCPI_QPCFG.bits.vcpi_frm_qp = channelcfg->all_reg.VEDU_VCPI_QPCFG.bits.vcpi_frm_qp; + pAllReg->VEDU_QPG_AVERAGE_LCU_BITS.bits.qpg_ave_lcu_bits = channelcfg->all_reg.VEDU_QPG_AVERAGE_LCU_BITS.bits.qpg_ave_lcu_bits; + pAllReg->VEDU_QPG_ROW_TARGET_BITS.bits.qpg_row_target_bits = channelcfg->all_reg.VEDU_QPG_ROW_TARGET_BITS.bits.qpg_row_target_bits; + pAllReg->VEDU_VCPI_MODE.bits.vcpi_sao_chroma = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_sao_chroma; + pAllReg->VEDU_VCPI_MODE.bits.vcpi_sao_luma = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_sao_luma; + + VeduHal_CfgReg_IntraSet(channelcfg); + + VeduHal_CfgReg_LambdaSet(channelcfg); + + VeduHal_CfgReg_QpgmapSet(channelcfg); + + VeduHal_CfgReg_AddrSet(channelcfg); + + VeduHal_CfgReg_SlcHeadSet(channelcfg); + + VeduHal_CfgReg_PREMMUSet(channelcfg); + +} + +void VeduHal_CfgReg(VENC_REG_INFO_S *channelcfg) +{ + S_HEVC_AVC_REGS_TYPE *pAllReg = NULL; + unsigned int vcpi_protocol = 0; + + pAllReg = (S_HEVC_AVC_REGS_TYPE*)VeduIpCtx.pRegBase; + vcpi_protocol = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_protocol; + + //nosec reg + { + U_VEDU_VCPI_INTMASK D32; + D32.bits.vcpi_enable_ve_eop = 1; + D32.bits.vcpi_enable_vedu_slice_end = 1; + D32.bits.vcpi_enable_ve_buffull = 1; + D32.bits.vcpi_enable_ve_pbitsover = 0; + D32.bits.vcpi_enable_vedu_brkpt = 0; + D32.bits.vcpi_enable_vedu_step = 0; + D32.bits.vcpi_enable_vedu_timeout = 1; + D32.bits.vcpi_enable_cfg_err = 0; + pAllReg->VEDU_VCPI_INTMASK.u32 = D32.u32; + } + + { + U_VEDU_VCPI_INTCLR D32; + D32.bits.vcpi_clr_ve_eop = 0; + D32.bits.vcpi_clr_vedu_slice_end = 0; + D32.bits.vcpi_clr_ve_buffull = 0; + D32.bits.vcpi_clr_ve_pbitsover = 0; + D32.bits.vcpi_clr_vedu_brkpt = 0; + D32.bits.vcpi_clr_vedu_step = 0; + D32.bits.vcpi_clr_vedu_timeout = 0; + D32.bits.vcpi_clr_cfg_err = 0; + pAllReg->VEDU_VCPI_INTCLR.u32 = D32.u32; + } +/* //sec reg + { + pAllReg->VEDU_VCPI_INTMASK_S.u32 = channelcfg->all_reg.VEDU_VCPI_INTMASK_S.u32; + } + + { + pAllReg->VEDU_VCPI_INTCLR_S.u32 = channelcfg->all_reg.VEDU_VCPI_INTCLR_S.u32; + } +*/ + + { + //U_VEDU_VCPI_START D32; + //D32.bits.vcpi_vstart = 0;//channelcfg->all_reg.VEDU_VCPI_START.vcpi_vstart; + //D32.bits.vcpi_vstep = channelcfg->all_reg.VEDU_VCPI_START.vcpi_vstep; + //pAllReg->VEDU_VCPI_START.u32 = channelcfg->all_reg.VEDU_VCPI_START.u32; + } + { + pAllReg->VEDU_VCPI_CNTCLR.u32 = 0; + } + + { + pAllReg->VEDU_VCPI_FRAMENO = 0; + } + + { + U_VEDU_VCPI_BP_POS D32; + D32.bits.vcpi_bp_lcu_x = 0; + D32.bits.vcpi_bp_lcu_y = 0; + D32.bits.vcpi_bkp_en = 0; + D32.bits.vcpi_dbgmod = 0; + pAllReg->VEDU_VCPI_BP_POS.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_TIMEOUT = 0; + } + { + U_VEDU_VCPI_MODE D32; + D32.bits.vcpi_vedsel = 0; + D32.bits.vcpi_lcu_time_sel = 1; + D32.bits.vcpi_protocol = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_protocol; + D32.bits.vcpi_cfg_mode = 0; + D32.bits.vcpi_slice_int_en = 1; + D32.bits.vcpi_sao_luma = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_sao_luma; + D32.bits.vcpi_sao_chroma = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_sao_chroma; + D32.bits.vcpi_rec_cmp_en = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_rec_cmp_en; + D32.bits.vcpi_img_improve_en = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_img_improve_en; + D32.bits.vcpi_frame_type = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_frame_type; + D32.bits.vcpi_entropy_mode = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_entropy_mode; + D32.bits.vcpi_long_term_refpic = 0; + D32.bits.vcpi_ref_num = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_ref_num; + D32.bits.vcpi_2line_paral_enc = 0; + D32.bits.vcpi_idr_pic = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_idr_pic; + D32.bits.vcpi_pskip_en = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_pskip_en; + D32.bits.vcpi_trans_mode = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_trans_mode; + D32.bits.vcpi_blk8_inter = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_blk8_inter; + D32.bits.vcpi_sobel_weight_en = 0; + D32.bits.vcpi_high_speed_en = 0; + D32.bits.vcpi_tiles_en = 0; + D32.bits.vcpi_10bit_mode = 0; + D32.bits.vcpi_lcu_size = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_lcu_size; + D32.bits.vcpi_time_en = 0; + D32.bits.vcpi_ref_cmp_en = channelcfg->all_reg.VEDU_VCPI_MODE.bits.vcpi_ref_cmp_en; + D32.bits.vcpi_refc_nload = 0; + pAllReg->VEDU_VCPI_MODE.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_TILE_SIZE.u32 = 0; + } + { + pAllReg->VEDU_VCPI_PICSIZE_PIX.u32 = channelcfg->all_reg.VEDU_VCPI_PICSIZE_PIX.u32; + } + + { + U_VEDU_VCPI_MULTISLC D32; + D32.bits.vcpi_slice_size = channelcfg->all_reg.VEDU_VCPI_MULTISLC.bits.vcpi_slice_size; + D32.bits.vcpi_slcspilt_mod = 1; + D32.bits.vcpi_multislc_en = channelcfg->all_reg.VEDU_VCPI_MULTISLC.bits.vcpi_multislc_en; + pAllReg->VEDU_VCPI_MULTISLC.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_QPCFG.u32 = channelcfg->all_reg.VEDU_VCPI_QPCFG.u32; + } + + { + pAllReg->VEDU_VCPI_DBLKCFG.u32 = channelcfg->all_reg.VEDU_VCPI_DBLKCFG.u32; + } + + { + U_VEDU_VCPI_LOW_POWER D32; + D32.bits.vcpi_intra_lowpow_en = 0; + D32.bits.vcpi_fme_lowpow_en = 1; + D32.bits.vcpi_ime_lowpow_en = 1; + D32.bits.vcpi_ddr_cross_idx = 0; + D32.bits.vcpi_tqitq_gtck_en = 1; + D32.bits.vcpi_mrg_gtck_en = 1; + D32.bits.vcpi_fme_gtck_en = 1; + D32.bits.vcpi_clkgate_en = 2; + D32.bits.vcpi_mem_clkgate_en = 1; + D32.bits.vcpi_hfbc_clkgate_en = 1; + D32.bits.vcpi_ddr_cross_en = 0; + D32.bits.vcpi_10bit_addr_mode = 0; + pAllReg->VEDU_VCPI_LOW_POWER.u32 = D32.u32; + } + + { + U_VEDU_VCPI_OUTSTD D32; + D32.bits.vcpi_r_outstanding = 0x1F; + D32.bits.vcpi_w_outstanding = 0x7; + pAllReg->VEDU_VCPI_OUTSTD.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_TMV_LOAD.bits.vcpi_tmv_wr_rd_avail = 3; + } + { + pAllReg->VEDU_VCPI_CROSS_TILE_SLC.u32 = channelcfg->all_reg.VEDU_VCPI_CROSS_TILE_SLC.u32; + } + + { + U_VEDU_VCPI_MEM_CTRL D32; + D32.bits.vcpi_ema = 3; + D32.bits.vcpi_emaw = 1; + D32.bits.vcpi_emaa = 3; + D32.bits.vcpi_emab = 3; + pAllReg->VEDU_VCPI_MEM_CTRL.u32 = D32.u32; + } + + { + U_VEDU_VCPI_INTRA_INTER_CU_EN D32; + D32.bits.vcpi_intra_cu_en = channelcfg->all_reg.VEDU_VCPI_INTRA_INTER_CU_EN.bits.vcpi_intra_cu_en; + D32.bits.vcpi_ipcm_en = 1; + D32.bits.vcpi_intra_h264_cutdiag = 1; + D32.bits.vcpi_fme_cu_en = channelcfg->all_reg.VEDU_VCPI_INTRA_INTER_CU_EN.bits.vcpi_fme_cu_en; + D32.bits.vcpi_mrg_cu_en = channelcfg->all_reg.VEDU_VCPI_INTRA_INTER_CU_EN.bits.vcpi_mrg_cu_en; + pAllReg->VEDU_VCPI_INTRA_INTER_CU_EN.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PRE_JUDGE_EXT_EN D32; + D32.bits.vcpi_iblk_pre_en = 0; + D32.bits.vcpi_pblk_pre_en = channelcfg->all_reg.VEDU_VCPI_PRE_JUDGE_EXT_EN.bits.vcpi_pblk_pre_en;//0; + D32.bits.vcpi_force_inter = 0; + D32.bits.vcpi_pintra_inter_flag_disable = 0; + D32.bits.vcpi_ext_edge_en = 1; + pAllReg->VEDU_VCPI_PRE_JUDGE_EXT_EN.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PRE_JUDGE_COST_THR D32; + D32.bits.vcpi_iblk_pre_cost_thr = DIST_PROTOCOL(vcpi_protocol, 0x1F4, 0x100); + D32.bits.vcpi_pblk_pre_cost_thr = 0x64; + pAllReg->VEDU_VCPI_PRE_JUDGE_COST_THR.u32 = D32.u32; + } + + { + U_VEDU_VCPI_IBLK_PRE_MV_THR D32; + D32.bits.vcpi_iblk_pre_mv_dif_thr0 = 0xF; + D32.bits.vcpi_iblk_pre_mv_dif_thr1 = 0xF; + D32.bits.vcpi_iblk_pre_mvx_thr = DIST_PROTOCOL(vcpi_protocol, 5, 0xC0); + D32.bits.vcpi_iblk_pre_mvy_thr = DIST_PROTOCOL(vcpi_protocol, 5, 0xA0); + pAllReg->VEDU_VCPI_IBLK_PRE_MV_THR.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PME_PARAM D32; + D32.bits.vcpi_move_sad_en = 0; + D32.bits.vcpi_pblk_pre_mvx_thr = DIST_PROTOCOL(vcpi_protocol, 2, 0x10); + D32.bits.vcpi_pblk_pre_mvy_thr = DIST_PROTOCOL(vcpi_protocol, 2, 0x10); + pAllReg->VEDU_VCPI_PME_PARAM.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PIC_STRONG_EN D32; + D32.bits.vcpi_skin_en = channelcfg->all_reg.VEDU_VCPI_PIC_STRONG_EN.bits.vcpi_skin_en; + D32.bits.vcpi_strong_edge_en = channelcfg->all_reg.VEDU_VCPI_PIC_STRONG_EN.bits.vcpi_strong_edge_en; + D32.bits.vcpi_still_en = 0; + D32.bits.vcpi_skin_close_angle = 0; + D32.bits.vcpi_rounding_sobel_en = 0; + pAllReg->VEDU_VCPI_PIC_STRONG_EN.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PINTRA_THRESH0 D32; + D32.bits.vcpi_pintra_pu16_amp_th = DIST_PROTOCOL(vcpi_protocol, 0x51, 0x80); + D32.bits.vcpi_pintra_pu32_amp_th = DIST_PROTOCOL(vcpi_protocol, 0x5E, 0x80); + D32.bits.vcpi_pintra_pu64_amp_th = 0x80; + pAllReg->VEDU_VCPI_PINTRA_THRESH0.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PINTRA_THRESH1 D32; + D32.bits.vcpi_pintra_pu16_std_th = DIST_PROTOCOL(vcpi_protocol, 0x66, 0x80); + D32.bits.vcpi_pintra_pu32_std_th = DIST_PROTOCOL(vcpi_protocol, 0x4C, 0x80); + pAllReg->VEDU_VCPI_PINTRA_THRESH1.u32 = D32.u32; + } + + { + U_VEDU_VCPI_PINTRA_THRESH2 D32; + D32.bits.vcpi_pintra_pu16_angel_cost_th = 0x80; + D32.bits.vcpi_pintra_pu32_angel_cost_th = 0x80; + pAllReg->VEDU_VCPI_PINTRA_THRESH2.u32 = D32.u32; + } + + { + U_VEDU_VCPI_CLKDIV_ENABLE D32; + D32.bits.vcpi_clkdiv_en = 0; + D32.bits.vcpi_down_freq_en = 0; + pAllReg->VEDU_VCPI_CLKDIV_ENABLE.u32 = D32.u32;//channelcfg->all_reg.VEDU_VCPI_CLKDIV_ENABLE.u32; + } + + { + pAllReg->VEDU_VCPI_SW_L0_SIZE.u32 = channelcfg->all_reg.VEDU_VCPI_SW_L0_SIZE.u32; + } + + { + pAllReg->VEDU_VCPI_SW_L1_SIZE.u32 = channelcfg->all_reg.VEDU_VCPI_SW_L1_SIZE.u32; + } + + { + U_VEDU_VCPI_CROP_START D32; + D32.bits.vcpi_crop_xstart = 0; + D32.bits.vcpi_crop_ystart = 0; + pAllReg->VEDU_VCPI_CROP_START.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_ORI_PICSIZE.u32 = channelcfg->all_reg.VEDU_VCPI_ORI_PICSIZE.u32; + } + + { + U_VEDU_VCPI_MEM_CTRL_T16 D32; + D32.bits.mem_ctrl_s = 0x00A8; + D32.bits.mem_ctrl_d1w2r = 0x01A8; + pAllReg->VEDU_VCPI_MEM_CTRL_T16.u32 = D32.u32; + } + + { + U_VEDU_VCPI_INTRA32_LOW_POWER D32; + D32.bits.vcpi_intra32_low_power_thr = 0x400; + D32.bits.vcpi_intra32_low_power_en = channelcfg->all_reg.VEDU_VCPI_INTRA32_LOW_POWER.bits.vcpi_intra32_low_power_en;//DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_VCPI_INTRA32_LOW_POWER.u32 = D32.u32; + } + + { + U_VEDU_VCPI_INTRA16_LOW_POWER D32; + D32.bits.vcpi_intra16_low_power_thr = 0x200; + D32.bits.vcpi_intra16_low_power_en = channelcfg->all_reg.VEDU_VCPI_INTRA16_LOW_POWER.bits.vcpi_intra16_low_power_en;//DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_VCPI_INTRA16_LOW_POWER.u32 = D32.u32; + } + + { + U_VEDU_VCPI_INTRA_REDUCE_RDO_NUM D32; + D32.bits.vcpi_intra_reduce_rdo_num_thr = 0x100; + D32.bits.vcpi_intra_reduce_rdo_num_en = 0; + pAllReg->VEDU_VCPI_INTRA_REDUCE_RDO_NUM.u32 = D32.u32; + } + + { + pAllReg->VEDU_VCPI_NOFORCEZERO.u32 = 0; + } + + { + pAllReg->VEDU_VCTRL_LCU_TARGET_BIT.bits.vctrl_lcu_target_bit = 0x64; + } + + { + pAllReg->VEDU_VCTRL_NARROW_THRESHOLD.bits.vctrl_narrow_tile_width = 3; + } + + { + U_VEDU_VCTRL_LCU_BASELINE D32; + D32.bits.vctrl_lcu_performance_baseline = DIST_PROTOCOL(vcpi_protocol, 0x186A, 0x1806); + pAllReg->VEDU_VCTRL_LCU_BASELINE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_norm32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x100, 0); + D32.bits.vctrl_norm32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingoffset32x32 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_NORM_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_norm16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x40, 0); + D32.bits.vctrl_norm16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x3, 0); + D32.bits.vctrl_roundingoffset16x16 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_NORM_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_NORM_COEFF_DENOISE D32; + D32.bits.vctrl_roundingmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingdegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundinglowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundinglowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_NORM_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_NORM_ENG_DENOISE D32; + D32.bits.vctrl_norm_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_norm_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_norm_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_norm_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_norm_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_norm_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_NORM_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_skin32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x20, 0); + D32.bits.vctrl_skin32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingskinoffset32x32 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_SKIN_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_skin16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_skin16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingskinoffset16x16 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_SKIN_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SKIN_COEFF_DENOISE D32; + D32.bits.vctrl_roundingskinmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingskindegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x5A, 0); + D32.bits.vctrl_roundingskinforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingskinac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingskinac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingskinlowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingskinlowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_SKIN_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SKIN_ENG_DENOISE D32; + D32.bits.vctrl_skin_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_skin_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_skin_engsum_32 = 0; + D32.bits.vctrl_skin_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_skin_engsum_16 = 0; + D32.bits.vctrl_skin_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_SKIN_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_hedge32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x20, 0); + D32.bits.vctrl_hedge32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingedgeoffset32x32 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_HEDGE_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_hedge16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_hedge16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingedgeoffset16x16 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_HEDGE_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGE_COEFF_DENOISE D32; + D32.bits.vctrl_roundingedgemechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingedgedegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingedgeforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingedgeac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingedgeac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingedgelowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingedgelowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_HEDGE_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGE_ENG_DENOISE D32; + D32.bits.vctrl_stredge_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_stredge_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_stredge_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_stredge_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_stredge_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_stredge_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_HEDGE_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_edgemov32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x20, 0); + D32.bits.vctrl_edgemov32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingedgemovoffset32x32 = 0; + pAllReg->VEDU_VCTRL_HEDGEMOV_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_edgemov16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_edgemov16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingedgemovoffset16x16 = 0; + pAllReg->VEDU_VCTRL_HEDGEMOV_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE D32; + D32.bits.vctrl_roundingedgemovmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingedgemovdegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingedgemovforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingedgemovac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingedgemovac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingedgemovlowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingedgemovlowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_HEDGEMOV_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_HEDGEMOV_ENG_DENOISE D32; + D32.bits.vctrl_edgemov_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_edgemov_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_edgemov_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_edgemov_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_edgemov_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_edgemov_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_HEDGEMOV_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_static32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_static32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingstilloffset32x32 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_STATIC_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_static16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_static16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingstilloffset16x16 = DIST_PROTOCOL(vcpi_protocol, 0x7, 0); + pAllReg->VEDU_VCTRL_STATIC_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_STATIC_COEFF_DENOISE D32; + D32.bits.vctrl_roundingstillmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingstilldegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingstillforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingstillac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingstillac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingstilllowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingstilllowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_STATIC_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_STATIC_ENG_DENOISE D32; + D32.bits.vctrl_still_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_still_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_still_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_still_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_still_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_still_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_STATIC_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_sobelstr32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_sobelstr32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingsobelstroffset32x32 = 0; + pAllReg->VEDU_VCTRL_SOBELSTR_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_sobelstr16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelstr16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingsobelstroffset16x16 = 0; + pAllReg->VEDU_VCTRL_SOBELSTR_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELSTR_COEFF_DENOISE D32; + D32.bits.vctrl_roundingsobelstrmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingsobelstrdegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingsobelstrforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingsobelstrac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingsobelstrac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingsobelstrlowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingsobelstrlowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_SOBELSTR_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELSTR_ENG_DENOISE D32; + D32.bits.vctrl_sobelstr_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_sobelstr_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_sobelstr_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelstr_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelstr_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_sobelstr_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_SOBELSTR_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE D32; + D32.bits.vctrl_sobelweak32_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x10, 0); + D32.bits.vctrl_sobelweak32_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingsobelweakoffset32x32 = 0; + pAllReg->VEDU_VCTRL_SOBELWEAK_TR32X32_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE D32; + D32.bits.vctrl_sobelweak16_coeff_protect_num = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelweak16_tr1_denois_max_num = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingsobelweakoffset16x16 = 0; + pAllReg->VEDU_VCTRL_SOBELWEAK_TR16X16_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE D32; + D32.bits.vctrl_roundingsobelweakmechanism = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_roundingsobelweakdegreethresh = DIST_PROTOCOL(vcpi_protocol, 0x21, 0); + D32.bits.vctrl_roundingsobelweakforcezeroresidthresh = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingsobelweakac32sum = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_roundingsobelweakac16sum = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_roundingsobelweaklowfreqacblk32 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + D32.bits.vctrl_roundingsobelweaklowfreqacblk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0); + pAllReg->VEDU_VCTRL_SOBELWEAK_COEFF_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_SOBELWEAK_ENG_DENOISE D32; + D32.bits.vctrl_sobelwk_isolate_ac_enable = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_sobelwk_force_zero_cnt = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_sobelwk_engsum_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelwk_engcnt_32 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.vctrl_sobelwk_engsum_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + D32.bits.vctrl_sobelwk_engcnt_16 = DIST_PROTOCOL(vcpi_protocol, 0x6, 0); + pAllReg->VEDU_VCTRL_SOBELWEAK_ENG_DENOISE.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_INTRA_RDO_FACTOR_0 D32; + D32.bits.vctrl_norm_intra_cu4_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_norm_intra_cu8_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_norm_intra_cu16_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_norm_intra_cu32_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_strmov_intra_cu4_rdcost_offset = 0; + D32.bits.vctrl_strmov_intra_cu8_rdcost_offset = 0; + D32.bits.vctrl_strmov_intra_cu16_rdcost_offset = 0; + D32.bits.vctrl_strmov_intra_cu32_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_0.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_INTRA_RDO_FACTOR_1 D32; + D32.bits.vctrl_skin_intra_cu4_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_skin_intra_cu8_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_skin_intra_cu16_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_skin_intra_cu32_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0xf, 0); + D32.bits.vctrl_sobel_str_intra_cu4_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_intra_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_intra_cu16_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_intra_cu32_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_1.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_INTRA_RDO_FACTOR_2 D32; + D32.bits.vctrl_hedge_intra_cu4_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_hedge_intra_cu8_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_hedge_intra_cu16_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.vctrl_hedge_intra_cu32_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.vctrl_sobel_tex_intra_cu4_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_intra_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_intra_cu16_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_intra_cu32_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_INTRA_RDO_FACTOR_2.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_MRG_RDO_FACTOR_0 D32; + D32.bits.vctrl_norm_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_norm_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_norm_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_norm_mrg_cu64_rdcost_offset = 0; + D32.bits.vctrl_strmov_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_strmov_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_strmov_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_strmov_mrg_cu64_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_MRG_RDO_FACTOR_0.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_MRG_RDO_FACTOR_1 D32; + D32.bits.vctrl_skin_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_skin_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_skin_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_skin_mrg_cu64_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_mrg_cu64_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_MRG_RDO_FACTOR_1.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_MRG_RDO_FACTOR_2 D32; + D32.bits.vctrl_hedge_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_hedge_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_hedge_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_hedge_mrg_cu64_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_mrg_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_mrg_cu16_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_mrg_cu32_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_mrg_cu64_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_MRG_RDO_FACTOR_2.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_FME_RDO_FACTOR_0 D32; + D32.bits.vctrl_norm_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_norm_fme_cu16_rdcost_offset = 0; + D32.bits.vctrl_norm_fme_cu32_rdcost_offset = 0; + D32.bits.vctrl_norm_fme_cu64_rdcost_offset = 0; + D32.bits.vctrl_strmov_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_strmov_fme_cu16_rdcost_offset = 0; + D32.bits.vctrl_strmov_fme_cu32_rdcost_offset = 0; + D32.bits.vctrl_strmov_fme_cu64_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_FME_RDO_FACTOR_0.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_FME_RDO_FACTOR_1 D32; + D32.bits.vctrl_skin_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_skin_fme_cu16_rdcost_offset = 0; + D32.bits.vctrl_skin_fme_cu32_rdcost_offset = 0; + D32.bits.vctrl_skin_fme_cu64_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_str_fme_cu16_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0xA, 0); + D32.bits.vctrl_sobel_str_fme_cu32_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0xA, 0); + D32.bits.vctrl_sobel_str_fme_cu64_rdcost_offset = DIST_PROTOCOL(vcpi_protocol, 0xA, 0); + pAllReg->VEDU_VCTRL_FME_RDO_FACTOR_1.u32 = D32.u32; + } + + { + U_VEDU_VCTRL_FME_RDO_FACTOR_2 D32; + D32.bits.vctrl_hedge_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_hedge_fme_cu16_rdcost_offset = 0; + D32.bits.vctrl_hedge_fme_cu32_rdcost_offset = 0; + D32.bits.vctrl_hedge_fme_cu64_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_fme_cu8_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_fme_cu16_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_fme_cu32_rdcost_offset = 0; + D32.bits.vctrl_sobel_tex_fme_cu64_rdcost_offset = 0; + pAllReg->VEDU_VCTRL_FME_RDO_FACTOR_2.u32 = D32.u32; + } + + { + U_VEDU_CURLD_GCFG D32; + D32.bits.curld_osd0_global_en = 0; + D32.bits.curld_osd1_global_en = 0; + D32.bits.curld_osd2_global_en = 0; + D32.bits.curld_osd3_global_en = 0; + D32.bits.curld_osd4_global_en = 0; + D32.bits.curld_osd5_global_en = 0; + D32.bits.curld_osd6_global_en = 0; + D32.bits.curld_osd7_global_en = 0; + D32.bits.curld_col2gray_en = 0; + D32.bits.curld_clip_en = 0; + D32.bits.curld_read_interval = 1; + D32.bits.curld_lowdly_en = 0; + D32.bits.curld_osd_rgbfmt = 0; + pAllReg->VEDU_CURLD_GCFG.u32 = D32.u32; + } + + { + pAllReg->VEDU_CURLD_OSD01_ALPHA.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD23_ALPHA.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD45_ALPHA.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD67_ALPHA.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD_GALPHA0.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD_GALPHA1.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD0_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD1_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD2_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD3_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD4_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD5_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD6_ADDR = 0; + } + + { + pAllReg->VEDU_CURLD_OSD7_ADDR= 0; + } + + { + pAllReg->VEDU_CURLD_OSD01_STRIDE.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD23_STRIDE.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD45_STRIDE.u32 = 0; + } + + { + pAllReg->VEDU_CURLD_OSD67_STRIDE.u32 = 0; + } + + { + U_VEDU_CURLD_CLIP_THR D32; + D32.bits.curld_clip_luma_min = 16; + D32.bits.curld_clip_luma_max = 0xEB; + D32.bits.curld_clip_chrm_min = 16; + D32.bits.curld_clip_chrm_max = DIST_PROTOCOL(vcpi_protocol, 0xF0, 240); + pAllReg->VEDU_CURLD_CLIP_THR.u32 = D32.u32; + } + + { + U_VEDU_CURLD_HOR_FILTER D32; + D32.bits.curld_filter_h0 = 0x1; + D32.bits.curld_filter_h1 = 0x1; + D32.bits.curld_filter_h2 = 0x1; + D32.bits.curld_filter_h3 = 0x1; + D32.bits.curld_filter_hrnd = channelcfg->all_reg.VEDU_CURLD_HOR_FILTER.bits.curld_filter_hrnd; + D32.bits.curld_filter_hshift = 0x2; + pAllReg->VEDU_CURLD_HOR_FILTER.u32 = D32.u32; + } + + { + U_VEDU_CURLD_VER_FILTER D32; + D32.bits.curld_filter_v0 = 0x1; + D32.bits.curld_filter_v1 = 0x1; + D32.bits.curld_filter_v2 = 0x1; + D32.bits.curld_filter_v3 = 0x1; + D32.bits.curld_filter_vrnd = channelcfg->all_reg.VEDU_CURLD_VER_FILTER.bits.curld_filter_vrnd; + D32.bits.curld_filter_vshift = 0x2; + pAllReg->VEDU_CURLD_VER_FILTER.u32 = D32.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_0COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_0COEFF.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_1COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_1COEFF.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_2COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_2COEFF.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_3COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_3COEFF.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_4COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_4COEFF.u32; + } + + { + pAllReg->VEDU_CURLD_ARGB_YUV_5COEFF.u32 = channelcfg->all_reg.VEDU_CURLD_ARGB_YUV_5COEFF.u32; + } + + { + U_VEDU_CURLD_ARGB_YUV_6COEFF D32; + D32.bits.vcpi_rgb_rndcr = 128; + D32.bits.vcpi_rgb_rndcb = 128; + pAllReg->VEDU_CURLD_ARGB_YUV_6COEFF.u32 = D32.u32; + } + + { + U_VEDU_CURLD_ARGB_CLIP D32; + D32.bits.vcpi_rgb_clpmin = 16; + D32.bits.vcpi_rgb_clpmax = 235; + D32.bits.vcpi_rgb_clip_en = 0; + pAllReg->VEDU_CURLD_ARGB_CLIP.u32 = D32.u32; + } + + { + pAllReg->VEDU_CURLD_NARROW_EN.u32 = channelcfg->all_reg.VEDU_CURLD_NARROW_EN.u32; + } + + { + U_VEDU_PME_SW_ADAPT_EN D32; + D32.bits.pme_l0_psw_adapt_en = DIST_PROTOCOL(vcpi_protocol, 1, 0); + D32.bits.pme_l1_psw_adapt_en = DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_PME_SW_ADAPT_EN.u32 = D32.u32; + } + + { + U_VEDU_PME_SW_THR0 D32; + D32.bits.pme_l0_psw_thr0 = 0x14; + D32.bits.pme_l1_psw_thr0 = 0x14; + pAllReg->VEDU_PME_SW_THR0.u32 = D32.u32; + } + + { + U_VEDU_PME_SW_THR1 D32; + D32.bits.pme_l0_psw_thr1 = 0x32; + D32.bits.pme_l1_psw_thr1 = 0x32; + pAllReg->VEDU_PME_SW_THR1.u32 = D32.u32; + } + + { + U_VEDU_PME_SW_THR2 D32; + D32.bits.pme_l0_psw_thr2 = 0x96; + D32.bits.pme_l1_psw_thr2 = 0x96; + pAllReg->VEDU_PME_SW_THR2.u32 = D32.u32; + } + + { + U_VEDU_PME_SKIP_PRE D32; + D32.bits.pme_skipblk_pre_cost_thr = DIST_PROTOCOL(vcpi_protocol, 0x1E, 0); + D32.bits.pme_skipblk_pre_en = 0; + pAllReg->VEDU_PME_SKIP_PRE.u32 = D32.u32; + } + + { + U_VEDU_PME_TR_WEIGHTX D32; + D32.bits.pme_tr_weightx_0 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0x10); + D32.bits.pme_tr_weightx_1 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0x20); + D32.bits.pme_tr_weightx_2 = DIST_PROTOCOL(vcpi_protocol, 0xC, 0x30); + pAllReg->VEDU_PME_TR_WEIGHTX.u32 = D32.u32; + } + + { + U_VEDU_PME_TR_WEIGHTY D32; + D32.bits.pme_tr_weighty_0 = DIST_PROTOCOL(vcpi_protocol, 0x4, 0x10); + D32.bits.pme_tr_weighty_1 = DIST_PROTOCOL(vcpi_protocol, 0x8, 0x20); + D32.bits.pme_tr_weighty_2 = DIST_PROTOCOL(vcpi_protocol, 0xC, 0x30); + pAllReg->VEDU_PME_TR_WEIGHTY.u32 = D32.u32; + } + + { + U_VEDU_PME_SR_WEIGHT D32; + D32.bits.pme_sr_weight_0 = 6; + D32.bits.pme_sr_weight_1 = 4; + D32.bits.pme_sr_weight_2 = 2; + D32.bits.pme_pskip_strongedge_madi_thr = 0x14; + D32.bits.pme_pskip_strongedge_madi_times = 0x03; + pAllReg->VEDU_PME_SR_WEIGHT.u32 = D32.u32; + } + + { + U_VEDU_PME_INTRABLK_DET D32; + D32.bits.pme_intrablk_det_cost_thr0 = DIST_PROTOCOL(vcpi_protocol, 0x174, 0x64); + D32.bits.pme_pskip_mvy_consistency_thr = 0; + D32.bits.pme_pskip_mvx_consistency_thr = 0; + pAllReg->VEDU_PME_INTRABLK_DET.u32 = D32.u32; + } + + { + U_VEDU_PME_INTRABLK_DET_THR D32; + D32.bits.pme_intrablk_det_mv_dif_thr1 = DIST_PROTOCOL(vcpi_protocol, 0x2, 0x0F); + D32.bits.pme_intrablk_det_mv_dif_thr0 = DIST_PROTOCOL(vcpi_protocol, 0x2, 0x0F); + D32.bits.pme_intrablk_det_mvy_thr = DIST_PROTOCOL(vcpi_protocol, 4, 0x10); + D32.bits.pme_intrablk_det_mvx_thr = DIST_PROTOCOL(vcpi_protocol, 4, 0x10); + pAllReg->VEDU_PME_INTRABLK_DET_THR.u32 = D32.u32; + } + + { + U_VEDU_PME_SKIN_THR D32; + D32.bits.pme_skin_u_max_thr = 0x7F; + D32.bits.pme_skin_u_min_thr = 0x64; + D32.bits.pme_skin_v_max_thr = 0xA0; + D32.bits.pme_skin_v_min_thr = 0x87; + pAllReg->VEDU_PME_SKIN_THR.u32 = D32.u32; + } + + { + U_VEDU_PME_INTRA_LOWPOW D32; + D32.bits.pme_intra16_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0xA, 0); + D32.bits.pme_intra32_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0x14, 0); + D32.bits.pme_intra_lowpow_en = channelcfg->all_reg.VEDU_PME_INTRA_LOWPOW.bits.pme_intra_lowpow_en;//DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_inter_first = 0; + pAllReg->VEDU_PME_INTRA_LOWPOW.u32 = D32.u32; + } + + { + U_VEDU_PME_IBLK_COST_THR D32; + D32.bits.pme_iblk_pre_cost_thr_h264 = DIST_PROTOCOL(vcpi_protocol, 0x02FF, 0x400); + D32.bits.pme_intrablk_det_cost_thr1 = DIST_PROTOCOL(vcpi_protocol, 0x0200, 0xC8); + pAllReg->VEDU_PME_IBLK_COST_THR.u32 = D32.u32; + } + + { + U_VEDU_PME_STRONG_EDGE D32; + D32.bits.pme_skin_num = DIST_PROTOCOL(vcpi_protocol, 0x80, 0x30); + D32.bits.pme_strong_edge_thr = DIST_PROTOCOL(vcpi_protocol, 0x1E, 0x28); + D32.bits.pme_strong_edge_cnt = DIST_PROTOCOL(vcpi_protocol, 0x3, 0x06); + D32.bits.pme_still_scene_thr = DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_PME_STRONG_EDGE.u32 = D32.u32; + } + + { + U_VEDU_PME_LARGE_MOVE_THR D32; + D32.bits.pme_move_scene_thr = DIST_PROTOCOL(vcpi_protocol, 0x3, 0); + D32.bits.pme_move_sad_thr = DIST_PROTOCOL(vcpi_protocol, 0x200, 0); + pAllReg->VEDU_PME_LARGE_MOVE_THR.u32 = D32.u32; + } + + { + U_VEDU_PME_INTER_STRONG_EDGE D32; + D32.bits.pme_interdiff_max_min_madi_abs = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_interdiff_max_min_madi_times = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_interstrongedge_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0x3C, 0); + pAllReg->VEDU_PME_INTER_STRONG_EDGE.u32 = D32.u32; + } + + { + pAllReg->VEDU_PME_NEW_COST.bits.pme_cost_lamda0 = channelcfg->all_reg.VEDU_PME_NEW_COST.bits.pme_cost_lamda0;; + pAllReg->VEDU_PME_NEW_COST.bits.pme_cost_lamda1 = 0x2; + pAllReg->VEDU_PME_NEW_COST.bits.pme_cost_lamda2 = 0xF; + pAllReg->VEDU_PME_NEW_COST.bits.pme_cost_lamda_en = 0; + pAllReg->VEDU_PME_NEW_COST.bits.pme_mvp3median_en = 0; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE0_L0.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE0_L0.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE1_L0.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE1_L0.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE2_L0.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE2_L0.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE3_L0.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE3_L0.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE0_L1.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE0_L1.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE1_L1.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE1_L1.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE2_L1.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE2_L1.u32; + } + + { + pAllReg->VEDU_PME_WINDOW_SIZE3_L1.u32 = channelcfg->all_reg.VEDU_PME_WINDOW_SIZE3_L1.u32; + } + + { + pAllReg->VEDU_PME_COST_OFFSET.u32 = 0; + } + + { + U_VEDU_PME_SAFE_CFG D32; + D32.bits.pme_safe_line = channelcfg->all_reg.VEDU_PME_SAFE_CFG.bits.pme_safe_line; + D32.bits.pme_safe_line_val = 0; + pAllReg->VEDU_PME_SAFE_CFG.u32 = D32.u32; + } + + { + pAllReg->VEDU_PME_IBLK_REFRESH.u32 = 0; + } + + { + pAllReg->VEDU_PME_IBLK_REFRESH_NUM.u32 = 0; + } + + { + U_VEDU_PME_QPG_RC_THR0 D32; + D32.bits.pme_madi_dif_thr = DIST_PROTOCOL(vcpi_protocol, 0, 0x5); + D32.bits.pme_cur_madi_dif_thr = DIST_PROTOCOL(vcpi_protocol, 0, 0x5); + pAllReg->VEDU_PME_QPG_RC_THR0.u32 = D32.u32; + } + + { + U_VEDU_PME_QPG_RC_THR1 D32; + D32.bits.pme_min_sad_thr_offset = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.pme_min_sad_thr_gain = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.pme_smooth_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0, 0x2); + D32.bits.pme_min_sad_thr_offset_cur = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + D32.bits.pme_min_sad_thr_gain_cur = DIST_PROTOCOL(vcpi_protocol, 0x8, 0); + pAllReg->VEDU_PME_QPG_RC_THR1.u32 = D32.u32; + } + + { + U_VEDU_PME_LOW_LUMA_THR D32; + D32.bits.pme_low_luma_thr = 0; + D32.bits.pme_low_luma_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0x5, 0x4); + D32.bits.pme_high_luma_thr = DIST_PROTOCOL(vcpi_protocol, 0xF, 0x3C); + pAllReg->VEDU_PME_LOW_LUMA_THR.u32 = D32.u32; + } + + { + U_VEDU_PME_PBLK_PRE1 D32; + D32.bits.pme_pblk_pre_mv_dif_thr1 = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_pblk_pre_mv_dif_thr0 = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_pblk_pre_mv_dif_cost_thr = DIST_PROTOCOL(vcpi_protocol, 0xC8, 0); + pAllReg->VEDU_PME_PBLK_PRE1.u32 = D32.u32; + } + + { + U_VEDU_PME_CHROMA_FLAT D32; + D32.bits.pme_flat_v_thr_high = DIST_PROTOCOL(vcpi_protocol, 0x85, 0); + D32.bits.pme_flat_v_thr_low = DIST_PROTOCOL(vcpi_protocol, 0x7D, 0); + D32.bits.pme_flat_u_thr_high = DIST_PROTOCOL(vcpi_protocol, 0x85, 0); + D32.bits.pme_flat_u_thr_low = DIST_PROTOCOL(vcpi_protocol, 0x7D, 0); + pAllReg->VEDU_PME_CHROMA_FLAT.u32 = D32.u32; + } + + { + U_VEDU_PME_LUMA_FLAT D32; + D32.bits.pme_flat_pmemv_thr = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.pme_flat_luma_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0x2, 0); + D32.bits.pme_flat_low_luma_thr = DIST_PROTOCOL(vcpi_protocol, 0x28, 0); + D32.bits.pme_flat_high_luma_thr = DIST_PROTOCOL(vcpi_protocol, 0x64, 0); + pAllReg->VEDU_PME_LUMA_FLAT.u32 = D32.u32; + } + + { + U_VEDU_PME_MADI_FLAT D32; + D32.bits.pme_flat_pmesad_thr = DIST_PROTOCOL(vcpi_protocol, 0x40, 0); + D32.bits.pme_flat_icount_thr = DIST_PROTOCOL(vcpi_protocol, 0xC8, 0); + D32.bits.pme_flat_region_cnt = DIST_PROTOCOL(vcpi_protocol, 0xD, 0); + D32.bits.pme_flat_madi_times = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + pAllReg->VEDU_PME_MADI_FLAT.u32 = D32.u32; + } + + { + U_VEDU_PME_SKIP_LARGE_RES D32; + D32.bits.pme_skip_sad_thr_offset = 0x8; + D32.bits.pme_skip_sad_thr_gain = 0x8; + D32.bits.pme_skip_large_res_det = 0x0; + pAllReg->VEDU_PME_SKIP_LARGE_RES.u32 = D32.u32; + } + + { + U_VEDU_QPG_MAX_MIN_QP D32; + D32.bits.qpg_min_qp = channelcfg->all_reg.VEDU_QPG_MAX_MIN_QP.bits.qpg_min_qp; + D32.bits.qpg_max_qp = channelcfg->all_reg.VEDU_QPG_MAX_MIN_QP.bits.qpg_max_qp; + D32.bits.qpg_cu_qp_delta_enable_flag = 1; + pAllReg->VEDU_QPG_MAX_MIN_QP.u32 = D32.u32; + } + + { + U_VEDU_QPG_ROW_TARGET_BITS D32; + D32.bits.qpg_qp_delta = channelcfg->all_reg.VEDU_QPG_ROW_TARGET_BITS.bits.qpg_qp_delta; + D32.bits.qpg_row_target_bits = channelcfg->all_reg.VEDU_QPG_ROW_TARGET_BITS.bits.qpg_row_target_bits;//DIST_PROTOCOL(vcpi_protocol, 0xB956, 0x0); + pAllReg->VEDU_QPG_ROW_TARGET_BITS.u32 = D32.u32; + } + + { + + pAllReg->VEDU_QPG_AVERAGE_LCU_BITS.u32 = channelcfg->all_reg.VEDU_QPG_AVERAGE_LCU_BITS.u32; + } + + { + U_VEDU_QPG_LOWLUMA D32; + D32.bits.qpg_lowluma_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_lowluma_max_qp = DIST_PROTOCOL(vcpi_protocol, 0xF, 0x33); + D32.bits.qpg_lowluma_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0xA, 0x3); + pAllReg->VEDU_QPG_LOWLUMA .u32 = D32.u32; + } + + { + U_VEDU_QPG_HEDGE D32; + D32.bits.qpg_hedge_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_hedge_max_qp = 0x33; + D32.bits.qpg_hedge_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x4); + pAllReg->VEDU_QPG_HEDGE.u32 = D32.u32; + } + + { + U_VEDU_QPG_HEDGE_MOVE D32; + D32.bits.qpg_hedge_move_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_hedge_move_max_qp = 0x33; + D32.bits.qpg_hedge_move_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x5); + pAllReg->VEDU_QPG_HEDGE_MOVE.u32 = D32.u32; + } + + { + U_VEDU_QPG_LARGE_MOVE D32; + D32.bits.qpg_large_move_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_large_move_max_qp =0x33; + D32.bits.qpg_large_move_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x0); + pAllReg->VEDU_QPG_LARGE_MOVE.u32 = D32.u32; + } + + { + U_VEDU_QPG_SKIN D32; + D32.bits.qpg_skin_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_skin_max_qp = channelcfg->all_reg.VEDU_QPG_SKIN.bits.qpg_skin_max_qp;//DIST_PROTOCOL(vcpi_protocol, 0x1E, 0x33); + D32.bits.qpg_skin_qp_delta = channelcfg->all_reg.VEDU_QPG_SKIN.bits.qpg_skin_qp_delta;//DIST_PROTOCOL(vcpi_protocol, 0x2, 0x3); + pAllReg->VEDU_QPG_SKIN.u32 = D32.u32; + } + + { + U_VEDU_QPG_INTRA_DET D32; + D32.bits.qpg_intra_det_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_intra_det_max_qp = 0x33; + D32.bits.qpg_intra_det_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0x4, 0x3); + pAllReg->VEDU_QPG_INTRA_DET.u32 = D32.u32; + } + + { + U_VEDU_QPG_H264_SMOOTH D32; + D32.bits.qpg_h264_smooth_min_qp = DIST_PROTOCOL(vcpi_protocol, 0x0, 0xA); + D32.bits.qpg_h264_smooth_max_qp = DIST_PROTOCOL(vcpi_protocol, 0, 0x2D); + D32.bits.qpg_h264_smooth_qp_delta = DIST_PROTOCOL(vcpi_protocol, 0, 0x5); + D32.bits.qpg_h264_smooth_qp_delta1 = DIST_PROTOCOL(vcpi_protocol, 0, 0x3); + pAllReg->VEDU_QPG_H264_SMOOTH.u32 = D32.u32; + } + + { + U_VEDU_QPG_CU_QP_DELTA_THRESH_REG0 D32; + D32.bits.qpg_cu_qp_delta_thresh0 = DIST_PROTOCOL(vcpi_protocol, 0, 1); + D32.bits.qpg_cu_qp_delta_thresh1 = DIST_PROTOCOL(vcpi_protocol, 0, 1); + D32.bits.qpg_cu_qp_delta_thresh2 = channelcfg->all_reg.VEDU_QPG_CU_QP_DELTA_THRESH_REG0.bits.qpg_cu_qp_delta_thresh2;//DIST_PROTOCOL(vcpi_protocol, 1, 2); + D32.bits.qpg_cu_qp_delta_thresh3 = channelcfg->all_reg.VEDU_QPG_CU_QP_DELTA_THRESH_REG0.bits.qpg_cu_qp_delta_thresh3;//DIST_PROTOCOL(vcpi_protocol, 1, 2); + pAllReg->VEDU_QPG_CU_QP_DELTA_THRESH_REG0.u32 = D32.u32; + } + + { + U_VEDU_QPG_CU_QP_DELTA_THRESH_REG1 D32; + D32.bits.qpg_cu_qp_delta_thresh4 = DIST_PROTOCOL(vcpi_protocol, 3, 3); + D32.bits.qpg_cu_qp_delta_thresh5 = DIST_PROTOCOL(vcpi_protocol, 3, 3); + D32.bits.qpg_cu_qp_delta_thresh6 = DIST_PROTOCOL(vcpi_protocol, 5, 5); + D32.bits.qpg_cu_qp_delta_thresh7 = DIST_PROTOCOL(vcpi_protocol, 5, 5); + pAllReg->VEDU_QPG_CU_QP_DELTA_THRESH_REG1.u32 = D32.u32; + } + + { + U_VEDU_QPG_CU_QP_DELTA_THRESH_REG2 D32; + D32.bits.qpg_cu_qp_delta_thresh8 = DIST_PROTOCOL(vcpi_protocol, 0xA, 0x8); + D32.bits.qpg_cu_qp_delta_thresh9 = channelcfg->all_reg.VEDU_QPG_CU_QP_DELTA_THRESH_REG2.bits.qpg_cu_qp_delta_thresh9;//DIST_PROTOCOL(vcpi_protocol, 0xA, 0x8); + D32.bits.qpg_cu_qp_delta_thresh10 = DIST_PROTOCOL(vcpi_protocol, 0x14, 0x8); + D32.bits.qpg_cu_qp_delta_thresh11 = channelcfg->all_reg.VEDU_QPG_CU_QP_DELTA_THRESH_REG2.bits.qpg_cu_qp_delta_thresh11;//DIST_PROTOCOL(vcpi_protocol, 0x14, 0xF); + pAllReg->VEDU_QPG_CU_QP_DELTA_THRESH_REG2.u32 = D32.u32; + } + + { + U_VEDU_QPG_CU_QP_DELTA_THRESH_REG3 D32; + D32.bits.qpg_cu_qp_delta_thresh12 = DIST_PROTOCOL(vcpi_protocol, 0xFF, 0x14); + D32.bits.qpg_cu_qp_delta_thresh13 = DIST_PROTOCOL(vcpi_protocol, 0xFF, 0x14); + D32.bits.qpg_cu_qp_delta_thresh14 = DIST_PROTOCOL(vcpi_protocol, 0xFF, 0x19); + D32.bits.qpg_cu_qp_delta_thresh15 = DIST_PROTOCOL(vcpi_protocol, 0xFF, 0x19); + pAllReg->VEDU_QPG_CU_QP_DELTA_THRESH_REG3.u32 = D32.u32; + } + + { + U_VEDU_QPG_DELTA_LEVEL D32; + D32.bits.qpg_qp_delta_level_0 = 1; + D32.bits.qpg_qp_delta_level_1 = 1; + D32.bits.qpg_qp_delta_level_2 = 1; + D32.bits.qpg_qp_delta_level_3 = 1; + D32.bits.qpg_qp_delta_level_4 = 1; + D32.bits.qpg_qp_delta_level_5 = 1; + D32.bits.qpg_qp_delta_level_6 = 1; + D32.bits.qpg_qp_delta_level_7 = 1; + D32.bits.qpg_qp_delta_level_8 = 1; + D32.bits.qpg_qp_delta_level_9 = 1; + D32.bits.qpg_qp_delta_level_10 = 1; + D32.bits.qpg_qp_delta_level_11 = 1; + D32.bits.qpg_qp_delta_level_12 = 1; + D32.bits.qpg_qp_delta_level_13 = 1; + D32.bits.qpg_qp_delta_level_14 = 1; + D32.bits.qpg_qp_delta_level_15 = 1; + pAllReg->VEDU_QPG_DELTA_LEVEL.u32 = D32.u32; + } + + { + U_VEDU_QPG_MADI_SWITCH_THR D32; + D32.bits.qpg_qp_madi_switch_thr = 0x8; + pAllReg->VEDU_QPG_MADI_SWITCH_THR.u32 = D32.u32; + } + + { + U_VEDU_QPG_CU32_DELTA D32; + D32.bits.qpg_cu32_delta_low = 0xC; + D32.bits.qpg_cu32_delta_high = 0xC; + pAllReg->VEDU_QPG_CU32_DELTA.u32 = D32.u32; + } + + { + U_VEDU_QPG_LAMBDA_MODE D32; + D32.bits.qpg_lambda_qp_offset = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x1A); + D32.bits.qpg_rdo_lambda_choose_mode = 0; + D32.bits.qpg_lambda_inter_stredge_en = DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_QPG_LAMBDA_MODE.u32 = D32.u32; + } + + { + U_VEDU_QPG_QP_RESTRAIN D32; + D32.bits.qpg_qp_restrain_madi_thr = DIST_PROTOCOL(vcpi_protocol, 0xA, 0x8); + D32.bits.qpg_qp_restrain_en = DIST_PROTOCOL(vcpi_protocol, 0x1, 0); + D32.bits.qpg_qp_restrain_mode = 0; + D32.bits.qpg_qp_restrain_delta_blk16 = DIST_PROTOCOL(vcpi_protocol, 0x4, 1); + D32.bits.qpg_qp_restrain_delta_blk32 = DIST_PROTOCOL(vcpi_protocol, 0x5, 3); + pAllReg->VEDU_QPG_QP_RESTRAIN.u32 = D32.u32; + } + + { + pAllReg->VEDU_QPG_CU_MIN_SAD_THRESH_0 = 0x0C080401;//channelcfg->all_reg.VEDU_QPG_CU_MIN_SAD_THRESH_0; + } + + { + pAllReg->VEDU_QPG_CU_MIN_SAD_THRESH_1 = 0xB4825A3C;//channelcfg->all_reg.VEDU_QPG_CU_MIN_SAD_THRESH_1; + } + + { + U_VEDU_QPG_CU_MIN_SAD_REG D32; + D32.bits.qpg_min_sad_level = DIST_PROTOCOL(vcpi_protocol, 0x5555, 0x5595); + D32.bits.qpg_low_min_sad_mode = 0; + D32.bits.qpg_high_min_sad_mode = 0; + D32.bits.qpg_min_sad_madi_en = DIST_PROTOCOL(vcpi_protocol, 0x1, 0x0); + D32.bits.qpg_min_sad_qp_restrain_en = 0; + pAllReg->VEDU_QPG_CU_MIN_SAD_REG.u32 = D32.u32; + } + + { + U_VEDU_QPG_FLAT_REGION D32; + D32.bits.qpg_flat_region_qp_delta = DIST_PROTOCOL(vcpi_protocol, 5, 0); // DIST_PROTOCOL(vcpi_protocol, 5, 5); + D32.bits.qpg_flat_region_max_qp = 0x33; + D32.bits.qpg_flat_region_min_qp = DIST_PROTOCOL(vcpi_protocol, 0xF, 0); + D32.bits.vcpi_cu32_use_cu16_mean_en = 0; + pAllReg->VEDU_QPG_FLAT_REGION.u32 = D32.u32; + } + + { + U_VEDU_IME_INTER_MODE D32; + D32.bits.ime_layer3to2_en = 0; + D32.bits.ime_inter8x8_en = DIST_PROTOCOL(vcpi_protocol, 0, 1); + D32.bits.ime_flat_region_force_low3layer = 0; + D32.bits.ime_high3pre_en = 0; + D32.bits.ime_intra4_lowpow_en = 0; + pAllReg->VEDU_IME_INTER_MODE.u32 = D32.u32; + } + + { + pAllReg->VEDU_IME_RDOCFG.u32 = 0; + } + + { + U_VEDU_IME_FME_LPOW_THR D32; + D32.bits.ime_lowpow_fme_thr0 = 0xA; + D32.bits.ime_lowpow_fme_thr1 = DIST_PROTOCOL(vcpi_protocol, 0x10, 0x14); + pAllReg->VEDU_IME_FME_LPOW_THR.u32 = D32.u32; + } + + { + U_VEDU_IME_LAYER3TO2_THR D32; + D32.bits.ime_layer3to2_thr0 = 0x70; + D32.bits.ime_layer3to2_thr1 = 0x10E; + pAllReg->VEDU_IME_LAYER3TO2_THR.u32 = D32.u32; + } + + { + U_VEDU_IME_LAYER3TO2_THR1 D32; + D32.bits.ime_layer3to2_cost_diff_thr = 0x100; + pAllReg->VEDU_IME_LAYER3TO2_THR1.u32 = D32.u32; + } + + { + U_VEDU_IME_LAYER3TO1_THR D32; + D32.bits.ime_layer3to1_en = 0; + D32.bits.ime_layer3to1_pu64_madi_thr = 5; + pAllReg->VEDU_IME_LAYER3TO1_THR.u32 = D32.u32; + } + + { + U_VEDU_IME_LAYER3TO1_THR1 D32; + D32.bits.ime_layer3to1_pu32_cost_thr = 0xBB8; + D32.bits.ime_layer3to1_pu64_cost_thr = 0x1000; + pAllReg->VEDU_IME_LAYER3TO1_THR1.u32 = D32.u32; + } + + { + pAllReg->VEDU_FME_BIAS_COST0.u32 = 0; + } + + { + pAllReg->VEDU_FME_BIAS_COST1.u32 = 0; + } + + { + U_VEDU_FME_PU64_LWP D32; + D32.bits.fme_pu64_lwp_flag = channelcfg->all_reg.VEDU_FME_PU64_LWP.bits.fme_pu64_lwp_flag;//0x1; + pAllReg->VEDU_FME_PU64_LWP.u32 = D32.u32; + } + + { + U_VEDU_MRG_FORCE_ZERO_EN D32; + D32.bits.mrg_force_zero_en = channelcfg->all_reg.VEDU_MRG_FORCE_ZERO_EN.bits.mrg_force_zero_en;//DIST_PROTOCOL(vcpi_protocol, 0x1, 0x0); + D32.bits.mrg_force_y_zero_en = DIST_PROTOCOL(vcpi_protocol, 0x1, 0x0); + D32.bits.mrg_force_u_zero_en = channelcfg->all_reg.VEDU_MRG_FORCE_ZERO_EN.bits.mrg_force_u_zero_en;//DIST_PROTOCOL(vcpi_protocol, 0x1, 0x0); + D32.bits.mrg_force_v_zero_en = channelcfg->all_reg.VEDU_MRG_FORCE_ZERO_EN.bits.mrg_force_v_zero_en;//DIST_PROTOCOL(vcpi_protocol, 0x1, 0x0); + D32.bits.fme_lpw_en = 0; + D32.bits.dct4_en = DIST_PROTOCOL(vcpi_protocol, 1, 0); + D32.bits.force_adapt_en = 0; + D32.bits.rqt_bias_weight = 0; + D32.bits.fme_lpw_th = 0x40; + pAllReg->VEDU_MRG_FORCE_ZERO_EN.u32 = D32.u32; + } + + { + pAllReg->VEDU_MRG_FORCE_SKIP_EN.u32 = 0; + } + + { + pAllReg->VEDU_MRG_BIAS_COST0.u32 = 0; //02; + } + + { + pAllReg->VEDU_MRG_BIAS_COST1.u32 = 0; + } + + { + pAllReg->VEDU_MRG_ABS_OFFSET0.u32 = 0; + } + + { + pAllReg->VEDU_MRG_ABS_OFFSET1.u32 = 0; + } + + { + pAllReg->VEDU_MRG_ADJ_WEIGHT.u32 = 0; + } + + { + pAllReg->VEDU_INTRA_CFG.u32 = 0; + } + + { + U_VEDU_INTRA_SMOOTH D32; + D32.bits.intra_smooth = DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_INTRA_SMOOTH.u32 = D32.u32; + } + + { + U_VEDU_INTRA_BIT_WEIGHT D32; + D32.bits.intra_bit_weight = DIST_PROTOCOL(vcpi_protocol, 0xD, 0); + pAllReg->VEDU_INTRA_BIT_WEIGHT.u32 = D32.u32; + } + + { + pAllReg->VEDU_INTRA_RDO_COST_OFFSET_0.u32 = 0; + } + + { + pAllReg->VEDU_INTRA_RDO_COST_OFFSET_1.u32 = 0; + } + + { + pAllReg->VEDU_INTRA_NO_DC_COST_OFFSET_0.u32 = 0; + } + + { + pAllReg->VEDU_INTRA_NO_DC_COST_OFFSET_1.u32 = 0; + } + + { + pAllReg->VEDU_INTRA_CHNL4_ANG_0EN.u32 = DIST_PROTOCOL(vcpi_protocol, (0xffffffff | 0x2), (0xffffffff | 0x4)); + pAllReg->VEDU_INTRA_CHNL4_ANG_1EN.u32 = (7 & 0x7); + } + + { + pAllReg->VEDU_INTRA_CHNL8_ANG_0EN.u32 = DIST_PROTOCOL(vcpi_protocol, (0xffffffff | 0x2), (0xffffffff | 0x4)); + pAllReg->VEDU_INTRA_CHNL8_ANG_1EN.u32 = (7 & 0x7); + } + + { + pAllReg->VEDU_INTRA_CHNL16_ANG_0EN.u32 = DIST_PROTOCOL(vcpi_protocol, (0xffffffff | 0x2), (0xffffffff | 0x4)); + pAllReg->VEDU_INTRA_CHNL16_ANG_1EN.u32 = (7 & 0x7); + } + + { + pAllReg->VEDU_INTRA_CHNL32_ANG_0EN.u32 = (0xffffffff | 0x2); + pAllReg->VEDU_INTRA_CHNL32_ANG_1EN.u32 = (7 & 0x7); + + } + + { + pAllReg->VEDU_INTRA_RDO_COST_OFFSET_3.u32 = 0; + } + + { + U_VEDU_PMV_TMV_EN D32; + D32.bits.pmv_tmv_en = DIST_PROTOCOL(vcpi_protocol, 1, 0); + pAllReg->VEDU_PMV_TMV_EN.u32 = D32.u32; + } + + { + U_VEDU_TQITQ_DEADZONE D32; + D32.bits.tqitq_deadzone_intra_slice = 0xAB; + D32.bits.tqitq_deadzone_inter_slice = 0x55; + pAllReg->VEDU_TQITQ_DEADZONE.u32 = D32.u32; + } + + { + U_VEDU_SEL_OFFSET_STRENGTH D32; + D32.bits.sel_offset_strength = DIST_PROTOCOL(vcpi_protocol, 0, 2); + pAllReg->VEDU_SEL_OFFSET_STRENGTH.u32 = D32.u32; + } + + { + U_VEDU_SEL_CU32_DC_AC_TH_OFFSET D32; + D32.bits.sel_cu32_dc_ac_th_offset = DIST_PROTOCOL(vcpi_protocol, 0, 1); + pAllReg->VEDU_SEL_CU32_DC_AC_TH_OFFSET.u32 = D32.u32; + } + + { + U_VEDU_SEL_CU32_QP_TH D32; + D32.bits.sel_cu32_qp0_th = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x26); + D32.bits.sel_cu32_qp1_th = DIST_PROTOCOL(vcpi_protocol, 0x0, 0x21); + pAllReg->VEDU_SEL_CU32_QP_TH.u32 = D32.u32; + } + + { + U_VEDU_SEL_RES_DC_AC_TH D32; + D32.bits.sel_res16_luma_dc_th = DIST_PROTOCOL(vcpi_protocol, 0, 3); + D32.bits.sel_res16_chroma_dc_th = DIST_PROTOCOL(vcpi_protocol, 0, 2); + D32.bits.sel_res16_luma_ac_th = DIST_PROTOCOL(vcpi_protocol, 0, 3); + D32.bits.sel_res16_chroma_ac_th = DIST_PROTOCOL(vcpi_protocol, 0, 2); + D32.bits.sel_res32_luma_dc_th = DIST_PROTOCOL(vcpi_protocol, 0, 4); + D32.bits.sel_res32_chroma_dc_th = DIST_PROTOCOL(vcpi_protocol, 0, 3); + D32.bits.sel_res32_luma_ac_th = DIST_PROTOCOL(vcpi_protocol, 0, 4); + D32.bits.sel_res32_chroma_ac_th = DIST_PROTOCOL(vcpi_protocol, 0, 3); + pAllReg->VEDU_SEL_RES_DC_AC_TH.u32 = D32.u32; + } + + { + U_VEDU_EMAR_WAIT_TIM_OUT D32; + D32.bits.vcpi_wtmax = 0xFF; + D32.bits.vcpi_rtmax = 0xFF; + pAllReg->VEDU_EMAR_WAIT_TIM_OUT.u32 = D32.u32; + } + + { + U_VEDU_EMAR_RCH_RPT_TH0 D32; + D32.bits.vcpi_ch00_rrmax = 0xF; + D32.bits.vcpi_ch01_rrmax = 0xF; + D32.bits.vcpi_ch02_rrmax = 0xF; + D32.bits.vcpi_ch03_rrmax = 0xF; + D32.bits.vcpi_ch04_rrmax = 0xF; + D32.bits.vcpi_ch05_rrmax = 0xF; + pAllReg->VEDU_EMAR_RCH_RPT_TH0.u32 = D32.u32; + } + + { + U_VEDU_EMAR_RCH_RPT_TH1 D32; + D32.bits.vcpi_ch06_rrmax = 0xF; + D32.bits.vcpi_ch07_rrmax = 0xF; + D32.bits.vcpi_ch08_rrmax = 0xF; + D32.bits.vcpi_ch09_rrmax = 0xF; + D32.bits.vcpi_ch10_rrmax = 0xF; + D32.bits.vcpi_ch11_rrmax = 0xF; + pAllReg->VEDU_EMAR_RCH_RPT_TH1.u32 = D32.u32; + } + + { + U_VEDU_EMAR_RCH_RPT_TH2 D32; + D32.bits.vcpi_ch12_rrmax = 0xF; + pAllReg->VEDU_EMAR_RCH_RPT_TH2.u32 = D32.u32; + } + + { + U_VEDU_EMAR_WCH_RPT_TH0 D32; + D32.bits.vcpi_ch00_wrmax = 0xF; + D32.bits.vcpi_ch01_wrmax = 0xF; + D32.bits.vcpi_ch02_wrmax = 0xF; + D32.bits.vcpi_ch03_wrmax = 0xF; + D32.bits.vcpi_ch04_wrmax = 0xF; + D32.bits.vcpi_ch05_wrmax = 0xF; + pAllReg->VEDU_EMAR_WCH_RPT_TH0.u32 = D32.u32; + } + + { + U_VEDU_EMAR_WCH_RPT_TH1 D32; + D32.bits.vcpi_ch06_wrmax = 0xF; + D32.bits.vcpi_ch07_wrmax = 0xF; + D32.bits.vcpi_ch08_wrmax = 0xF; + D32.bits.vcpi_ch09_wrmax = 0xF; + D32.bits.vcpi_ch10_wrmax = 0xF; + D32.bits.vcpi_ch11_wrmax = 0xF; + pAllReg->VEDU_EMAR_WCH_RPT_TH1.u32 = D32.u32; + } + + { + U_VEDU_EMAR_WCH_RPT_TH2 D32; + D32.bits.vcpi_ch12_wrmax = 0xF; + D32.bits.vcpi_ch13_wrmax = 0xF; + D32.bits.vcpi_ch14_wrmax = 0xF; + pAllReg->VEDU_EMAR_WCH_RPT_TH2.u32 = D32.u32; + } + + { + pAllReg->VEDU_EMAR_SCRAMBLE_TYPE.u32 = 0; + + } + { + pAllReg->VEDU_PACK_SYNTAX_CONFIG = 0; + } + + { + U_VEDU_PACK_CU_PARAMETER D32; + D32.bits.pack_vcpi2cu_tq_bypass_enabled_flag = 0; + D32.bits.pack_vcpi2cu_qp_min_cu_size = 2; + pAllReg->VEDU_PACK_CU_PARAMETER.u32 = D32.u32; + } + + { + U_VEDU_PACK_PCM_PARAMETER D32; + D32.bits.pack_vcpi2pu_log2_min_ipcm_cbsizey = 3; + D32.bits.pack_vcpi2pu_log2_max_ipcm_cbsizey = 3; + pAllReg->VEDU_PACK_PCM_PARAMETER.u32 = D32.u32; + } + + { + U_VEDU_PACK_TF_SKIP_FLAG D32; + D32.bits.pack_vcpi2res_tf_skip_enabled_flag = 0; + pAllReg->VEDU_PACK_TF_SKIP_FLAG.u32 = D32.u32; + } + + { + U_VEDU_VLCST_PTBITS_EN D32; + D32.bits.vlcst_ptbits_en = 0; + pAllReg->VEDU_VLCST_PTBITS_EN.u32 = D32.u32; + } + + { + pAllReg->VEDU_VLCST_PTBITS = 0; + } + + VeduHal_CfgReg_IntraSet(channelcfg); + + VeduHal_CfgReg_LambdaSet(channelcfg); + + VeduHal_CfgReg_QpgmapSet(channelcfg); + + VeduHal_CfgReg_AddrSet(channelcfg); + + VeduHal_CfgReg_SlcHeadSet(channelcfg); + + //------------------------------MMU MAIN REG CFG--------------------------------------------- + //MMU ABOUT SETTING + ////MST INT_NS + + pAllReg->MMU_PRE_GLB_SCR.bits.glb_scr = channelcfg->all_reg.MMU_PRE_GLB_SCR.bits.glb_scr;//(~pEncPara_channel->bSecureFlag); + + pAllReg->SMMU_MSTR_GLB_BYPASS.bits.glb_bypass = channelcfg->all_reg.SMMU_MSTR_GLB_BYPASS.bits.glb_bypass;//pEncPara_channel->bMMUByPass; + pAllReg->SMMU_SCR.bits.glb_bypass = channelcfg->all_reg.SMMU_SCR.bits.glb_bypass;//pEncPara_channel->bMMUByPass; + + VeduHal_CfgReg_SMMUSet(channelcfg); + + VeduHal_CfgReg_PREMMUSet(channelcfg); + +} + diff --git a/drivers/vcodec/venc_hivna/hi_drv_mem.c b/drivers/vcodec/venc_hivna/hi_drv_mem.c new file mode 100755 index 000000000000..6c5ea795a5b4 --- /dev/null +++ b/drivers/vcodec/venc_hivna/hi_drv_mem.c @@ -0,0 +1,239 @@ +#include "drv_venc_osal.h" +#include "hi_drv_mem.h" +#include + + +#define MAX_BUFFER_SIZE (10*1024) + +char *g_sbuf = NULL; +int g_venc_node_num = 0; + +struct semaphore g_VencMemSem; +venc_mem_buf g_venc_mem_node[MAX_KMALLOC_MEM_NODE]; + +VENC_SMMU_ERR_ADDR g_smmu_err_mem; + +int DRV_MEM_INIT(void) +{ + char *sbuf; + int s32Ret; + MEM_BUFFER_S MEM_SMMU_RD_ADDR; + MEM_BUFFER_S MEM_SMMU_WR_ADDR; + + HiVENC_INIT_MUTEX(&g_VencMemSem); + + sbuf = HiMemVAlloc(MAX_BUFFER_SIZE); + if (!sbuf) { + HI_FATAL_VENC("call vmalloc failed\n"); + return HI_FAILURE; + } + + HiMemSet((void *)&g_venc_mem_node, 0, MAX_KMALLOC_MEM_NODE*sizeof(g_venc_mem_node[0])); + HiMemSet((void *)&g_smmu_err_mem, 0, sizeof(g_smmu_err_mem)); + HiMemSet((void *)&MEM_SMMU_RD_ADDR, 0, sizeof(MEM_BUFFER_S)); + HiMemSet((void *)&MEM_SMMU_WR_ADDR, 0, sizeof(MEM_BUFFER_S)); + + MEM_SMMU_RD_ADDR.u32Size = SMMU_RWERRADDR_SIZE; + s32Ret = DRV_MEM_KAlloc("SMMU_RDERR", "OMXVENC", &MEM_SMMU_RD_ADDR); + if (s32Ret != HI_SUCCESS ) { + HI_ERR_VENC("SMMU_RDERR alloc failed\n"); + goto err_sbuf_exit; + } + + MEM_SMMU_WR_ADDR.u32Size = SMMU_RWERRADDR_SIZE; + s32Ret = DRV_MEM_KAlloc("SMMU_WRERR", "OMXVENC", &MEM_SMMU_WR_ADDR); + if (s32Ret != HI_SUCCESS ) { + HI_ERR_VENC("SMMU_WRERR alloc failed\n"); + goto err_rd_smmu_exit; + } + + g_smmu_err_mem.RdAddr = MEM_SMMU_RD_ADDR.u64StartPhyAddr;//config alloc phyaddr,in order system don't dump + g_smmu_err_mem.WrAddr = MEM_SMMU_WR_ADDR.u64StartPhyAddr; + g_sbuf = sbuf; + HiMemSet((void *)g_sbuf, 0, MAX_BUFFER_SIZE); + + return HI_SUCCESS; + +err_rd_smmu_exit: + DRV_MEM_KFree(&MEM_SMMU_RD_ADDR); +err_sbuf_exit: + HiMemVFree(sbuf); + + return HI_FAILURE; + +} + +int DRV_MEM_EXIT(void) +{ + int i; + + if (g_sbuf) { + HiMemVFree(g_sbuf); + g_sbuf = NULL; + } + + /* Exit kfree mem for register's VEDU_COMN1_REGS.COMN1_SMMU_ERR_RDADDRR*/ + for (i = 0; i < MAX_KMALLOC_MEM_NODE; i++) { + if (g_venc_mem_node[i].virt_addr != NULL) { + kfree(g_venc_mem_node[i].virt_addr); + HiMemSet(&g_venc_mem_node[i], 0, sizeof(g_venc_mem_node[i])); + } + } + + g_venc_node_num = 0; + + return HI_SUCCESS; +} + +/* kalloc */ +int DRV_MEM_KAlloc(const char* bufName, const char *zone_name, MEM_BUFFER_S *psMBuf) +{ + unsigned int i; + int ret = HI_FAILURE; + void *virt_addr = NULL; + + if (psMBuf == NULL || psMBuf->u32Size == 0) { + HI_FATAL_VENC("invalid Param, psMBuf is NULL or size is zero\n"); + return ret; + } + + if (HiVENC_DOWN_INTERRUPTIBLE(&g_VencMemSem)) { + HI_FATAL_VENC("Kalloc, down_interruptible failed\n"); + return ret; + } + + for (i = 0; i < MAX_KMALLOC_MEM_NODE; i++) { + if ((0 == g_venc_mem_node[i].phys_addr) && (g_venc_mem_node[i].virt_addr == NULL)) { + break; + } + } + + if (i == MAX_KMALLOC_MEM_NODE) { + HI_FATAL_VENC("No free ion mem node\n"); + goto err_exit; + } + + virt_addr = kmalloc(psMBuf->u32Size, GFP_KERNEL | GFP_DMA);/*lint !e747*/ + if (IS_ERR_OR_NULL(virt_addr)) { + HI_FATAL_VENC("call kzalloc failed, size : %d\n", psMBuf->u32Size); + goto err_exit; + } + + memset(virt_addr, 0, psMBuf->u32Size); /* unsafe_function_ignore: memset */ /*lint !e668*/ + + psMBuf->pStartVirAddr = virt_addr; + psMBuf->u64StartPhyAddr = __pa(virt_addr);/*lint !e648 !e834 !e712*/ + + snprintf(g_venc_mem_node[i].node_name, MAX_MEM_NAME_LEN, "%s", bufName); /* unsafe_function_ignore: snprintf */ + + snprintf(g_venc_mem_node[i].zone_name, MAX_MEM_NAME_LEN, "%s", zone_name); /* unsafe_function_ignore: snprintf */ + + g_venc_mem_node[i].virt_addr = psMBuf->pStartVirAddr; + g_venc_mem_node[i].phys_addr = psMBuf->u64StartPhyAddr; + g_venc_mem_node[i].size = psMBuf->u32Size; + + g_venc_node_num++; + + ret = HI_SUCCESS; + +err_exit: + HiVENC_UP_INTERRUPTIBLE(&g_VencMemSem); + return ret; /*lint !e593*/ +} /*lint !e593*/ + +/* kfree */ +int DRV_MEM_KFree(const MEM_BUFFER_S *psMBuf) +{ + unsigned int i; + int ret = HI_FAILURE; + + if (NULL == psMBuf || psMBuf->pStartVirAddr == NULL || psMBuf->u64StartPhyAddr == 0) { + HI_FATAL_VENC("invalid Parameters\n"); + return ret; + } + + if (HiVENC_DOWN_INTERRUPTIBLE(&g_VencMemSem)) { + HI_FATAL_VENC("Kfree, down interruptible failed\n"); + return ret; + } + + + for (i=0; iu64StartPhyAddr == g_venc_mem_node[i].phys_addr) && + (psMBuf->pStartVirAddr == g_venc_mem_node[i].virt_addr)) + { + break; + } + } + + if(i == MAX_KMALLOC_MEM_NODE) { + HI_FATAL_VENC("No free ion mem node\n"); + goto err_exit; + } + + kfree(g_venc_mem_node[i].virt_addr); + HiMemSet(&g_venc_mem_node[i], 0, sizeof(g_venc_mem_node[i]));/*lint !e866 */ + g_venc_node_num = (g_venc_node_num > 0)?(g_venc_node_num-1):0; + + ret = HI_SUCCESS; + +err_exit: + HiVENC_UP_INTERRUPTIBLE(&g_VencMemSem); + return ret; +} + +int HI_DRV_UserCopy(struct file *file, unsigned int cmd, unsigned long arg, + long (*func)(struct file *file, unsigned int cmd, unsigned long uarg)) +{ + //HI_CHAR sbuf[768]; + void *parg = NULL; + int err = -EINVAL; + + /* Copy arguments into temp kernel buffer */ + if (!(void __user*)arg) { + HI_FATAL_VENC("arg is NULL\n"); + goto out; + } + + if (_IOC_SIZE(cmd) <= MAX_BUFFER_SIZE) { + parg = g_sbuf; + } else { + HI_FATAL_VENC("cmd size is too long\n"); + goto out; + } + + if (!parg) { + HI_FATAL_VENC("parg is NULL\n"); + goto out; + } + err = -EFAULT; + if (_IOC_DIR(cmd) & _IOC_WRITE) { + if (copy_from_user(parg, (void __user*)arg, _IOC_SIZE(cmd))) {/*lint !e747 */ + HI_FATAL_VENC("copy_from_user failed, cmd value is 0x%x\n", cmd); + goto out; + } + } + + /* call driver */ + err = func(file, cmd, (long)(parg)); /*lint !e732 !e712*/ + if (err == -ENOIOCTLCMD) + err = -EINVAL; + if (err < 0) + goto out; + + /* Copy results into user buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_READ: + case (_IOC_WRITE | _IOC_READ): + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) {/*lint !e747 */ + HI_FATAL_VENC("copy_to_user failed, cmd value is 0x%x\n", cmd); + err = -EFAULT; + } + break; + default: + goto out; + } +out: + return err; +} + diff --git a/drivers/vcodec/venc_hivna/hi_drv_mem.h b/drivers/vcodec/venc_hivna/hi_drv_mem.h new file mode 100755 index 000000000000..5025c8795136 --- /dev/null +++ b/drivers/vcodec/venc_hivna/hi_drv_mem.h @@ -0,0 +1,72 @@ +/* +* Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd. +* +* File Name : hi_type.h +* Version : Initial Draft +* Author : Hisilicon multimedia software group +* Created : 2005/4/23 +* +* Last Modified : +* Description : The common data type defination +* Function List : +* +* History : +* 1.Date : 2008/06/28 +* Author : c42025 +* Modification: modified definition for HI_S8 +* +* 2.Date : 2008/10/31 +* Author : z44949 +* Modification: Translate the chinese comment +*/ +#ifndef __HI_DRV_MEM_H__ +#define __HI_DRV_MEM_H__ +#include "drv_venc.h" +#include +#include +#include + + +#define MAX_MEM_NAME_LEN (15) +#define MAX_KMALLOC_MEM_NODE (16) /*1 channel need 2 node ,there is have max 8 channels*/ +#define MAX_ION_MEM_NODE (200) +#define SMMU_RWERRADDR_SIZE (128) + +typedef struct { + unsigned long long RdAddr; // HI_U64 + unsigned long long WrAddr; // HI_U64 +} VENC_SMMU_ERR_ADDR; + +typedef struct { + void *pStartVirAddr; + unsigned long long u64StartPhyAddr; // HI_U64 + unsigned int u32Size; + unsigned char u8IsMapped; + unsigned int u32ShareFd; +} MEM_BUFFER_S; + +typedef struct { + char node_name[MAX_MEM_NAME_LEN]; + char zone_name[MAX_MEM_NAME_LEN]; + void* virt_addr; + unsigned long long phys_addr; // HI_U64 + unsigned int size; + struct ion_handle *handle; +} venc_mem_buf; + +/*********************************************************************************** + memory menage relative functions +***********************************************************************************/ +int HI_DRV_UserCopy(struct file *file, unsigned int cmd, unsigned long arg, long (*func)(struct file *file, unsigned int cmd, unsigned long uarg)); + +/**************************************platform.h**************************************************/ +int DRV_MEM_INIT(void); +int DRV_MEM_EXIT(void); +int DRV_MEM_KAlloc(const char* bufName, const char *zone_name, MEM_BUFFER_S *psMBuf); +int DRV_MEM_KFree(const MEM_BUFFER_S *psMBuf); + +/**************************************************************************************/ + + +#endif /* __HI_DRV_MEM_H__ */ + diff --git a/drivers/vcodec/venc_hivna/venc_regulator.c b/drivers/vcodec/venc_hivna/venc_regulator.c new file mode 100755 index 000000000000..878fda0bdb00 --- /dev/null +++ b/drivers/vcodec/venc_hivna/venc_regulator.c @@ -0,0 +1,275 @@ +#include +#include +#include +#include +#include + +#include "venc_regulator.h" +#include "drv_venc_osal.h" +#include "drv_venc.h" + +#define VENC_CLK_RATE "enc_clk_rate" +#define VENC_REGULATOR_NAME "ldo_venc" +#define MEDIA_REGULATOR_NAME "ldo_media" +#define VENC_CLOCK_NAME "clk_gate_vencfreq" + +static struct clk *g_PvencClk = NULL; +struct iommu_domain *g_hisi_mmu_domain = NULL; +static VeduEfl_DTS_CONFIG_S g_VencDtsConfig; +static VENC_CLK_TYPE g_currClk = VENC_CLK_RATE_LOW; + +static unsigned int g_vencQosMode = 0x2; +static int g_VencPowerOn = 0; +/*lint -e838 -e747 -e774 -e845*/ +static int Venc_Enable_Iommu(struct platform_device *pdev) +{ + struct iommu_domain *hisi_domain = NULL; + struct iommu_domain_data* domain_data = NULL; + struct device *dev = NULL; + //uint64_t phy_pgd_base = 0; + int ret = HI_FAILURE; + + if ((!pdev ) || (!(&pdev->dev))){ + HI_ERR_VENC("%s, invalid Parameters\n", __func__); + return HI_FAILURE; + } + + dev = &pdev->dev; + hisi_domain = iommu_domain_alloc(dev->bus); + if (!hisi_domain) { + HI_ERR_VENC("%s, iommu_domain_alloc failed\n", __func__); + return HI_FAILURE; + } + + ret = iommu_attach_device(hisi_domain, dev); + if (ret){ + HI_ERR_VENC("iommu_attach_device failed\n"); + goto out_free_domain; + } + + g_hisi_mmu_domain = hisi_domain; + domain_data = (struct iommu_domain_data *)(g_hisi_mmu_domain->priv); + if (domain_data == NULL){ + //pCtx->phy_pgd_base = (uint64_t)(domain_data->phy_pgd_base); + //}else{ + goto out_detach_device; + } + + return HI_SUCCESS; + +out_detach_device: + iommu_detach_device(g_hisi_mmu_domain, dev); +out_free_domain: + iommu_domain_free(hisi_domain); + return HI_FAILURE; +} + +static int Venc_Disable_Iommu(struct platform_device *pdev) +{ + if( g_hisi_mmu_domain && pdev) { + iommu_detach_device(g_hisi_mmu_domain, &pdev->dev); + iommu_domain_free(g_hisi_mmu_domain); + g_hisi_mmu_domain = NULL; + return HI_SUCCESS; + } + + return HI_FAILURE; +} + +static int Venc_GetDtsConfigInfo(struct platform_device *pdev, VeduEfl_DTS_CONFIG_S *pDtsConfig) +{ + unsigned int rate_h = 0; + unsigned int rate_n = 0; + unsigned int rate_l = 0; + int ret = HI_FAILURE; + struct resource res; + struct clk *pvenc_clk = NULL; + struct device_node *np = NULL; + struct device *dev = &pdev->dev; + struct iommu_domain_data *domain_data = NULL; + + if (!dev) { + HI_FATAL_VENC("invalid argument, dev is NULL\n"); + return HI_FAILURE; + } + + np = dev->of_node; + + HiMemSet(&res, 0, sizeof(res)); + if ((!np) || (!pDtsConfig)) { + HI_FATAL_VENC("invalid argument np or pDtsConfig is NULL\n"); + return HI_FAILURE; + } + + /* 1 read IRQ num from dts */ + pDtsConfig->VeduIrqNumNorm = irq_of_parse_and_map(np, 0); + if (pDtsConfig->VeduIrqNumNorm == 0) { + HI_FATAL_VENC("parse and map irq VeduIrqNumNorm failed\n"); + return HI_FAILURE; + } + + pDtsConfig->VeduIrqNumProt = irq_of_parse_and_map(np, 1); + if (pDtsConfig->VeduIrqNumProt == 0) { + HI_FATAL_VENC("parse and map irq VeduIrqNumProt failed\n"); + return HI_FAILURE; + } + + pDtsConfig->VeduIrqNumSafe = irq_of_parse_and_map(np, 2); + if (pDtsConfig->VeduIrqNumSafe == 0) { + HI_FATAL_VENC("parse and map irq VeduIrqNumSafe failed\n"); + return HI_FAILURE; + } + + /* 2 read venc register start address, range */ + ret = of_address_to_resource(np, 0, &res); + if (ret) { + HI_FATAL_VENC("address to resource failed, ret value is %d\n", ret); + return HI_FAILURE; + } + pDtsConfig->VencRegBaseAddr = res.start;/*lint !e712 */ + pDtsConfig->VencRegRange = resource_size(&res);/*lint !e712 */ + + /* 3 read venc clk rate [low, high], venc clock */ + pvenc_clk = devm_clk_get(dev, VENC_CLOCK_NAME); + if (IS_ERR_OR_NULL(pvenc_clk)) { + HI_FATAL_VENC("can not get venc clock, pvenc_clk is 0x%pK\n", pvenc_clk); + return HI_FAILURE; + } + g_PvencClk = pvenc_clk; + + ret = of_property_read_u32_index(np, VENC_CLK_RATE, 0, &rate_h); + ret += of_property_read_u32_index(np, VENC_CLK_RATE, 1, &rate_n); + ret += of_property_read_u32_index(np, VENC_CLK_RATE, 2, &rate_l); + if (ret) { + HI_FATAL_VENC("can not get venc rate, return %d\n", ret); + return HI_FAILURE; + } + pDtsConfig->highRate = rate_h; + pDtsConfig->normalRate = rate_n; + pDtsConfig->lowRate = rate_l; + HI_INFO_VENC("venc_clk_rate: highRate:%u, normalRate:%u, lowRate:%u\n", pDtsConfig->highRate, pDtsConfig->normalRate, pDtsConfig->lowRate); + + /* 4 get venc qos mode */ + ret = of_property_read_u32(np, "venc_qos_mode", &g_vencQosMode); + if (ret) { + g_vencQosMode = 0x2; + HI_ERR_VENC("get venc qos mode failed set default\n"); + } + + domain_data = (struct iommu_domain_data *)(g_hisi_mmu_domain->priv); + if (domain_data) { + pDtsConfig->SmmuPageBaseAddr = (uint64_t)(domain_data->phy_pgd_base); + HI_INFO_VENC("SmmuPageBaseAddr is 0x%pK\n", __func__, pDtsConfig->SmmuPageBaseAddr); + } + + return HI_SUCCESS; +} + +int Venc_Regulator_Init(struct platform_device *pdev) +{ + int ret = 0; + + if (!pdev) { + HI_FATAL_VENC("invalid argument\n"); + return HI_FAILURE; + } + + /* 1 create smmu domain */ + ret = Venc_Enable_Iommu(pdev); + if (ret < 0) { + HI_FATAL_VENC("enable venc iommu failed\n"); + return HI_FAILURE; + } + + /* 2 read venc dts info from dts */ + HiMemSet(&g_VencDtsConfig, 0, sizeof(VeduEfl_DTS_CONFIG_S)); + ret = Venc_GetDtsConfigInfo(pdev, &g_VencDtsConfig); + if (ret != HI_SUCCESS) { + HI_FATAL_VENC("get venc DTS config info failed\n"); + return HI_FAILURE; + } + + /* 3 set dts into to efi */ + ret = VENC_SetDtsConfig(&g_VencDtsConfig); + if (ret != HI_SUCCESS) { + HI_FATAL_VENC("set venc DTS config info failed\n"); + return HI_FAILURE; + } + + return HI_SUCCESS; +} + +void Venc_Regulator_Deinit(struct platform_device *pdev) +{ + if (pdev) + Venc_Disable_Iommu(pdev); +} + +int Venc_Regulator_Enable(void) +{ + int ret = HI_FAILURE; + if (1 == g_VencPowerOn) { + return HI_SUCCESS; + } + if(IS_ERR_OR_NULL(g_PvencClk)) { + HI_FATAL_VENC("invalid_argument g_PvencClk:0x%pK\n", + g_PvencClk); + return HI_FAILURE; + } + + ret = clk_prepare_enable(g_PvencClk); + if (ret != 0) { + HI_FATAL_VENC("prepare clk enable failed\n"); + return HI_FAILURE; + } + + ret = clk_set_rate(g_PvencClk, g_VencDtsConfig.lowRate); + if(ret != 0) { + HI_FATAL_VENC("set clk low rate failed\n"); + goto on_error_prepare_clk; + } + + g_currClk = VENC_CLK_RATE_LOW; + + ret = clk_set_rate(g_PvencClk, g_VencDtsConfig.lowRate); + if(ret != 0) { + HI_FATAL_VENC("set clk low rate failed\n"); + goto on_error_prepare_clk; + } + g_VencPowerOn = 1; + + HI_INFO_VENC("++\n"); + return HI_SUCCESS; + +on_error_prepare_clk: + clk_disable_unprepare(g_PvencClk); + + return HI_FAILURE; +} + +int Venc_Regulator_Disable(void) +{ + int ret = HI_FAILURE; + HI_INFO_VENC("Venc_Regulator_Disable\n"); + + if (0 == g_VencPowerOn) { + return HI_SUCCESS; + } + + if(IS_ERR_OR_NULL(g_PvencClk)) { + HI_FATAL_VENC("invalid_argument g_PvencClk:0x%pK\n",g_PvencClk); + return HI_FAILURE; + } + + ret = clk_set_rate(g_PvencClk, g_VencDtsConfig.lowRate); + if(ret != 0) { + HI_ERR_VENC("set clk lowrate:%u failed\n", g_VencDtsConfig.lowRate); + //return HI_FAILURE;//continue, no need return + } + g_currClk = VENC_CLK_RATE_LOW; + clk_disable_unprepare(g_PvencClk); + + g_VencPowerOn = 0; + HI_INFO_VENC("--\n"); + return HI_SUCCESS; +}/*lint !e715 */ diff --git a/drivers/vcodec/venc_hivna/venc_regulator.h b/drivers/vcodec/venc_hivna/venc_regulator.h new file mode 100755 index 000000000000..b7c38d823f64 --- /dev/null +++ b/drivers/vcodec/venc_hivna/venc_regulator.h @@ -0,0 +1,12 @@ +#ifndef __VENC_REGULATOR_H__ +#define __VENC_REGULATOR_H__ +#include "drv_venc.h" +#include +#include + +int Venc_Regulator_Init(struct platform_device *pdev); +void Venc_Regulator_Deinit(struct platform_device *pdev); +int Venc_Regulator_Enable(void); +int Venc_Regulator_Disable(void); +#endif +