From ab920b0a7fbc2ea7d476cda9267e16a222454a18 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sat, 21 Jan 2017 10:26:31 +0800 Subject: [PATCH] clk: hisilicon: fix lock assignment In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Change-Id: I9bb58ef5b79baf86336a07b40e80bcb56f741c6c Signed-off-by: Leo Yan Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/clkgate-separated.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index a47812f56a17..7908bc3c9ec7 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->bit_idx = bit_idx; sclk->flags = clk_gate_flags; sclk->hw.init = &init; + sclk->lock = lock; clk = clk_register(dev, &sclk->hw); if (IS_ERR(clk))