From c021aabeffdc08a2900338868eee35ee8e9b0039 Mon Sep 17 00:00:00 2001 From: liwei213 Date: Tue, 6 Feb 2018 14:37:46 +0800 Subject: [PATCH] drivers/scsi:ufs:add hikey970 ufs driver Modify ufs driver to support both hikey960 and hikey970. Signed-off-by: liwei213 --- .../devicetree/bindings/ufs/hi3660-ufs.txt | 58 -- .../devicetree/bindings/ufs/ufs-hisi.txt | 38 + .../boot/dts/hisilicon/hi3660-hikey960.dts | 9 - arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 5 +- arch/arm64/configs/hikey960_defconfig | 2 +- drivers/scsi/ufs/Kconfig | 16 +- drivers/scsi/ufs/Makefile | 2 +- drivers/scsi/ufs/ufs-hi3660.c | 715 ---------------- drivers/scsi/ufs/ufs-hi3660.h | 170 ---- drivers/scsi/ufs/ufs-hisi.c | 784 ++++++++++++++++++ drivers/scsi/ufs/ufs-hisi.h | 158 ++++ drivers/scsi/ufs/ufs_quirks.h | 6 + drivers/scsi/ufs/ufshcd.c | 16 +- 13 files changed, 1008 insertions(+), 971 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ufs/hi3660-ufs.txt create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt delete mode 100644 drivers/scsi/ufs/ufs-hi3660.c delete mode 100644 drivers/scsi/ufs/ufs-hi3660.h create mode 100644 drivers/scsi/ufs/ufs-hisi.c create mode 100644 drivers/scsi/ufs/ufs-hisi.h diff --git a/Documentation/devicetree/bindings/ufs/hi3660-ufs.txt b/Documentation/devicetree/bindings/ufs/hi3660-ufs.txt deleted file mode 100644 index 461afc8ef017..000000000000 --- a/Documentation/devicetree/bindings/ufs/hi3660-ufs.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Hisilicon Universal Flash Storage (UFS) Host Controller - -UFS nodes are defined to describe on-chip UFS hardware macro. -Each UFS Host Controller should have its own node. - -Required properties: -- compatible : compatible list, contains one of the following - - "hisilicon,hi3660-ufs" for hisi ufs host controller - present on Hi3660 chipset. -- reg : should contain UFS register address space & UFS SYS CTRL register address, -- interrupt-parent : interrupt device -- interrupts : interrupt number -- clocks : List of phandle and clock specifier pairs -- clock-names : List of clock input name strings sorted in the same - order as the clocks property. "clk_ref", "clk_phy" is optional -- resets : reset node register, one reset the clk and the other reset the controller -- reset-names : describe reset node register - -Optional properties for board device: -- ufs-hi3660-use-rate-B : specifies UFS rate-B -- ufs-hi3660-broken-fastauto : specifies no fastauto -- ufs-hi3660-use-HS-GEAR3 : specifies UFS HS-GEAR3 -- ufs-hi3660-use-HS-GEAR2 : specifies UFS HS-GEAR2 -- ufs-hi3660-use-HS-GEAR1 : specifies UFS HS-GEAR1 -- ufs-hi3660-broken-clk-gate-bypass : specifies no clk-gate -- ufs-hi3660-use-one-line : specifies UFS use one line work -- reset-gpio : specifies to reset devices - -Example: - - ufs: ufs@ff3b0000 { - compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3b0000 0x0 0x1000>, - <0x0 0xff3b1000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; - clock-names = "clk_ref", "clk_phy"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - /* offset: 0x84; bit: 7 */ - resets = <&crg_rst 0x84 12>, - <&crg_rst 0x84 7>; - reset-names = "rst", "assert"; - } - - &ufs { - ufs-hi3660-use-rate-B; - ufs-hi3660-broken-fastauto; - ufs-hi3660-use-HS-GEAR3; - ufs-hi3660-broken-clk-gate-bypass; - reset-gpio = <&gpio18 1 0>; - status = "okay"; - } - diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt new file mode 100644 index 000000000000..af6684e02f6a --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt @@ -0,0 +1,38 @@ +* Hisilicon Universal Flash Storage (UFS) Host Controller + +UFS nodes are defined to describe on-chip UFS hardware macro. +Each UFS Host Controller should have its own node. + +Required properties: +- compatible : compatible list, contains one of the following - + "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs + host controller present on Hi36xx chipset. +- reg : should contain UFS register address space & UFS SYS CTRL register address, +- interrupt-parent : interrupt device +- interrupts : interrupt number +- clocks : List of phandle and clock specifier pairs +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. "ref_clk", "phy_clk" is optional +- resets : reset node register, one reset the clk and the other reset the controller +- reset-names : describe reset node register + +Example: + + ufs: ufs@ff3b0000 { + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3b0000 0x0 0x1000>, + <0x0 0xff3b1000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; + clock-names = "ref_clk", "phy_clk"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + /* offset: 0x84; bit: 7 */ + resets = <&crg_rst 0x84 12>, + <&crg_rst 0x84 7>; + reset-names = "rst", "assert"; + }; \ No newline at end of file diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c7dfbd19a51e..10f58961751b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -496,12 +496,3 @@ interrupts = <3 IRQ_TYPE_EDGE_RISING>; }; }; - -&ufs { - ufs-hi3660-use-rate-B; - ufs-hi3660-broken-fastauto; - ufs-hi3660-use-HS-GEAR3; - ufs-hi3660-broken-clk-gate-bypass; - reset-gpio = <&gpio18 1 0>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 791e4a7e1a6a..15398a915ab7 100755 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1180,7 +1180,7 @@ }; ufs: ufs@ff3b0000 { - compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; /* 0: HCI standard */ /* 1: UFS SYS CTRL */ reg = <0x0 0xff3b0000 0x0 0x1000>, @@ -1189,7 +1189,7 @@ interrupts = ; clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; - clock-names = "clk_ref", "clk_phy"; + clock-names = "ref_clk", "phy_clk"; freq-table-hz = <0 0>, <0 0>; /* offset: 0x84; bit: 12 */ /* offset: 0x84; bit: 7 */ @@ -1198,7 +1198,6 @@ reset-names = "rst", "assert"; }; - hub5734_gpio:hub5734_gpio { compatible = "hub5734_gpio"; pinctrl-names = "default"; diff --git a/arch/arm64/configs/hikey960_defconfig b/arch/arm64/configs/hikey960_defconfig index 5d0373f36d4f..47756a0cb728 100644 --- a/arch/arm64/configs/hikey960_defconfig +++ b/arch/arm64/configs/hikey960_defconfig @@ -219,7 +219,7 @@ CONFIG_HISI_HIKEY_USB=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_HI3660=y +CONFIG_SCSI_UFS_HISI=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index 119604ea0aae..48d141ae1b73 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -80,14 +80,6 @@ config SCSI_UFSHCD_PLATFORM If unsure, say N. -config SCSI_UFS_HI3660 - tristate "Hisilicon Hi3660 UFS controller platform driver" - depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM - help - This selects the Hisilicon HI3660 additions to UFSHCD platform driver. - - If unsure, say N. - config SCSI_UFS_DWC_TC_PLATFORM tristate "DesignWare platform support using a G210 Test Chip" depends on SCSI_UFSHCD_PLATFORM @@ -108,3 +100,11 @@ config SCSI_UFS_QCOM Select this if you have UFS controller on QCOM chipset. If unsure, say N. + +config SCSI_UFS_HISI + tristate "Hisilicon Kirin UFS controller platform driver" + depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM + help + This selects the Hisilicon Kirin additions to UFSHCD platform driver. + + If unsure, say N. diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index ae880189f018..6969f4921f14 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -2,7 +2,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o -obj-$(CONFIG_SCSI_UFS_HI3660) += ufs-hi3660.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o +obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o \ No newline at end of file diff --git a/drivers/scsi/ufs/ufs-hi3660.c b/drivers/scsi/ufs/ufs-hi3660.c deleted file mode 100644 index d261dbce10d8..000000000000 --- a/drivers/scsi/ufs/ufs-hi3660.c +++ /dev/null @@ -1,715 +0,0 @@ -/* - * Copyright (c) 2016-2017 Linaro Ltd. - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ufshcd.h" -#include "ufshcd-pltfrm.h" -#include "unipro.h" -#include "ufs-hi3660.h" -#include "ufshci.h" - -static int ufs_hi3660_check_hibern8(struct ufs_hba *hba) -{ - int err; - u32 tx_fsm_val_0; - u32 tx_fsm_val_1; - unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); - - do { - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), - &tx_fsm_val_0); - err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), - &tx_fsm_val_1); - if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && tx_fsm_val_1 == TX_FSM_HIBERN8)) - break; - - /* sleep for max. 200us */ - usleep_range(100, 200); - } while (time_before(jiffies, timeout)); - - /* - * we might have scheduled out for long during polling so - * check the state again. - */ - if (time_after(jiffies, timeout)) { - err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), - &tx_fsm_val_0); - err |= ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), - &tx_fsm_val_1); - } - - if (err) { - dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", - __func__, err); - } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || tx_fsm_val_1 != TX_FSM_HIBERN8) { - err = -1; - dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", - __func__, tx_fsm_val_0, tx_fsm_val_1); - } - - return err; -} - -static void ufs_hi3660_clk_init(struct ufs_hba *hba) -{ - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - - ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); - if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN) - mdelay(1); - /* use abb clk */ - ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL); - ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN); - /* open mphy ref clk */ - ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); -} - -static void ufs_hi3660_soc_init(struct ufs_hba *hba) -{ - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - u32 reg; - - if (!IS_ERR(host->rst)) - reset_control_assert(host->rst); - - /* HC_PSW powerup */ - ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL); - udelay(10); - /* notify PWR ready */ - ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL); - ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0, - UFS_DEVICE_RESET_CTRL); - - if (gpio_is_valid(host->reset_gpio)) - gpio_direction_output(host->reset_gpio, 0); - - reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); - reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK; - /* set cfg clk freq */ - ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); - /* set ref clk freq */ - ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL); - /* bypass ufs clk gate */ - ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS, CLOCK_GATE_BYPASS); - ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); - - /* open psw clk */ - ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL); - /* disable ufshc iso */ - ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL); - /* disable phy iso */ - ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN); - /* notice iso disable */ - ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL); - if (!IS_ERR(host->assert)) - reset_control_deassert(host->assert); - /* disable lp_reset_n */ - ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN); - mdelay(1); - - if (gpio_is_valid(host->reset_gpio)) - gpio_direction_output(host->reset_gpio, 1); - - ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET, - UFS_DEVICE_RESET_CTRL); - - mdelay(20); - - /* - * enable the fix of linereset recovery, - * and enable rx_reset/tx_rest beat - * enable ref_clk_en override(bit5) & - * override value = 1(bit4), with mask - */ - ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL); - - if (!IS_ERR(host->rst)) - reset_control_deassert(host->rst); -} - -static int ufs_hi3660_link_startup_pre_change(struct ufs_hba *hba) -{ - int err; - uint32_t value; - uint32_t reg; - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - - /* Unipro VS_mphy_disable */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); - if (host->caps & USE_RATE_B) { - /* PA_HSSeries */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); - /* MPHY CBRATESEL */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); - /* MPHY CBOVRCTRL2 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); - /* MPHY CBOVRCTRL3 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); - /* Unipro VS_MphyCfgUpdt */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - /* MPHY RXOVRCTRL4 rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58); - /* MPHY RXOVRCTRL4 rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58); - /* MPHY RXOVRCTRL5 rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB); - /* MPHY RXOVRCTRL5 rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB); - /* MPHY RXSQCONTROL rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); - /* MPHY RXSQCONTROL rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1); - /* Unipro VS_MphyCfgUpdt */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - } else { - /* PA_HSSeries */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x1); - /* MPHY CBRATESEL */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x0); - /* MPHY CBOVRCTRL2 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x4C); - /* MPHY CBOVRCTRL3 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); - /* Unipro VS_MphyCfgUpdt */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - /* MPHY RXOVRCTRL4 rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x18); - /* MPHY RXOVRCTRL4 rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x18); - /* MPHY RXOVRCTRL5 rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xD); - /* MPHY RXOVRCTRL5 rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xD); - /* MPHY RXSQCONTROL rx0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); - /* MPHY RXSQCONTROL rx1 */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1); - /* Unipro VS_MphyCfgUpdt */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - } - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - /* Gear3 Synclength */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4A); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4A); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4A); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4A); - /* Tactive RX */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7); - /* Thibernate Tx */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); - /* Unipro VS_mphy_disable */ - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value); - if (value != 0x1) - dev_info(hba->dev, - "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value); - - /* Unipro VS_mphy_disable */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0); - err = ufs_hi3660_check_hibern8(hba); - if (err) - dev_err(hba->dev, "ufs_hi3660_check_hibern8 error\n"); - - ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); - - /* disable auto H8 */ - reg = ufshcd_readl(hba, REG_CONTROLLER_AHIT); - reg = reg & (~UFS_AHIT_AH8ITV_MASK); - ufshcd_writel(hba, reg, REG_CONTROLLER_AHIT); - - /* Unipro PA_Local_TX_LCC_Enable */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0); - /* close Unipro VS_Mk2ExtnSupport */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0); - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value); - if (0 != value) { - /* Ensure close success */ - dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n"); - } - - return err; -} - -static int ufs_hi3660_link_startup_post_change(struct ufs_hba *hba) -{ - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - - /* Unipro DL_AFC0CreditThreshold */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); - /* Unipro DL_TC0OutAckThreshold */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); - /* Unipro DL_TC0TXFCThreshold */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); - - if (host->caps & BROKEN_CLK_GATE_BYPASS) { - /* not bypass ufs clk gate */ - ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS, CLOCK_GATE_BYPASS); - ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); - } - - if (host->caps & USE_AUTO_H8) { - /* disable power-gating in auto hibernate 8 */ - ufshcd_rmwl(hba, LP_AH8_PGE, 0, UFS_REG_OCPTHRTL); - - /* enable auto H8 */ - ufshcd_writel(hba, UFS_AHIT_AUTOH8_TIMER, REG_CONTROLLER_AHIT); - } - - return 0; -} - -static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba, - enum ufs_notify_change_status status) -{ - int err = 0; - - switch (status) { - case PRE_CHANGE: - err = ufs_hi3660_link_startup_pre_change(hba); - break; - case POST_CHANGE: - err = ufs_hi3660_link_startup_post_change(hba); - break; - default: - break; - } - - return err; -} - -struct ufs_hi3660_dev_params { - u32 pwm_rx_gear; /* pwm rx gear to work in */ - u32 pwm_tx_gear; /* pwm tx gear to work in */ - u32 hs_rx_gear; /* hs rx gear to work in */ - u32 hs_tx_gear; /* hs tx gear to work in */ - u32 rx_lanes; /* number of rx lanes */ - u32 tx_lanes; /* number of tx lanes */ - u32 rx_pwr_pwm; /* rx pwm working pwr */ - u32 tx_pwr_pwm; /* tx pwm working pwr */ - u32 rx_pwr_hs; /* rx hs working pwr */ - u32 tx_pwr_hs; /* tx hs working pwr */ - u32 hs_rate; /* rate A/B to work in HS */ - u32 desired_working_mode; -}; - -static int ufs_hi3660_get_pwr_dev_param(struct ufs_hi3660_dev_params *hi3660_param, - struct ufs_pa_layer_attr *dev_max, - struct ufs_pa_layer_attr *agreed_pwr) -{ - int min_hi3660_gear; - int min_dev_gear; - bool is_dev_sup_hs = false; - bool is_hi3660_max_hs = false; - - if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE) - is_dev_sup_hs = true; - - if (hi3660_param->desired_working_mode == FAST) { - is_hi3660_max_hs = true; - min_hi3660_gear = min_t(u32, hi3660_param->hs_rx_gear, - hi3660_param->hs_tx_gear); - } else { - min_hi3660_gear = min_t(u32, hi3660_param->pwm_rx_gear, - hi3660_param->pwm_tx_gear); - } - - /* - * device doesn't support HS but - * hi3660_param->desired_working_mode is HS, - * thus device and hi3660_param don't agree - */ - if (!is_dev_sup_hs && is_hi3660_max_hs) { - pr_err("%s: device not support HS\n", __func__); - return -ENOTSUPP; - } else if (is_dev_sup_hs && is_hi3660_max_hs) { - /* - * since device supports HS, it supports FAST_MODE. - * since hi3660_param->desired_working_mode is also HS - * then final decision (FAST/FASTAUTO) is done according - * to hi3660_params as it is the restricting factor - */ - agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = - hi3660_param->rx_pwr_hs; - } else { - /* - * here hi3660_param->desired_working_mode is PWM. - * it doesn't matter whether device supports HS or PWM, - * in both cases hi3660_param->desired_working_mode will - * determine the mode - */ - agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = - hi3660_param->rx_pwr_pwm; - } - - /* - * we would like tx to work in the minimum number of lanes - * between device capability and vendor preferences. - * the same decision will be made for rx - */ - agreed_pwr->lane_tx = - min_t(u32, dev_max->lane_tx, hi3660_param->tx_lanes); - agreed_pwr->lane_rx = - min_t(u32, dev_max->lane_rx, hi3660_param->rx_lanes); - - /* device maximum gear is the minimum between device rx and tx gears */ - min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx); - - /* - * if both device capabilities and vendor pre-defined preferences are - * both HS or both PWM then set the minimum gear to be the chosen - * working gear. - * if one is PWM and one is HS then the one that is PWM get to decide - * what is the gear, as it is the one that also decided previously what - * pwr the device will be configured to. - */ - if ((is_dev_sup_hs && is_hi3660_max_hs) || - (!is_dev_sup_hs && !is_hi3660_max_hs)) - agreed_pwr->gear_rx = agreed_pwr->gear_tx = - min_t(u32, min_dev_gear, min_hi3660_gear); - else - agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hi3660_gear; - - agreed_pwr->hs_rate = hi3660_param->hs_rate; - - pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, " - "rate = %d\n", - agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx, - agreed_pwr->hs_rate); - return 0; -} - -static void ufs_hi3660_pwr_change_pre_change(struct ufs_hba *hba) -{ - /* update */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1); - /* PA_TxSkip */ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0); - /*PA_PWRModeUserData0 = 8191, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191); - /*PA_PWRModeUserData1 = 65535, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535); - /*PA_PWRModeUserData2 = 32767, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767); - /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191); - /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535); - /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767); - /*PA_PWRModeUserData3 = 8191, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191); - /*PA_PWRModeUserData4 = 65535, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535); - /*PA_PWRModeUserData5 = 32767, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767); - /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191); - /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535); - /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/ - ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767); -} - -static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba, - enum ufs_notify_change_status status, - struct ufs_pa_layer_attr *dev_max_params, - struct ufs_pa_layer_attr *dev_req_params) -{ - struct ufs_hi3660_dev_params ufs_hi3660_cap; - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - int ret = 0; - uint32_t value; - - if (!dev_req_params) { - dev_err(hba->dev, - "%s: incoming dev_req_params is NULL\n", __func__); - ret = -EINVAL; - goto out; - } - - switch (status) { - case PRE_CHANGE: - if (host->caps & USE_ONE_LANE) { - ufs_hi3660_cap.tx_lanes = 1; - ufs_hi3660_cap.rx_lanes = 1; - } else { - ufs_hi3660_cap.tx_lanes = 2; - ufs_hi3660_cap.rx_lanes = 2; - } - - if (host->caps & USE_HS_GEAR3) { - ufs_hi3660_cap.hs_rx_gear = UFS_HS_G3; - ufs_hi3660_cap.hs_tx_gear = UFS_HS_G3; - ufs_hi3660_cap.desired_working_mode = FAST; - } else if (host->caps & USE_HS_GEAR2) { - ufs_hi3660_cap.hs_rx_gear = UFS_HS_G2; - ufs_hi3660_cap.hs_tx_gear = UFS_HS_G2; - ufs_hi3660_cap.desired_working_mode = FAST; - } else if (host->caps & USE_HS_GEAR1) { - ufs_hi3660_cap.hs_rx_gear = UFS_HS_G1; - ufs_hi3660_cap.hs_tx_gear = UFS_HS_G1; - ufs_hi3660_cap.desired_working_mode = FAST; - } else { - ufs_hi3660_cap.desired_working_mode = SLOW; - } - - ufs_hi3660_cap.pwm_rx_gear = UFS_HI3660_LIMIT_PWMGEAR_RX; - ufs_hi3660_cap.pwm_tx_gear = UFS_HI3660_LIMIT_PWMGEAR_TX; - ufs_hi3660_cap.rx_pwr_pwm = UFS_HI3660_LIMIT_RX_PWR_PWM; - ufs_hi3660_cap.tx_pwr_pwm = UFS_HI3660_LIMIT_TX_PWR_PWM; - /*hynix not support fastauto now*/ - if (host->caps & BROKEN_FASTAUTO) { - ufs_hi3660_cap.rx_pwr_hs = FAST_MODE; - ufs_hi3660_cap.tx_pwr_hs = FAST_MODE; - } else { - ufs_hi3660_cap.rx_pwr_hs = FASTAUTO_MODE; - ufs_hi3660_cap.tx_pwr_hs = FASTAUTO_MODE; - } - - if (host->caps & USE_RATE_B) - ufs_hi3660_cap.hs_rate = PA_HS_MODE_B; - else - ufs_hi3660_cap.hs_rate = PA_HS_MODE_A; - - ret = ufs_hi3660_get_pwr_dev_param( - &ufs_hi3660_cap, dev_max_params, dev_req_params); - if (ret) { - dev_err(hba->dev, - "%s: failed to determine capabilities\n", __func__); - goto out; - } - - dev_info(hba->dev, "set TX_EQUALIZER 3.5db\n"); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), 0x1); - if ((dev_req_params->lane_tx > 1) && (dev_req_params->lane_rx > 1)) - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0037, 0x1), 0x1); - - ufs_hi3660_pwr_change_pre_change(hba); - break; - case POST_CHANGE: - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x0037, 0x0), &value); - dev_info(hba->dev, "check TX_EQUALIZER DB value lane0 = 0x%x\n", value); - if ((dev_req_params->lane_tx > 1) && (dev_req_params->lane_rx > 1)) { - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x0037, 0x1), &value); - dev_info(hba->dev, "check TX_EQUALIZER DB value lane1 = 0x%x\n", value); - } - break; - default: - ret = -EINVAL; - break; - } -out: - return ret; -} - -static int ufs_hi3660_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) -{ - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - - if (ufshcd_is_runtime_pm(pm_op)) - return 0; - - if (host->in_suspend) { - WARN_ON(1); - return 0; - } - - ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); - udelay(10); - /* set ref_dig_clk override of PHY PCS to 0 */ - ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL); - - host->in_suspend = true; - - return 0; -} - -static int ufs_hi3660_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) -{ - struct ufs_hi3660_host *host = ufshcd_get_variant(hba); - - if (!host->in_suspend) - return 0; - - /* set ref_dig_clk override of PHY PCS to 1 */ - ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL); - udelay(10); - ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); - - host->in_suspend = false; - return 0; -} - -static int ufs_hi3660_get_resource(struct ufs_hi3660_host *host) -{ - struct resource *mem_res; - struct device *dev = host->hba->dev; - struct platform_device *pdev = to_platform_device(dev); - - /* get resource of ufs sys ctrl */ - mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res); - if (!host->ufs_sys_ctrl) { - dev_err(dev, "cannot ioremap for ufs sys ctrl register\n"); - return -ENOMEM; - } - - return 0; -} - -static void ufs_hi3660_set_pm_lvl(struct ufs_hba *hba) -{ - hba->rpm_lvl = UFS_PM_LVL_1; - hba->spm_lvl = UFS_PM_LVL_3; -} - -static void ufs_hi3660_populate_dt(struct device *dev, - struct ufs_hi3660_host *host) -{ - struct device_node *np = dev->of_node; - int ret; - - if (!np) { - dev_err(dev, "can not find device node\n"); - return; - } - - if (of_find_property(np, "ufs-hi3660-use-rate-B", NULL)) - host->caps |= USE_RATE_B; - - if (of_find_property(np, "ufs-hi3660-broken-fastauto", NULL)) - host->caps |= BROKEN_FASTAUTO; - - if (of_find_property(np, "ufs-hi3660-use-one-line", NULL)) - host->caps |= USE_ONE_LANE; - - if (of_find_property(np, "ufs-hi3660-use-HS-GEAR3", NULL)) - host->caps |= USE_HS_GEAR3; - - if (of_find_property(np, "ufs-hi3660-use-HS-GEAR2", NULL)) - host->caps |= USE_HS_GEAR2; - - if (of_find_property(np, "ufs-hi3660-use-HS-GEAR1", NULL)) - host->caps |= USE_HS_GEAR1; - - if (of_find_property(np, "ufs-hi3660-broken-clk-gate-bypass", NULL)) - host->caps |= BROKEN_CLK_GATE_BYPASS; - - host->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); - if (gpio_is_valid(host->reset_gpio)) { - ret = devm_gpio_request_one(dev, host->reset_gpio, - GPIOF_DIR_OUT, "hi3660_ufs_reset"); - if (ret < 0) - dev_err(dev, "could not acquire gpio (err=%d)\n", ret); - } -} - -/** - * ufs_hi3660_init - * @hba: host controller instance - */ -static int ufs_hi3660_init(struct ufs_hba *hba) -{ - int err; - struct device *dev = hba->dev; - struct ufs_hi3660_host *host; - - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); - if (!host) { - dev_err(dev, "%s: no memory for hi3660 ufs host\n", __func__); - return -ENOMEM; - } - - host->hba = hba; - ufshcd_set_variant(hba, host); - - host->rst = devm_reset_control_get(dev, "rst"); - host->assert = devm_reset_control_get(dev, "assert"); - - ufs_hi3660_set_pm_lvl(hba); - - ufs_hi3660_populate_dt(dev, host); - - err = ufs_hi3660_get_resource(host); - if (err) { - ufshcd_set_variant(hba, NULL); - return err; - } - - ufs_hi3660_clk_init(hba); - - ufs_hi3660_soc_init(hba); - - return 0; -} - -static struct ufs_hba_variant_ops ufs_hba_hi3660_vops = { - .name = "hi3660", - .init = ufs_hi3660_init, - .link_startup_notify = ufs_hi3660_link_startup_notify, - .pwr_change_notify = ufs_hi3660_pwr_change_notify, - .suspend = ufs_hi3660_suspend, - .resume = ufs_hi3660_resume, -}; - -static int ufs_hi3660_probe(struct platform_device *pdev) -{ - return ufshcd_pltfrm_init(pdev, &ufs_hba_hi3660_vops); -} - -static int ufs_hi3660_remove(struct platform_device *pdev) -{ - struct ufs_hba *hba = platform_get_drvdata(pdev); - - ufshcd_remove(hba); - return 0; -} - -static const struct of_device_id ufs_hi3660_of_match[] = { - { .compatible = "hisilicon,hi3660-ufs" }, - {}, -}; - -static const struct dev_pm_ops ufs_hi3660_pm_ops = { - .suspend = ufshcd_pltfrm_suspend, - .resume = ufshcd_pltfrm_resume, - .runtime_suspend = ufshcd_pltfrm_runtime_suspend, - .runtime_resume = ufshcd_pltfrm_runtime_resume, - .runtime_idle = ufshcd_pltfrm_runtime_idle, -}; - -static struct platform_driver ufs_hi3660_pltform = { - .probe = ufs_hi3660_probe, - .remove = ufs_hi3660_remove, - .shutdown = ufshcd_pltfrm_shutdown, - .driver = { - .name = "ufshcd-hi3660", - .pm = &ufs_hi3660_pm_ops, - .of_match_table = of_match_ptr(ufs_hi3660_of_match), - }, -}; -module_platform_driver(ufs_hi3660_pltform); - -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:ufshcd-hi3660"); -MODULE_DESCRIPTION("HiSilicon Hi3660 UFS Driver"); diff --git a/drivers/scsi/ufs/ufs-hi3660.h b/drivers/scsi/ufs/ufs-hi3660.h deleted file mode 100644 index 04775cd2dddf..000000000000 --- a/drivers/scsi/ufs/ufs-hi3660.h +++ /dev/null @@ -1,170 +0,0 @@ -/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef UFS_HI3660_H_ -#define UFS_HI3660_H_ - -#define HBRN8_POLL_TOUT_MS 1000 - -/* - * pericrg specific define - */ -#define PEREN5_OFFSET (0x050) -#define PERRSTEN3_OFFSET (0x084) -#define PERRSTDIS3_OFFSET (0x088) -#define PERRSTSTAT3_OFFSET (0x08C) -#define CLKDIV16_OFFSET (0x0E8) -#define CLKDIV17_OFFSET (0x0EC) -#define CLKDIV21_OFFSET (0x0FC) -#define UFS_ARESET UFS_BIT(7) -#define RST_UFS UFS_BIT(12) - -/* - * ufs sysctrl specific define - */ -#define PSW_POWER_CTRL (0x04) -#define PHY_ISO_EN (0x08) -#define HC_LP_CTRL (0x0C) -#define PHY_CLK_CTRL (0x10) -#define PSW_CLK_CTRL (0x14) -#define CLOCK_GATE_BYPASS (0x18) -#define RESET_CTRL_EN (0x1C) -#define PHY_RESET_STATUS (0x28) -#define UFS_SYSCTRL (0x5C) -#define UFS_DEVICE_RESET_CTRL (0x60) -#define UFS_APB_ADDR_MASK (0x64) - -#define BIT_UFS_PSW_ISO_CTRL (1 << 16) -#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) -#define BIT_UFS_REFCLK_ISO_EN (1 << 16) -#define BIT_UFS_PHY_ISO_CTRL (1 << 0) -#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) -#define BIT_SYSCTRL_LP_PWR_GATE (1 << 0) -#define BIT_SYSCTRL_PWR_READY (1 << 8) -#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) -#define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) -#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) -#define UFS_FREQ_CFG_CLK (0x39) -#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) -#define MASK_UFS_CLK_GATE_BYPASS (0x3F) -#define BIT_STATUS_LP_RESETCOMPLETE (1 << 0) -#define BIT_SYSCTRL_LP_RESET_N (1 << 0) -#define BIT_UFS_REFCLK_SRC_SEl (1 << 0) -#define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) -#define MASK_UFS_DEVICE_RESET (0x1 << 16) -#define BIT_UFS_DEVICE_RESET (0x1) - -/* - * M-TX Configuration Attributes for hi3660 - */ -#define MPHY_TX_FSM_STATE 0x41 -#define TX_FSM_DISABLED 0x0 -#define TX_FSM_HIBERN8 0x1 -#define TX_FSM_SLEEP 0x2 -#define TX_FSM_STALL 0x3 -#define TX_FSM_LS_BURST 0x4 -#define TX_FSM_HS_BURST 0x5 -#define TX_FSM_LINE_CFG 0x6 -#define TX_FSM_LINE_RESET 0x7 - -/* - * hi3660 UFS HC specific Registers - */ -enum { - UFS_REG_OCPTHRTL = 0xc0, - UFS_REG_OOCPR = 0xc4, - - UFS_REG_CDACFG = 0xd0, - UFS_REG_CDATX1 = 0xd4, - UFS_REG_CDATX2 = 0xd8, - UFS_REG_CDARX1 = 0xdc, - UFS_REG_CDARX2 = 0xe0, - UFS_REG_CDASTA = 0xe4, - - UFS_REG_LBMCFG = 0xf0, - UFS_REG_LBMSTA = 0xf4, - UFS_REG_UFSMODE = 0xf8, - - UFS_REG_HCLKDIV = 0xfc, -}; - -#define UFS_AHIT_AUTOH8_TIMER (0x1001) - -/* REG UFS_REG_OCPTHRTL definition */ -#define LP_PGE UFS_BIT(16) -#define LP_AH8_PGE UFS_BIT(17) - -#define UFS_HCLKDIV_NORMAL_VALUE 0xE4 -#define UFS_HCLKDIV_FPGA_VALUE 0x28 - -/* hi3660 UFS Unipro specific Registers */ -#define VS_ULPH8_Cntrl 0xd0af -#define Ulp_Ulp_CtrlMode UFS_BIT(3) - -/* vendor specific pre-defined parameters */ -#define SLOW 1 -#define FAST 2 - -#define UFS_HI3660_LIMIT_NUM_LANES_RX 2 -#define UFS_HI3660_LIMIT_NUM_LANES_TX 2 -#define UFS_HI3660_LIMIT_HSGEAR_RX UFS_HS_G1 -#define UFS_HI3660_LIMIT_HSGEAR_TX UFS_HS_G1 -#define UFS_HI3660_LIMIT_PWMGEAR_RX UFS_PWM_G1 -#define UFS_HI3660_LIMIT_PWMGEAR_TX UFS_PWM_G1 -#define UFS_HI3660_LIMIT_RX_PWR_PWM SLOWAUTO_MODE -#define UFS_HI3660_LIMIT_TX_PWR_PWM SLOWAUTO_MODE -#define UFS_HI3660_LIMIT_RX_PWR_HS FASTAUTO_MODE -#define UFS_HI3660_LIMIT_TX_PWR_HS FASTAUTO_MODE -#define UFS_HI3660_LIMIT_HS_RATE PA_HS_MODE_A -#define UFS_HI3660_LIMIT_DESIRED_MODE FAST - -struct ufs_hi3660_host { - struct ufs_hba *hba; - void __iomem *ufs_sys_ctrl; - struct reset_control *rst; - struct reset_control *assert; - uint64_t caps; -#define hi3660_CAP_RESERVED UFS_BIT(0) -#define USE_SNPS_MPHY_TC UFS_BIT(1) -#define USE_FPGA_BOARD_CLK UFS_BIT(2) -#define USE_RATE_B UFS_BIT(3) -#define BROKEN_FASTAUTO UFS_BIT(4) -#define USE_ONE_LANE UFS_BIT(5) -#define USE_HS_GEAR3 UFS_BIT(6) -#define USE_HS_GEAR2 UFS_BIT(7) -#define USE_HS_GEAR1 UFS_BIT(8) -#define USE_AUTO_H8 UFS_BIT(9) -#define BROKEN_CLK_GATE_BYPASS UFS_BIT(10) - - int avail_ln_rx; - int avail_ln_tx; - - u32 busthrtl_backup; - u32 reset_gpio; - - bool in_suspend; - - struct ufs_pa_layer_attr dev_req_params; -}; - -#define ufs_sys_ctrl_writel(host, val, reg) \ - writel((val), (host)->ufs_sys_ctrl + (reg)) -#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) -#define ufs_sys_ctrl_set_bits(host, mask, reg) \ - ufs_sys_ctrl_writel( \ - (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) -#define ufs_sys_ctrl_clr_bits(host, mask, reg) \ - ufs_sys_ctrl_writel((host), \ - ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ - (reg)) -#endif /* UFS_HI3660_H_ */ diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c new file mode 100644 index 000000000000..b6ee15092f2b --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.c @@ -0,0 +1,784 @@ +/* + * + * HiSilicon Hixxxx UFS Driver + * + * Copyright (c) 2016-2017 Linaro Ltd. + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#include "ufshcd.h" +#include "ufshcd-pltfrm.h" +#include "unipro.h" +#include "ufs-hisi.h" +#include "ufshci.h" +#include "ufs_quirks.h" + +static int ufs_hisi_check_hibern8(struct ufs_hba *hba) +{ + int err = 0; + u32 tx_fsm_val_0 = 0; + u32 tx_fsm_val_1 = 0; + unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); + + do { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 && + tx_fsm_val_1 == TX_FSM_HIBERN8)) + break; + + /* sleep for max. 200us */ + usleep_range(100, 200); + } while (time_before(jiffies, timeout)); + + /* + * we might have scheduled out for long during polling so + * check the state again. + */ + if (time_after(jiffies, timeout)) { + err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), + &tx_fsm_val_0); + err |= ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); + } + + if (err) { + dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", + __func__, err); + } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 || + tx_fsm_val_1 != TX_FSM_HIBERN8) { + err = -1; + dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", + __func__, tx_fsm_val_0, tx_fsm_val_1); + } + + return err; +} + +static void ufs_hisi_clk_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN) + mdelay(1); + /* use abb clk */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL); + ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN); + /* open mphy ref clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); +} + +static void ufs_hisi_soc_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + u32 reg; + + if (!IS_ERR(host->rst)) + reset_control_assert(host->rst); + + /* HC_PSW powerup */ + ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL); + udelay(10); + /* notify PWR ready */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL); + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0, + UFS_DEVICE_RESET_CTRL); + + reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); + reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK; + /* set cfg clk freq */ + ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); + /* set ref clk freq */ + ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL); + /* bypass ufs clk gate */ + ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); + + /* open psw clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL); + /* disable ufshc iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL); + /* disable phy iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN); + /* notice iso disable */ + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL); + + if (!IS_ERR(host->assert)) + reset_control_deassert(host->assert); + + /* disable lp_reset_n */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN); + mdelay(1); + + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET, + UFS_DEVICE_RESET_CTRL); + + mdelay(20); + + /* + * enable the fix of linereset recovery, + * and enable rx_reset/tx_rest beat + * enable ref_clk_en override(bit5) & + * override value = 1(bit4), with mask + */ + ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL); + + if (!IS_ERR(host->rst)) + reset_control_deassert(host->rst); +} + +static void ufs_hisi_v21_soc_init(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + u32 reg; + + /*CS LOW TEMP 207M*/ + ufs_sctrl_writel(host, BIT_UFS_SUBSYS_GT_CLK, SCTRL_SCPERDIS4); + ufs_sctrl_writel(host, 0x003F0007, SCTRL_SCCLKDIV9); + ufs_sctrl_writel(host, BIT_UFS_SUBSYS_GT_CLK, SCTRL_SCPEREN4); + + ufs_sys_ctrl_writel(host, BIT_IES_EN_MASK, UFS_UMECTRL); + ufs_sys_ctrl_writel(host, BIT_CLK_DIV, CRG_UFS_CFG); + + /* efuse indicates enable rhold or not */ + if (ufs_sctrl_readl(host, SCDEEPSLEEPED_OFFSET) & BIT_EFUSE_RHOLD) + ufs_sctrl_writel(host, (MASK_UFS_MPHY_RHOLD | BIT_UFS_MPHY_RHOLD), + UFS_DEVICE_RESET_CTRL); + + /* HC_PSW powerup */ + ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL); + udelay(10); + /* notify PWR ready */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL); + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + /*Bit[4:2], div =4*/ + reg = ((0x3 << 2) | (0x7 << (2 + 16))); + ufs_sys_ctrl_writel(host, reg, CRG_UFS_CFG); + reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); + reg = reg & (~MASK_SYSCTRL_CFG_CLOCK_FREQ); + /* BUS 207M / 4 = 0x34 syscfg clk */ + reg = reg | 0x34; + /* set cfg clk freq */ + ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); + /* set ref clk freq */ + ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL); + + /* enable ref_clk_en override(bit5) & override value = 1(bit4), with mask */ + ufs_sys_ctrl_writel(host, 0x00300030, UFS_DEVICE_RESET_CTRL); + + /* bypass ufs clk gate */ + ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS, CLOCK_GATE_BYPASS); + ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL); + + /* open psw clk */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL); + /* disable ufshc iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL); + /*phy iso only effective on Miami,double check for kirin980 and later plat*/ + /* disable phy iso */ + ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN); + /* notice iso disable */ + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL); + + ufs_sys_ctrl_writel(host, 1 << 17 | 2, CRG_UFS_CFG); + + /* disable lp_reset_n */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN); + mdelay(1); + + /* open clock of M-PHY */ + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, + PHY_CLK_CTRL); + + /* reset device */ + ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0, + UFS_DEVICE_RESET_CTRL); + + ufs_sctrl_readl(host, CTRL_SCDEEPSLEEPED); + if (0 == (reg & (1 << 21))) { + mdelay(1); + /* disable Device Reset */ + ufs_sys_ctrl_writel( + host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET, + UFS_DEVICE_RESET_CTRL); + } + mdelay(40); + + ufs_sys_ctrl_writel(host, BIT_CLK_DIV | 1, CRG_UFS_CFG); + + return; +} + +static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + int err; + uint32_t value; + uint32_t reg; + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); + /* PA_HSSeries */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); + /* MPHY CBRATESEL */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); + /* MPHY CBOVRCTRL2 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); + /* MPHY CBOVRCTRL3 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); + + if (host->caps & HISI_CAP_UFS_PHY10nm) { + /* MPHY CBOVRCTRL4 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98); + /* MPHY CBOVRCTRL5 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1); + } + + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* MPHY RXOVRCTRL4 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58); + /* MPHY RXOVRCTRL4 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58); + /* MPHY RXOVRCTRL5 rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB); + /* MPHY RXOVRCTRL5 rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB); + /* MPHY RXSQCONTROL rx0 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1); + /* MPHY RXSQCONTROL rx1 */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1); + /* Unipro VS_MphyCfgUpdt */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + + if (host->caps & HISI_CAP_UFS_PHY10nm) { + /* RX_Hibern8Time_Capability*/ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA); + /* RX_Hibern8Time_Capability*/ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA); + /* RX_Min_ActivateTime */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA); + /* RX_Min_ActivateTime*/ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA); + } else { + /* Tactive RX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7); + /* Tactive RX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7); + } + /* Gear3 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F); + /* Gear3 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F); + /* Gear2 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F); + /* Gear2 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F); + /* Gear1 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F); + /* Gear1 Synclength */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F); + /* Thibernate Tx */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5); + /* Thibernate Tx */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); + /* Unipro VS_mphy_disable */ + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value); + if (value != 0x1) + dev_info(hba->dev, + "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value); + + /* Unipro VS_mphy_disable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0); + err = ufs_hisi_check_hibern8(hba); + if (err) + dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n"); + + if (!(host->caps & HISI_CAP_UFS_PHY10nm)) + ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); + + /* disable auto H8 */ + reg = ufshcd_readl(hba, REG_CONTROLLER_AHIT); + reg = reg & (~UFS_AHIT_AH8ITV_MASK); + ufshcd_writel(hba, reg, REG_CONTROLLER_AHIT); + + /* Unipro PA_Local_TX_LCC_Enable */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0); + /* close Unipro VS_Mk2ExtnSupport */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0); + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value); + if (value != 0) { + /* Ensure close success */ + dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n"); + } + + return err; +} + +static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + /* Unipro DL_AFC0CreditThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); + /* Unipro DL_TC0OutAckThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); + /* Unipro DL_TC0TXFCThreshold */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); + + /* not bypass ufs clk gate */ + ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS, + CLOCK_GATE_BYPASS); + ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS, + UFS_SYSCTRL); + + /* select received symbol cnt */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000); + /* reset counter0 and enable */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005); + + return 0; +} + +static int ufs_hisi_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + switch (status) { + case PRE_CHANGE: + err = ufs_hisi_link_startup_pre_change(hba); + break; + case POST_CHANGE: + err = ufs_hisi_link_startup_post_change(hba); + break; + default: + break; + } + + return err; +} + +struct ufs_hisi_dev_params { + u32 pwm_rx_gear; /* pwm rx gear to work in */ + u32 pwm_tx_gear; /* pwm tx gear to work in */ + u32 hs_rx_gear; /* hs rx gear to work in */ + u32 hs_tx_gear; /* hs tx gear to work in */ + u32 rx_lanes; /* number of rx lanes */ + u32 tx_lanes; /* number of tx lanes */ + u32 rx_pwr_pwm; /* rx pwm working pwr */ + u32 tx_pwr_pwm; /* tx pwm working pwr */ + u32 rx_pwr_hs; /* rx hs working pwr */ + u32 tx_pwr_hs; /* tx hs working pwr */ + u32 hs_rate; /* rate A/B to work in HS */ + u32 desired_working_mode; +}; + +static int ufs_hisi_get_pwr_dev_param( + struct ufs_hisi_dev_params *hisi_param, + struct ufs_pa_layer_attr *dev_max, + struct ufs_pa_layer_attr *agreed_pwr) +{ + int min_hisi_gear; + int min_dev_gear; + bool is_dev_sup_hs = false; + bool is_hisi_max_hs = false; + + if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE) + is_dev_sup_hs = true; + + if (hisi_param->desired_working_mode == FAST) { + is_hisi_max_hs = true; + min_hisi_gear = min_t(u32, hisi_param->hs_rx_gear, + hisi_param->hs_tx_gear); + } else { + min_hisi_gear = min_t(u32, hisi_param->pwm_rx_gear, + hisi_param->pwm_tx_gear); + } + + /* + * device doesn't support HS but + * hisi_param->desired_working_mode is HS, + * thus device and hisi_param don't agree + */ + if (!is_dev_sup_hs && is_hisi_max_hs) { + pr_err("%s: device not support HS\n", __func__); + return -ENOTSUPP; + } else if (is_dev_sup_hs && is_hisi_max_hs) { + /* + * since device supports HS, it supports FAST_MODE. + * since hisi_param->desired_working_mode is also HS + * then final decision (FAST/FASTAUTO) is done according + * to hisi_params as it is the restricting factor + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_hs; + } else { + /* + * here hisi_param->desired_working_mode is PWM. + * it doesn't matter whether device supports HS or PWM, + * in both cases hisi_param->desired_working_mode will + * determine the mode + */ + agreed_pwr->pwr_rx = agreed_pwr->pwr_tx = + hisi_param->rx_pwr_pwm; + } + + /* + * we would like tx to work in the minimum number of lanes + * between device capability and vendor preferences. + * the same decision will be made for rx + */ + agreed_pwr->lane_tx = + min_t(u32, dev_max->lane_tx, hisi_param->tx_lanes); + agreed_pwr->lane_rx = + min_t(u32, dev_max->lane_rx, hisi_param->rx_lanes); + + /* device maximum gear is the minimum between device rx and tx gears */ + min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx); + + /* + * if both device capabilities and vendor pre-defined preferences are + * both HS or both PWM then set the minimum gear to be the chosen + * working gear. + * if one is PWM and one is HS then the one that is PWM get to decide + * what is the gear, as it is the one that also decided previously what + * pwr the device will be configured to. + */ + if ((is_dev_sup_hs && is_hisi_max_hs) || + (!is_dev_sup_hs && !is_hisi_max_hs)) + agreed_pwr->gear_rx = agreed_pwr->gear_tx = + min_t(u32, min_dev_gear, min_hisi_gear); + else + agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hisi_gear; + + agreed_pwr->hs_rate = hisi_param->hs_rate; + + pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, rate = %d\n", + agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx, + agreed_pwr->hs_rate); + return 0; +} + +static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + uint32_t value; + + if (host->caps & HISI_CAP_UFS_PHY10nm) { + /*Boston platform need to set SaveConfigTime to 0x13, + *and change sync length to maximum value + */ + /* VS_DebugSaveConfigTime */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13); + /* g1 sync length */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f); + /* g2 sync length */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f); + /* g3 sync length */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f); + /* PA_Hibern8Time */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA); + /* PA_Tactivate */ + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01); + } + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) { + pr_info("H**** device must set VS_DebugSaveConfigTime 0x10\n"); + /* VS_DebugSaveConfigTime */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10); + /* sync length */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48); + } + + ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8), &value); + if (value < 0x7) + /* update PaTactive */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x7); + + /* PA_TxSkip */ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0); + /*PA_PWRModeUserData0 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191); + /*PA_PWRModeUserData1 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535); + /*PA_PWRModeUserData2 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767); + /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191); + /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535); + /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767); + /*PA_PWRModeUserData3 = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191); + /*PA_PWRModeUserData4 = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535); + /*PA_PWRModeUserData5 = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767); + /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191); + /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535); + /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/ + ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767); +} + +static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status, + struct ufs_pa_layer_attr *dev_max_params, + struct ufs_pa_layer_attr *dev_req_params) +{ + struct ufs_hisi_dev_params ufs_hisi_cap; + int ret = 0; + + if (!dev_req_params) { + dev_err(hba->dev, + "%s: incoming dev_req_params is NULL\n", __func__); + ret = -EINVAL; + goto out; + } + + switch (status) { + case PRE_CHANGE: + ufs_hisi_cap.rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX; + ufs_hisi_cap.tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX; + ufs_hisi_cap.hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX; + ufs_hisi_cap.hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX; + ufs_hisi_cap.pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX; + ufs_hisi_cap.pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX; + ufs_hisi_cap.rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM; + ufs_hisi_cap.tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM; + ufs_hisi_cap.rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS; + ufs_hisi_cap.tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS; + ufs_hisi_cap.hs_rate = UFS_HISI_LIMIT_HS_RATE; + ufs_hisi_cap.desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE; + + ret = ufs_hisi_get_pwr_dev_param( + &ufs_hisi_cap, dev_max_params, dev_req_params); + if (ret) { + dev_err(hba->dev, + "%s: failed to determine capabilities\n", __func__); + goto out; + } + + ufs_hisi_pwr_change_pre_change(hba); + break; + case POST_CHANGE: + break; + default: + ret = -EINVAL; + break; + } +out: + return ret; +} + +static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (ufshcd_is_runtime_pm(pm_op)) + return 0; + + if (host->in_suspend) { + WARN_ON(1); + return 0; + } + + ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + udelay(10); + /* set ref_dig_clk override of PHY PCS to 0 */ + ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL); + + host->in_suspend = true; + + return 0; +} + +static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) +{ + struct ufs_hisi_host *host = ufshcd_get_variant(hba); + + if (!host->in_suspend) + return 0; + + /* set ref_dig_clk override of PHY PCS to 1 */ + ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL); + udelay(10); + ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL); + + host->in_suspend = false; + return 0; +} + +static int ufs_hisi_get_resource(struct ufs_hisi_host *host) +{ + struct resource *mem_res; + struct device_node *np = NULL; + struct device *dev = host->hba->dev; + struct platform_device *pdev = to_platform_device(dev); + + /* get resource of ufs sys ctrl */ + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res); + if (IS_ERR(host->ufs_sys_ctrl)) + return PTR_ERR(host->ufs_sys_ctrl); + + if (host->caps & HISI_CAP_UFS_PHY10nm) { + np = of_find_compatible_node(NULL, NULL, "hisilicon,kirin970-sctrl"); + if (!np) { + dev_err(host->hba->dev, + "can't find device node \"hisilicon,kirin970-sctrl\"\n"); + return -ENODEV; + } + + host->sysctrl = of_iomap(np, 0); + if (IS_ERR(host->sysctrl)) { + dev_err(host->hba->dev, "sysctrl iomap error!\n"); + return PTR_ERR(host->sysctrl); + } + } + + return 0; +} + +static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba) +{ + hba->rpm_lvl = UFS_PM_LVL_1; + hba->spm_lvl = UFS_PM_LVL_3; +} + +static void ufs_hisi_populate_dt(struct device *dev, + struct ufs_hisi_host *host) +{ + struct device_node *np = dev->of_node; + + if (!np) { + dev_err(dev, "can not find device node\n"); + return; + } + + if (of_find_property(np, "ufs-kirin-phy10nm-support", NULL)) + host->caps |= HISI_CAP_UFS_PHY10nm; + + return; + +} + +/** + * ufs_hisi_init + * @hba: host controller instance + */ +static int ufs_hisi_init(struct ufs_hba *hba) +{ + int err = 0; + struct device *dev = hba->dev; + struct ufs_hisi_host *host; + + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) { + dev_err(dev, "%s: no memory for hisi ufs host\n", __func__); + return -ENOMEM; + } + + host->hba = hba; + ufshcd_set_variant(hba, host); + + host->rst = devm_reset_control_get(dev, "rst"); + host->assert = devm_reset_control_get(dev, "assert"); + + ufs_hisi_set_pm_lvl(hba); + + ufs_hisi_populate_dt(dev, host); + + err = ufs_hisi_get_resource(host); + if (err) { + ufshcd_set_variant(hba, NULL); + return err; + } + + if (host->caps & HISI_CAP_UFS_PHY10nm) { + ufs_hisi_v21_soc_init(hba); + } else { + ufs_hisi_clk_init(hba); + ufs_hisi_soc_init(hba); + } + + return 0; +} + +static struct ufs_hba_variant_ops ufs_hba_hisi_vops = { + .name = "hisi", + .init = ufs_hisi_init, + .link_startup_notify = ufs_hisi_link_startup_notify, + .pwr_change_notify = ufs_hisi_pwr_change_notify, + .suspend = ufs_hisi_suspend, + .resume = ufs_hisi_resume, +}; + +static int ufs_hisi_probe(struct platform_device *pdev) +{ + return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops); +} + +static int ufs_hisi_remove(struct platform_device *pdev) +{ + struct ufs_hba *hba = platform_get_drvdata(pdev); + + ufshcd_remove(hba); + return 0; +} + +static const struct of_device_id ufs_hisi_of_match[] = { + { .compatible = "hisilicon,hi3660-ufs" }, + { .compatible = "hisilicon,kirin970-ufs" }, + {}, +}; + +static const struct dev_pm_ops ufs_hisi_pm_ops = { + .suspend = ufshcd_pltfrm_suspend, + .resume = ufshcd_pltfrm_resume, + .runtime_suspend = ufshcd_pltfrm_runtime_suspend, + .runtime_resume = ufshcd_pltfrm_runtime_resume, + .runtime_idle = ufshcd_pltfrm_runtime_idle, +}; + +static struct platform_driver ufs_hisi_pltform = { + .probe = ufs_hisi_probe, + .remove = ufs_hisi_remove, + .shutdown = ufshcd_pltfrm_shutdown, + .driver = { + .name = "ufshcd-hisi", + .pm = &ufs_hisi_pm_ops, + .of_match_table = of_match_ptr(ufs_hisi_of_match), + }, +}; +module_platform_driver(ufs_hisi_pltform); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ufshcd-hisi"); +MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver"); diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h new file mode 100644 index 000000000000..4cd30205017f --- /dev/null +++ b/drivers/scsi/ufs/ufs-hisi.h @@ -0,0 +1,158 @@ +/* Copyright (c) 2017, HiSilicon. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef UFS_HISI_H_ +#define UFS_HISI_H_ + +#define HBRN8_POLL_TOUT_MS 1000 + +/* + * SOC specific define + */ +#define SCDEEPSLEEPED_OFFSET (0x008) +#define SCTRL_SCPERDIS4 (0x1B4) +#define SCTRL_SCCLKDIV9 (0x274) +#define SCTRL_SCPEREN4 (0x1B0) +#define CTRL_SCDEEPSLEEPED (0x008) + +#define BIT_UFS_SUBSYS_GT_CLK UFS_BIT(14) +#define BIT_EFUSE_RHOLD UFS_BIT(22) +#define MASK_UFS_MPHY_RHOLD (0x1 << (11 + 16)) +#define BIT_UFS_MPHY_RHOLD UFS_BIT(11) + +/* + * pericrg specific define + */ +#define PERRSTEN3_OFFSET (0x084) +#define PERRSTDIS3_OFFSET (0x088) + +#define UFS_ARESET UFS_BIT(7) +#define RST_UFS UFS_BIT(12) + +/* + * ufs sysctrl specific define + */ +#define PSW_POWER_CTRL (0x04) +#define PHY_ISO_EN (0x08) +#define HC_LP_CTRL (0x0C) +#define PHY_CLK_CTRL (0x10) +#define PSW_CLK_CTRL (0x14) +#define CLOCK_GATE_BYPASS (0x18) +#define RESET_CTRL_EN (0x1C) +#define UFS_SYSCTRL (0x5C) +#define UFS_DEVICE_RESET_CTRL (0x60) +#define UFS_UMECTRL (0x64) +#define CRG_UFS_CFG (0x7C) + +#define BIT_UFS_PSW_ISO_CTRL UFS_BIT(16) +#define BIT_UFS_PSW_MTCMOS_EN UFS_BIT(0) +#define BIT_UFS_REFCLK_ISO_EN UFS_BIT(16) +#define BIT_UFS_PHY_ISO_CTRL UFS_BIT(0) +#define BIT_SYSCTRL_LP_ISOL_EN UFS_BIT(16) +#define BIT_SYSCTRL_PWR_READY UFS_BIT(8) +#define BIT_SYSCTRL_REF_CLOCK_EN UFS_BIT(24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define UFS_FREQ_CFG_CLK (0x39) +#define BIT_SYSCTRL_PSW_CLK_EN UFS_BIT(4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_SYSCTRL_LP_RESET_N UFS_BIT(0) +#define BIT_UFS_REFCLK_SRC_SEl UFS_BIT(0) +#define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET UFS_BIT(16) +#define BIT_UFS_DEVICE_RESET UFS_BIT(0) +#define BIT_IES_EN_MASK UFS_BIT(0) +#define BIT_CLK_DIV UFS_BIT(16) + +/* + * M-TX Configuration Attributes for Hixxxx + */ +#define MPHY_TX_FSM_STATE 0x41 +#define TX_FSM_HIBERN8 0x1 + +/* + * Hixxxx UFS HC specific Registers + */ +enum { + UFS_REG_OCPTHRTL = 0xc0, + UFS_REG_OOCPR = 0xc4, + + UFS_REG_CDACFG = 0xd0, + UFS_REG_CDATX1 = 0xd4, + UFS_REG_CDATX2 = 0xd8, + UFS_REG_CDARX1 = 0xdc, + UFS_REG_CDARX2 = 0xe0, + UFS_REG_CDASTA = 0xe4, + + UFS_REG_LBMCFG = 0xf0, + UFS_REG_LBMSTA = 0xf4, + UFS_REG_UFSMODE = 0xf8, + + UFS_REG_HCLKDIV = 0xfc, +}; + +/* AHIT - Auto-Hibernate Idle Timer */ +#define UFS_AHIT_AH8ITV_MASK 0x3FF + +/* REG UFS_REG_OCPTHRTL definition */ +#define UFS_HCLKDIV_NORMAL_VALUE 0xE4 + +/* vendor specific pre-defined parameters */ +#define SLOW 1 +#define FAST 2 + +#define UFS_HISI_LIMIT_NUM_LANES_RX 2 +#define UFS_HISI_LIMIT_NUM_LANES_TX 2 +#define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3 +#define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3 +#define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G4 +#define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G4 +#define UFS_HISI_LIMIT_RX_PWR_PWM SLOW_MODE +#define UFS_HISI_LIMIT_TX_PWR_PWM SLOW_MODE +#define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE +#define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B +#define UFS_HISI_LIMIT_DESIRED_MODE FAST + +#define HISI_CAP_RESERVED UFS_BIT(0) +#define HISI_CAP_UFS_PHY10nm UFS_BIT(1) + +struct ufs_hisi_host { + struct ufs_hba *hba; + void __iomem *ufs_sys_ctrl; + void __iomem *sysctrl; + + struct reset_control *rst; + struct reset_control *assert; + + uint64_t caps; + + bool in_suspend; +}; + +#define ufs_sys_ctrl_writel(host, val, reg) \ + writel((val), (host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) +#define ufs_sys_ctrl_set_bits(host, mask, reg) \ + ufs_sys_ctrl_writel( \ + (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) +#define ufs_sys_ctrl_clr_bits(host, mask, reg) \ + ufs_sys_ctrl_writel((host), \ + ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ + (reg)) + +#define ufs_sctrl_writel(host, val, reg) \ + writel((val), (host)->sysctrl + (reg)) +#define ufs_sctrl_readl(host, reg) readl((host)->sysctrl + (reg)) + +#endif /* UFS_HISI_H_ */ diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h index 08b799d4efcc..414782b3644e 100644 --- a/drivers/scsi/ufs/ufs_quirks.h +++ b/drivers/scsi/ufs/ufs_quirks.h @@ -144,6 +144,12 @@ struct ufs_dev_fix { */ #define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8) +/* + * Some UFS devices require VS_DebugSaveConfigTime is 0x10, + * enabling this quirk ensure this. + */ +#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9) + struct ufs_hba; void ufs_advertise_fixup_device(struct ufs_hba *hba); diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index fe893f23d693..26f36e7d1971 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -210,6 +210,8 @@ static struct ufs_dev_fix ufs_fixups[] = { UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ), UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME), + UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, + UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME), END_FIX }; @@ -1343,10 +1345,11 @@ static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) u32 upiu_flags; int ret = 0; - if (hba->ufs_version == UFSHCI_VERSION_20) - lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; - else + if ((hba->ufs_version == UFSHCI_VERSION_10) || + (hba->ufs_version == UFSHCI_VERSION_11)) lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; + else + lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) @@ -1370,10 +1373,11 @@ static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) u32 upiu_flags; int ret = 0; - if (hba->ufs_version == UFSHCI_VERSION_20) - lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; - else + if ((hba->ufs_version == UFSHCI_VERSION_10) || + (hba->ufs_version == UFSHCI_VERSION_11)) lrbp->command_type = UTP_CMD_TYPE_SCSI; + else + lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; if (likely(lrbp->cmd)) { ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,