Yao Chen
09fd0174c5
This patch fixes MSI interrupts missing problem. Signed-off-by: Yao Chen <chenyao11@huawei.com>
426 lines
9.2 KiB
C
426 lines
9.2 KiB
C
/*
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* PCIe host controller driver for Kirin Phone SoCs
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*
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* Copyright (C) 2015 Hilisicon Electronics Co., Ltd.
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* http://www.huawei.com
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*
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* Author: Xiaowei Song <songxiaowei@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "pcie-kirin.h"
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struct kirin_pcie *g_kirin_pcie;
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static void kirin_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
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{
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u32 val;
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struct kirin_pcie *pcie = to_kirin_pcie(pp);
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val = kirin_elb_readl(pcie, SOC_PCIECTRL_CTRL0_ADDR);
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if (on)
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val = val | PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
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kirin_elb_writel(pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
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}
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static void kirin_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
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{
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u32 val;
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struct kirin_pcie *pcie = to_kirin_pcie(pp);
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val = kirin_elb_readl(pcie, SOC_PCIECTRL_CTRL1_ADDR);
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if (on)
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val = val | PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
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kirin_elb_writel(pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
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}
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static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
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int where, int size, u32 *val)
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{
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kirin_pcie_sideband_dbi_r_mode(pp, true);
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*val = readl(pp->dbi_base + (where & ~0x3));
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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else if (size != 4)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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kirin_pcie_sideband_dbi_r_mode(pp, false);
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return PCIBIOS_SUCCESSFUL;
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}
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static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
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int where, int size, u32 val)
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{
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int ret;
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kirin_pcie_sideband_dbi_w_mode(pp, true);
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if (size == 4)
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writel(val, pp->dbi_base + (where & ~0x3));
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else if (size == 2)
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writew(val, pp->dbi_base + (where & ~0x3) + (where & 2));
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else if (size == 1)
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writeb(val, pp->dbi_base + (where & ~0x3) + (where & 3));
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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kirin_pcie_sideband_dbi_w_mode(pp, false);
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return ret;
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}
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static u32 kirin_pcie_readl_rc(struct pcie_port *pp, u32 reg)
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{
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u32 val;
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kirin_pcie_sideband_dbi_r_mode(pp, true);
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val = readl(pp->dbi_base + reg);
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kirin_pcie_sideband_dbi_r_mode(pp, false);
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return val;
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}
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static void kirin_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
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{
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kirin_pcie_sideband_dbi_w_mode(pp, true);
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writel(val, pp->dbi_base + reg);
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kirin_pcie_sideband_dbi_w_mode(pp, false);
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}
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static int kirin_pcie_link_up(struct pcie_port *pp)
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{
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struct kirin_pcie *pcie = to_kirin_pcie(pp);
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u32 val = kirin_elb_readl(pcie, SOC_PCIECTRL_STATE0_ADDR);
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if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
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return 1;
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return 0;
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}
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static int kirin_pcie_establish_link(struct pcie_port *pp)
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{
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int count = 0;
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struct kirin_pcie *pcie = to_kirin_pcie(pp);
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if (kirin_pcie_link_up(pp))
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return 0;
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dw_pcie_setup_rc(pp);
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/* assert LTSSM enable */
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kirin_elb_writel(pcie, PCIE_LTSSM_ENABLE_BIT,
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SOC_PCIECTRL_CTRL7_ADDR);
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/* check if the link is up or not */
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while (!kirin_pcie_link_up(pp)) {
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mdelay(1);
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count++;
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if (count == 1000) {
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dev_err(pp->dev, "Link Fail\n");
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return -EINVAL;
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}
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}
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return 0;
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}
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static irqreturn_t kirin_pcie_msi_irq_handler(int irq, void *arg)
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{
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struct pcie_port *pp = arg;
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return dw_handle_msi_irq(pp);
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}
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static void kirin_pcie_msi_init(struct pcie_port *pp)
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{
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dw_pcie_msi_init(pp);
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}
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static void kirin_pcie_enable_interrupts(struct pcie_port *pp)
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{
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if (IS_ENABLED(CONFIG_PCI_MSI))
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kirin_pcie_msi_init(pp);
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}
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static void kirin_pcie_host_init(struct pcie_port *pp)
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{
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if (kirin_pcie_establish_link(pp))
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return;
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kirin_pcie_enable_interrupts(pp);
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return;
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}
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static struct pcie_host_ops kirin_pcie_host_ops = {
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.readl_rc = kirin_pcie_readl_rc,
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.writel_rc = kirin_pcie_writel_rc,
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.rd_own_conf = kirin_pcie_rd_own_conf,
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.wr_own_conf = kirin_pcie_wr_own_conf,
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.link_up = kirin_pcie_link_up,
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.host_init = kirin_pcie_host_init,
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};
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static int __init kirin_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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pp->msi_irq = platform_get_irq(pdev, 0);
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if (!pp->msi_irq) {
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dev_err(&pdev->dev, "failed to get msi irq\n");
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return -ENODEV;
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}
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ret = devm_request_irq(&pdev->dev, pp->msi_irq,
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kirin_pcie_msi_irq_handler,
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IRQF_SHARED | IRQF_NO_THREAD,
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"kirin_pcie_msi", pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to request msi irq\n");
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return ret;
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &kirin_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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return ret;
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}
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int kirin_pcie_save_rc_cfg(struct kirin_pcie *pcie)
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{
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int ret;
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u32 val = 0;
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int aer_pos;
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struct pcie_port *pp;
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pp = &(pcie->pp);
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kirin_pcie_rd_own_conf(pp, PORT_MSI_CTRL_ADDR, 4, &val);
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pcie->msi_controller_config[0] = val;
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kirin_pcie_rd_own_conf(pp, PORT_MSI_CTRL_UPPER_ADDR, 4, &val);
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pcie->msi_controller_config[1] = val;
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kirin_pcie_rd_own_conf(pp, PORT_MSI_CTRL_INT0_ENABLE, 4, &val);
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pcie->msi_controller_config[2] = val;
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aer_pos = pci_find_ext_capability(pcie->rc_dev, PCI_EXT_CAP_ID_ERR);
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if (!aer_pos ) {
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dev_err(pcie->pp.dev, "Failed to get RC PCI_EXT_CAP_ID_ERR\n");
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return -EINVAL;
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}
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pci_read_config_dword(pcie->rc_dev, aer_pos + PCI_ERR_ROOT_COMMAND,
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&pcie->aer_config);
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ret = pci_save_state(pcie->rc_dev);
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if (ret) {
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dev_err(pcie->pp.dev, "Failed to save state of RC\n");
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return -EINVAL;
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}
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pcie->rc_saved_state = pci_store_saved_state(pcie->rc_dev);
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return 0;
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}
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int kirin_pcie_restore_rc_cfg(struct kirin_pcie *pcie)
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{
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struct pcie_port *pp;
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int aer_pos;
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pp = &(pcie->pp);
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kirin_pcie_wr_own_conf(pp, PORT_MSI_CTRL_ADDR,
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4, pcie->msi_controller_config[0]);
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kirin_pcie_wr_own_conf(pp, PORT_MSI_CTRL_UPPER_ADDR,
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4, pcie->msi_controller_config[1]);
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kirin_pcie_wr_own_conf(pp, PORT_MSI_CTRL_INT0_ENABLE,
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4, pcie->msi_controller_config[2]);
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aer_pos = pci_find_ext_capability(pcie->rc_dev, PCI_EXT_CAP_ID_ERR);
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if (!aer_pos ) {
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dev_err(pcie->pp.dev, "Failed to get RC PCI_EXT_CAP_ID_ERR\n");
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return -EINVAL;
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}
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pci_write_config_dword(pcie->rc_dev, aer_pos + PCI_ERR_ROOT_COMMAND,
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pcie->aer_config);
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pci_load_saved_state(pcie->rc_dev, pcie->rc_saved_state);
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pci_restore_state(pcie->rc_dev);
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return 0;
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}
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static int kirin_pcie_probe(struct platform_device *pdev)
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{
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struct kirin_pcie *pcie;
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struct pcie_port *pp;
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int ret;
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u32 dev_id;
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u32 vendor_id;
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int (*pcie_probe)(struct kirin_pcie *);
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "NULL node\n");
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return -EINVAL;
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}
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pcie = devm_kzalloc(&pdev->dev,
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sizeof(struct kirin_pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pp = &pcie->pp;
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g_kirin_pcie = pcie;
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pp->dev = &pdev->dev;
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pcie->pcie_ops= of_device_get_match_data(pp->dev);
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if (!pcie->pcie_ops) {
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dev_err(&pdev->dev, "failed to get pcie_ops\n");
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return -EINVAL;
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}
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pcie_probe = pcie->pcie_ops->pcie_probe;
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if (!pcie_probe) {
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dev_err(&pdev->dev, "failed to get pcie_probe function\n");
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return -EINVAL;
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}
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ret = pcie_probe(pcie);
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if (ret) {
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dev_err(&pdev->dev, "pcie_probe fail\n");
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return -EINVAL;
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}
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ret = kirin_add_pcie_port(pp, pdev);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, pcie);
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kirin_pcie_rd_own_conf(pp, PCI_VENDOR_ID, 2, &vendor_id);
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kirin_pcie_rd_own_conf(pp, PCI_DEVICE_ID, 2, &dev_id);
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pcie->rc_dev = pci_get_device(vendor_id, dev_id, pcie->rc_dev);
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if (!pcie->rc_dev) {
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dev_err(&pdev->dev, "Failed to get RC device\n");
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return -EINVAL;
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}
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ret = kirin_pcie_save_rc_cfg(pcie);
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return 0;
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}
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#ifdef CONFIG_PM
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static int kirin_pcie_resume_noirq(struct device *dev)
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{
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int ret;
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struct kirin_pcie *pcie;
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int (*pcie_resume_noirq)(struct device *);
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pcie = dev_get_drvdata(dev);
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if (!pcie) {
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dev_err(dev, "Failed to get drvdata\n");
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return -EINVAL;
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}
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pcie_resume_noirq = pcie->pcie_ops->pcie_resume_noirq;
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if (!pcie_resume_noirq) {
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dev_err(dev, "failed to get pcie_resume_noirq function\n");
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return 0;
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}
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ret = pcie_resume_noirq(dev);
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if (ret)
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return ret;
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ret = kirin_pcie_establish_link(&(pcie->pp));
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if (ret)
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return ret;
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return 0;
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}
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static int kirin_pcie_suspend_noirq(struct device *dev)
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{
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int ret;
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struct kirin_pcie *pcie;
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int (*pcie_suspend_noirq)(struct device *);
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pcie = dev_get_drvdata(dev);
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if (!pcie) {
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dev_err(dev, "Failed to get drvdata\n");
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return -EINVAL;
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}
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pcie_suspend_noirq = pcie->pcie_ops->pcie_suspend_noirq;
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if (!pcie_suspend_noirq) {
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dev_err(dev, "failed to get pcie_suspend_noirq function\n");
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return 0;
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}
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ret = pcie_suspend_noirq(dev);
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if (ret)
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return ret;
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return 0;
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}
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#else
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#define kirin_pcie_suspend_noirq NULL
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#define kirin_pcie_resume_noirq NULL
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#endif
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static const struct dev_pm_ops kirin_pcie_dev_pm_ops = {
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.suspend_noirq = kirin_pcie_suspend_noirq,
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.resume_noirq = kirin_pcie_resume_noirq,
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};
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static const struct of_device_id kirin_pcie_match[] = {
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{
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.compatible = "hisilicon,hikey960",
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.data = &kirin960_pcie_ops
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},
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{
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.compatible = "hisilicon,hikey970",
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.data = &kirin970_pcie_ops
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, kirin_pcie_match);
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struct platform_driver kirin_pcie_driver = {
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.probe = kirin_pcie_probe,
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.driver = {
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.name = "Kirin-pcie",
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.owner = THIS_MODULE,
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.of_match_table = kirin_pcie_match,
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.pm =&kirin_pcie_dev_pm_ops,
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},
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};
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module_platform_driver(kirin_pcie_driver);
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