hifi-mailbox: ipcm:Pulled code from hisilicon open source
Here is the link to hisilicon kernel open source tree and look for "MHA" Description "Mate 9, MHA, Android 7.0, EMUI 5.0" http://consumer.huawei.com/en/opensource/detail/index.htm?siteCode=worldwide&productCode=Smartphones&fileType=openSourceSoftware&pageSize=10&curPage=1 Added hifi-mailbox:ipcm Signed-off-by: Niranjan Yadla <nyadla@cadence.com>
This commit is contained in:
Niranjan Yadla
committed by
Dmitry Shmidt
Dmitry Shmidt
parent
bacafe9e71
commit
6d1ee5eb03
@@ -10,6 +10,7 @@ if HISILICON_PLATFORM
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source "drivers/hisi/mailbox/Kconfig"
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source "drivers/hisi/hifi_dsp/Kconfig"
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source "drivers/hisi/hifi_mailbox/Kconfig"
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endif #HISILICON_PLATFORM
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@@ -1,3 +1,4 @@
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obj-$(CONFIG_HISILICON_PLATFORM_MAILBOX) += mailbox/
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obj-$(CONFIG_HIFI_DSP_ONE_TRACK) += hifi_dsp/
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obj-$(CONFIG_HIFI_MAILBOX) += hifi_mailbox/
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@@ -0,0 +1 @@
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source "drivers/hisi/hifi_mailbox/ipcm/Kconfig"
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@@ -0,0 +1,2 @@
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obj-$(CONFIG_HIFI_IPC) += ipcm/
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@@ -0,0 +1,23 @@
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menu "Hifi mailbox driver"
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config HIFI_IPC
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bool "k3 multicore ipc driver"
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default n
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help
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k3 multicore ipc driver.
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config HIFI_IPC_3650
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bool "hifi 3650 mailbox driver base on ipc"
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default n
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help
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transplant 3650 mailbox driver.
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config HIFI_IPC_3660
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bool "hifi 3660 mailbox driver base on ipc"
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default n
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help
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transplant 3660 mailbox driver.
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config HIFI_IPC_6250
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bool "hifi 6250 mailbox driver base on ipc"
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default n
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help
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transplant 6250 mailbox driver.
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endmenu
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@@ -0,0 +1,5 @@
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EXTRA_CFLAGS += -I$(srctree)/drivers/hisi/hifi_mailbox/mailbox/
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obj-$(CONFIG_HIFI_IPC) := bsp_ipc.o
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@@ -0,0 +1,116 @@
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#ifndef _BSP_DRV_IPC_H_
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#define _BSP_DRV_IPC_H_
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#include <asm/io.h>
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#include "drv_comm.h"
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#include "../mailbox/mdrv_ipc_enum.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void __iomem *ipc_base;
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#define SIZE_4K (4096)
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#define BSP_IPC_BASE_ADDR (SOC_IPC_S_BASE_ADDR)
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#define IPC_REG_SIZE (SIZE_4K)
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#define BSP_RegRd(uwAddr) (0)
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#define BSP_RegWr(uwAddr, uwValue)
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#define SOC_IPC_CPU_INT_EN_ADDR(base, i) ((base) + (0x500+(0x10*(i))))
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#define SOC_IPC_SEM_INT_MASK_ADDR(base, j) ((base) + (0x604+(0x10*(j))))
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#define SOC_IPC_CPU_INT_CLR_ADDR(base, i) ((base) + (0x40C+(0x10*(i))))
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#define IRQ_IPC0_S (252)
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#define IRQ_IPC1_S (253)
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#define SOC_IPC_CPU_INT_EN_ADDR(base, i) ((base) + (0x500+(0x10*(i))))
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#define SOC_IPC_CPU_INT_DIS_ADDR(base, i) ((base) + (0x504+(0x10*(i))))
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#define SOC_IPC_CPU_INT_STAT_ADDR(base, i) ((base) + (0x408+(0x10*(i))))
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#define SOC_IPC_CPU_RAW_INT_ADDR(base, i) ((base) + (0x400+(0x10*(i))))
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#define SOC_IPC_CPU_INT_MASK_ADDR(base, i) ((base) + (0x404+(0x10*(i))))
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#define SOC_IPC_SEM_INT_CLR_ADDR(base, j) ((base) + (0x60C+(0x10*(j))))
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#define SOC_IPC_HS_CTRL_ADDR(base, j, k) ((base) + (0x800+(0x100*(j))+(0x8*(k))))
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#define SOC_IPC_SEM_INT_STAT_ADDR(base, j) ((base) + (0x608+(0x10*(j))))
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#define SOC_IPC_S_BASE_ADDR (0xe0475000)
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#define SOC_IPC_CPU_INT_MASK_DIS_ADDR(base, i) SOC_IPC_CPU_INT_EN_ADDR(base, i)
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#define SOC_IPC_CPU_INT_MASK_EN_ADDR(base, i) SOC_IPC_CPU_INT_DIS_ADDR(base, i)
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#define BSP_IPC_CPU_RAW_INT(i) (SOC_IPC_CPU_RAW_INT_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_CPU_INT_MASK(i) (SOC_IPC_CPU_INT_MASK_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_CPU_INT_STAT(i) (SOC_IPC_CPU_INT_STAT_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_CPU_INT_CLR(i) (SOC_IPC_CPU_INT_CLR_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_INT_MASK_EN(i) (SOC_IPC_CPU_INT_MASK_EN_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_INT_MASK_DIS(i) (SOC_IPC_CPU_INT_MASK_DIS_ADDR((BSP_U32)ipc_base, i))
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#define BSP_IPC_SEM_RAW_INT(j) (SOC_IPC_SEM_RAW_INT_ADDR((BSP_U32)ipc_base, j))
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#define BSP_IPC_SEM_INT_MASK(j) (SOC_IPC_SEM_INT_MASK_ADDR((BSP_U32)ipc_base, j))
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#define BSP_IPC_SEM_INT_STAT(j) (SOC_IPC_SEM_INT_STAT_ADDR((BSP_U32)ipc_base, j))
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#define BSP_IPC_SEM_INT_CLR(j) (SOC_IPC_SEM_INT_CLR_ADDR((BSP_U32)ipc_base, j))
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#define BSP_IPC_HS_CTRL(j, k) (SOC_IPC_HS_CTRL_ADDR((BSP_U32)ipc_base, j, k))
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#define BSP_IPC_HS_STAT(j, k) (SOC_IPC_HS_STAT_ADDR((BSP_U32)ipc_base, j, k))
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#define BSP_IPC_CPU_RAW_INT_ACPU (BSP_IPC_CPU_RAW_INT((BSP_U32)IPC_CORE_ACPU))
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#define BSP_IPC_CPU_INT_MASK_ACPU (BSP_IPC_CPU_INT_MASK((BSP_U32)IPC_CORE_ACPU))
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#define BSP_IPC_CPU_INT_STAT_ACPU (BSP_IPC_CPU_INT_STAT((BSP_U32)IPC_CORE_ACPU))
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#define BSP_IPC_CPU_INT_CLR_ACPU (BSP_IPC_CPU_INT_CLR((BSP_U32)IPC_CORE_ACPU))
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#define BSP_IPC_CPU_INT_MASK_EN_ACPU (BSP_IPC_INT_MASK_EN((BSP_U32)IPC_CORE_ACPU))
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#define BSP_IPC_CPU_INT_MASK_DIS_ACPU (BSP_IPC_INT_MASK_DIS((BSP_U32)IPC_CORE_ACPU))
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#define UCOM_COMM_UINT32_MAX (0xffffffff)
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#define BSP_IPC_MAX_INT_NUM (32)
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#define IPC_MASK 0xFFFFFF0F
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#define INT_LEV_IPC_CPU (IRQ_IPC0_S)
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#define INT_LEV_IPC_SEM (IRQ_IPC1_S)
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#define INT_VEC_IPC_SEM IVEC_TO_INUM(INT_LEV_IPC_SEM)
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#define INTSRC_NUM 32
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#define INT_VEC_IPC_CPU IVEC_TO_INUM(INT_LEV_IPC_CPU)
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#define IPC_CHECK_PARA(ulLvl) \
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do {\
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if (ulLvl >= INTSRC_NUM) {\
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pr_warn("Wrong para , line:%d\n", __LINE__);\
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return BSP_ERROR;\
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} \
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} while (0)
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typedef struct tagIPC_DEV_S {
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BSP_BOOL bInit;
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} IPC_DEV_S;
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typedef struct {
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VOIDFUNCPTR routine;
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BSP_U32 arg;
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} BSP_IPC_ENTRY;
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typedef struct tagIPC_DEBUG_E {
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BSP_U32 u32RecvIntCore;
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BSP_U32 u32IntHandleTimes[INTSRC_NUM];
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BSP_U32 u32IntSendTimes[INTSRC_NUM];
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BSP_U32 u32SemId;
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BSP_U32 u32SemTakeTimes[INTSRC_NUM];
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BSP_U32 u32SemGiveTimes[INTSRC_NUM];
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} IPC_DEBUG_E;
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BSP_S32 DRV_IPCIntInit(void);
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BSP_S32 IPC_IntEnable(IPC_INT_LEV_E ulLvl);
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BSP_S32 IPC_IntConnect(IPC_INT_LEV_E ulLvl, VOIDFUNCPTR routine,
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BSP_U32 parameter);
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BSP_S32 IPC_IntSend(IPC_INT_CORE_E enDstCore, IPC_INT_LEV_E ulLvl);
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BSP_VOID IPC_SpinLock(BSP_U32 u32SignalNum);
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BSP_VOID IPC_SpinUnLock(BSP_U32 u32SignalNum);
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BSP_VOID IPC_SemGive_Ccore_All(BSP_VOID);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end #define _BSP_IPC_H_ */
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@@ -0,0 +1,436 @@
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/string.h>
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#include <linux/semaphore.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/notifier.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/hisi/hisi_mailbox.h>
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#include <linux/hisi/hisi_rproc.h>
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#include "bsp_drv_ipc.h"
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/*#define USE_HIFI_IPC*/
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BSP_IPC_ENTRY stIpcIntTable[INTSRC_NUM];
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static IPC_DEV_S g_stIpcDev = { 0 };
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BSP_U32 g_CoreNum;
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struct semaphore g_semIpcTask[INTSRC_NUM];
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IPC_DEBUG_E g_stIpc_debug = { 0 };
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/* base address of ipc registers */
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void __iomem *ipc_base;
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spinlock_t g_ipc_int_lock = __SPIN_LOCK_UNLOCKED("ipc");
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#define USE_HISI_MAILBOX
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/*************************************k3 ipc******************************************/
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#define BIT_ENABLE(n) (1 << (n))
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#define BYTE_REF(address) (*((unsigned char volatile *) (address)))
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#define HALFWORD_REF(address) (*((unsigned short volatile *) (address)))
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#define WORD_REF(address) (*((unsigned int volatile *) (address)))
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#define WORD_PTR(address) (*((unsigned int volatile **) (address)))
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#define BYTE(address) volatile unsigned char __attribute__((section(".ARM.__at_"address)))
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#define HALFWORD(address) volatile unsigned short __attribute__((section(".ARM.__at_"address)))
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#define WORD(address) volatile unsigned int __attribute__((section(".ARM.__at_"address)))
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#define K3_IPC_MODE_ACK (7)
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#define K3_IPC_MODE_IDLE (4)
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#define K3_IPC_MODE_AUTOACK (0)
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/*************************************hifiϵͳipc******************************************/
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#define K3_SYS_IPC_BASE_ADDR_S (unsigned long)(0xe896a000)
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#define K3_SYS_IPC_BASE_ADDR_NS (unsigned long)(0xe896b000)
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#define K3_SYS_IPC_REG_SIZE (0xA00)
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#define K3_IPC_LOCK(base) WORD_REF(base + 0xA00)
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#define K3_IPC_SOURCE(base, box) WORD_REF(base + ((box) * 64))
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#define K3_IPC_DEST(base, box) WORD_REF(base + ((box) * 64) + 0x04)
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#define K3_IPC_DCLR(base, box) WORD_REF(base + ((box) * 64) + 0x08)
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#define K3_IPC_DSTATUS(base, box) WORD_REF(base + ((box) * 64) + 0x0c)
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#define K3_IPC_MODE(base, box) WORD_REF(base + ((box) * 64) + 0x10)
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#define K3_IPC_IMASK(base, box) WORD_REF(base + ((box) * 64) + 0x14)
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#define K3_IPC_ICLR(base, box) WORD_REF(base + ((box) * 64) + 0x18)
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#define K3_IPC_SEND(base, box) WORD_REF(base + ((box) * 64) + 0x1c)
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#define K3_IPC_DATA(base, box, num) WORD_REF(base + ((box) * 64) + 0x20 + ((num) * 4))
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#define K3_IPC_CPUIMST(base, core) WORD_REF(base + 0x800 + ((core) * 8))
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#define K3_IPC_CPUIRST(base, core) WORD_REF(base + 0x804 + ((core) * 8))
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#define K3_SYS_IPC_CORE_LIT (0)
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#define K3_SYS_IPC_CORE_BIG (1)
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#define K3_SYS_IPC_CORE_IOM3 (2)
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#define K3_SYS_IPC_CORE_LPM3 (3)
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#define K3_SYS_IPC_CORE_HIFI (4)
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#define K3_HIFI_IPC_BASE_ADDR (unsigned long)(0xE804C000)
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#define K3_HIFI_IPC_REG_SIZE (0x1000)
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#define K3_ASP_CFG_CTRLDIS(base) WORD_REF(base + 0x04)
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#define K3_ASP_CFG_GATE_EN(base) WORD_REF(base + 0x0c)
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enum {
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K3_HIFI_IPC_CORE_AP_LPM3_IOM3 = 0,
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K3_HIFI_IPC_CORE_MODEM_A9 = 1,
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K3_HIFI_IPC_CORE_MODEM_BBE = 2,
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K3_HIFI_IPC_CORE_HIFI = 3,
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K3_HIFI_IPC_CORE_IOM3 = 5,
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K3_HIFI_IPC_CORE_AP = 6,
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K3_HIFI_IPC_CORE_LPM3 = 8,
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};
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typedef enum {
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K3_SEC_SYS_IPC = 0,
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K3_UNSEC_SYS_IPC,
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K3_HIFI_IPC,
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} K3_IPC;
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typedef struct {
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K3_IPC ipcMode;
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void __iomem *ipcBase;
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int mailBoxNum;
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int intNum;
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int sourceCore;
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int destCore;
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} K3_IPC_CONFIG;
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enum {
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K3_IPC_CORE_IS_SEND = 0,
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K3_IPC_CORE_IS_RECEIVE,
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K3_IPC_CORE_IS_UNKNOEN,
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};
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static K3_IPC_CONFIG k3IpcConfig[K3_IPC_CORE_IS_UNKNOEN] = {
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{
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K3_UNSEC_SYS_IPC,
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NULL,
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18,
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220,
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K3_SYS_IPC_CORE_LIT,
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K3_SYS_IPC_CORE_HIFI},
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{
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K3_UNSEC_SYS_IPC,
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NULL,
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2,
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227,
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K3_SYS_IPC_CORE_HIFI,
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K3_SYS_IPC_CORE_BIG}
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};
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static int DRV_k3IpcIntHandler_ipc(struct notifier_block *nb, unsigned long len,
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void *msg);
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struct hisi_mbox *hifi_tx_mbox;
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struct notifier_block rx_nb;
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#ifdef USE_HISI_MAILBOX
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#define MAX_SEND_IPC_TRY 3
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static int hisi_hifi_mbox_init(void)
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{
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int ret = 0, rproc_id = 0;
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rx_nb.next = NULL;
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rx_nb.notifier_call = DRV_k3IpcIntHandler_ipc;
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rproc_id = HISI_RPROC_HIFI_MBX2;
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/* register the rx notify callback */
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ret = RPROC_MONITOR_REGISTER(rproc_id, &rx_nb);
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if (ret)
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pr_info("%s:RPROC_MONITOR_REGISTER failed", __func__);
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return ret;
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}
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/*
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static void hisi_hifi_mbox_exit(void)
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{
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if (hifi_mbox)
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hisi_mbox_put(&hifi_mbox);
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}
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*/
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#else
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static irqreturn_t DRV_k3IpcIntHandler_ack(int irq, void *dev_id)
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{
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BSP_S32 retval = IRQ_HANDLED;
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BSP_U32 u32IntStat = 0;
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int myRole = K3_IPC_CORE_IS_SEND;
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BSP_U32 mailBoxNum = k3IpcConfig[myRole].mailBoxNum;
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BSP_U32 source = k3IpcConfig[myRole].sourceCore;
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void __iomem *ipcBase = k3IpcConfig[myRole].ipcBase;
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u32IntStat = K3_IPC_CPUIMST(ipcBase, source);
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if (u32IntStat & BIT_ENABLE(mailBoxNum)) {
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if (K3_IPC_MODE(ipcBase, mailBoxNum) &
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BIT_ENABLE(K3_IPC_MODE_ACK)) {
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pr_info("func:%s: Receive ack int\n", __func__);
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K3_IPC_SOURCE(ipcBase, mailBoxNum) = BIT_ENABLE(source);
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}
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K3_IPC_DCLR(ipcBase, mailBoxNum) = BIT_ENABLE(mailBoxNum);
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}
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return (irqreturn_t) IRQ_RETVAL(retval);
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}
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#endif
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BSP_S32 DRV_IPCIntInit(void)
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{
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int myRole = 0;
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printk(KERN_ERR "DRV_IPCIntInit begin.\n");
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if (BSP_TRUE == g_stIpcDev.bInit) {
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return BSP_OK;
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}
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printk(KERN_ERR "DRV_IPCIntInit line = %d\n", __LINE__);
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g_CoreNum = IPC_CORE_ACPU;
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memset((void *)stIpcIntTable, 0x0,
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(INTSRC_NUM * sizeof(BSP_IPC_ENTRY)));
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myRole = K3_IPC_CORE_IS_SEND;
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if (K3_UNSEC_SYS_IPC == k3IpcConfig[myRole].ipcMode) {
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k3IpcConfig[myRole].ipcBase =
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ioremap(K3_SYS_IPC_BASE_ADDR_NS, K3_SYS_IPC_REG_SIZE);
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if (!k3IpcConfig[myRole].ipcBase) {
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||||
printk(KERN_ERR
|
||||
"line %d :k3 unsec sys ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
} else if (K3_SEC_SYS_IPC == k3IpcConfig[myRole].ipcMode) {
|
||||
k3IpcConfig[myRole].ipcBase =
|
||||
ioremap(K3_SYS_IPC_BASE_ADDR_S, K3_SYS_IPC_REG_SIZE);
|
||||
if (!k3IpcConfig[myRole].ipcBase) {
|
||||
printk(KERN_ERR
|
||||
"line %d :k3 sec sys ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
k3IpcConfig[myRole].ipcBase =
|
||||
ioremap(K3_HIFI_IPC_BASE_ADDR, K3_HIFI_IPC_REG_SIZE);
|
||||
if (!k3IpcConfig[myRole].ipcBase) {
|
||||
printk(KERN_ERR "line %d :k3 hifi ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
K3_IPC_LOCK(k3IpcConfig[myRole].ipcBase) = 0x1ACCE551;
|
||||
myRole = K3_IPC_CORE_IS_RECEIVE;
|
||||
if (K3_UNSEC_SYS_IPC == k3IpcConfig[myRole].ipcMode) {
|
||||
k3IpcConfig[myRole].ipcBase =
|
||||
ioremap(K3_SYS_IPC_BASE_ADDR_NS, K3_SYS_IPC_REG_SIZE);
|
||||
if (!k3IpcConfig[myRole].ipcBase) {
|
||||
printk(KERN_ERR
|
||||
"line %d :k3 unsec sys ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
} else if (K3_SEC_SYS_IPC == k3IpcConfig[myRole].ipcMode) {
|
||||
k3IpcConfig[myRole].ipcBase =
|
||||
ioremap(K3_SYS_IPC_BASE_ADDR_S, K3_SYS_IPC_REG_SIZE);
|
||||
if (!k3IpcConfig[myRole].ipcBase) {
|
||||
printk(KERN_ERR
|
||||
"line %d :k3 sec sys ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
k3IpcConfig[myRole].ipcBase =
|
||||
ioremap(K3_HIFI_IPC_BASE_ADDR, K3_HIFI_IPC_REG_SIZE);
|
||||
if (!k3IpcConfig[myRole].ipcBase) {
|
||||
printk(KERN_ERR "line %d :k3 hifi ipc ioremap error.\n",
|
||||
__LINE__);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
K3_IPC_LOCK(k3IpcConfig[myRole].ipcBase) = 0x1ACCE551;
|
||||
#ifdef USE_HISI_MAILBOX
|
||||
hisi_hifi_mbox_init();
|
||||
#else
|
||||
ret = request_irq(k3IpcConfig[K3_IPC_CORE_IS_SEND].intNum,
|
||||
DRV_k3IpcIntHandler_ack, 0, "k3IpcIntHandler_ack",
|
||||
NULL);
|
||||
if (ret) {
|
||||
printk(KERN_ERR
|
||||
"BSP_DRV_IPCIntInit: Unable to register ipc irq ret=%d.\n",
|
||||
ret);
|
||||
return BSP_ERROR;
|
||||
}
|
||||
printk(KERN_ERR "BSP_DRV_IPCIntInit line = %d\n", __LINE__);
|
||||
#endif
|
||||
|
||||
g_stIpcDev.bInit = BSP_TRUE;
|
||||
|
||||
printk(KERN_ERR "BSP_DRV_IPCIntInit end.\n");
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
BSP_S32 IPC_IntEnable(IPC_INT_LEV_E ulLvl)
|
||||
{
|
||||
IPC_CHECK_PARA(ulLvl);
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
BSP_S32 IPC_IntDisable(IPC_INT_LEV_E ulLvl)
|
||||
{
|
||||
IPC_CHECK_PARA(ulLvl);
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
BSP_S32 IPC_IntConnect(IPC_INT_LEV_E ulLvl, VOIDFUNCPTR routine,
|
||||
BSP_U32 parameter)
|
||||
{
|
||||
|
||||
unsigned long flag = 0;
|
||||
|
||||
IPC_CHECK_PARA(ulLvl);
|
||||
|
||||
spin_lock_irqsave(&g_ipc_int_lock, flag);
|
||||
stIpcIntTable[ulLvl].routine = routine;
|
||||
stIpcIntTable[ulLvl].arg = parameter;
|
||||
spin_unlock_irqrestore(&g_ipc_int_lock, flag);
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
BSP_S32 IPC_IntDisonnect(IPC_INT_LEV_E ulLvl, VOIDFUNCPTR routine,
|
||||
BSP_U32 parameter)
|
||||
{
|
||||
unsigned long flag = 0;
|
||||
|
||||
IPC_CHECK_PARA(ulLvl);
|
||||
|
||||
spin_lock_irqsave(&g_ipc_int_lock, flag);
|
||||
stIpcIntTable[ulLvl].routine = NULL;
|
||||
stIpcIntTable[ulLvl].arg = 0;
|
||||
spin_unlock_irqrestore(&g_ipc_int_lock, flag);
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
static int DRV_k3IpcIntHandler_ipc(struct notifier_block *nb, unsigned long len,
|
||||
void *msg)
|
||||
{
|
||||
BSP_U32 newLevel = 0;
|
||||
mbox_msg_t *_msg = (mbox_msg_t *) msg;
|
||||
|
||||
newLevel = _msg[0];
|
||||
|
||||
if (newLevel < INTSRC_NUM) {
|
||||
g_stIpc_debug.u32IntHandleTimes[newLevel]++;
|
||||
|
||||
if (NULL != stIpcIntTable[newLevel].routine) {
|
||||
stIpcIntTable[newLevel].routine(stIpcIntTable[newLevel].
|
||||
arg);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
BSP_S32 IPC_IntSend(IPC_INT_CORE_E enDstCore, IPC_INT_LEV_E ulLvl)
|
||||
{
|
||||
int myRole = K3_IPC_CORE_IS_SEND;
|
||||
BSP_U32 source = k3IpcConfig[myRole].sourceCore;
|
||||
|
||||
#ifdef USE_HISI_MAILBOX
|
||||
BSP_U32 ipcMsg[2];
|
||||
int ret = 0, rproc_id = 0;
|
||||
#else
|
||||
BSP_U32 mailBoxNum = k3IpcConfig[myRole].mailBoxNum;
|
||||
BSP_U32 dest = k3IpcConfig[myRole].destCore;
|
||||
void __iomem *ipcBase = k3IpcConfig[myRole].ipcBase;
|
||||
#endif
|
||||
|
||||
IPC_CHECK_PARA(ulLvl);
|
||||
|
||||
if (IPC_CORE_HiFi == enDstCore) {
|
||||
#ifdef USE_HISI_MAILBOX
|
||||
ipcMsg[0] = (source << 24) | (ulLvl << 8);
|
||||
|
||||
rproc_id = HISI_RPROC_HIFI_MBX18;
|
||||
ret = RPROC_ASYNC_SEND(rproc_id, (mbox_msg_t *) ipcMsg, 2);
|
||||
if (ret) {
|
||||
printk(" %s , line %d, send error\n", __func__,
|
||||
__LINE__);
|
||||
}
|
||||
#else
|
||||
while (0 ==
|
||||
(K3_IPC_MODE(ipcBase, mailBoxNum) &
|
||||
BIT_ENABLE(K3_IPC_MODE_IDLE))) {
|
||||
printk("func:%s: mailbox is busy mode = 0x%x\n",
|
||||
__func__, K3_IPC_MODE(ipcBase, mailBoxNum));
|
||||
}
|
||||
|
||||
K3_IPC_SOURCE(ipcBase, mailBoxNum) = BIT_ENABLE(source);
|
||||
K3_IPC_DEST(ipcBase, mailBoxNum) = BIT_ENABLE(dest);
|
||||
|
||||
K3_IPC_IMASK(ipcBase, mailBoxNum) =
|
||||
~(BIT_ENABLE(source) | BIT_ENABLE(dest));
|
||||
|
||||
K3_IPC_MODE(ipcBase, mailBoxNum) =
|
||||
BIT_ENABLE(K3_IPC_MODE_AUTOACK);
|
||||
|
||||
K3_IPC_DATA(ipcBase, mailBoxNum, 0) = source;
|
||||
K3_IPC_DATA(ipcBase, mailBoxNum, 1) = ulLvl;
|
||||
|
||||
K3_IPC_SEND(ipcBase, mailBoxNum) = BIT_ENABLE(source);
|
||||
|
||||
#endif
|
||||
} else {
|
||||
BSP_RegWr(BSP_IPC_CPU_RAW_INT(enDstCore), 1 << ulLvl);
|
||||
}
|
||||
|
||||
g_stIpc_debug.u32RecvIntCore = enDstCore;
|
||||
g_stIpc_debug.u32IntSendTimes[ulLvl]++;
|
||||
|
||||
return BSP_OK;
|
||||
}
|
||||
|
||||
void BSP_IPC_SpinLock(unsigned int u32SignalNum)
|
||||
{
|
||||
unsigned int u32HsCtrl;
|
||||
|
||||
if (u32SignalNum >= INTSRC_NUM) {
|
||||
printk("BSP_IPC_SpinLock Parameter error, line:%d\n",
|
||||
__LINE__);
|
||||
return;
|
||||
}
|
||||
for (;;) {
|
||||
u32HsCtrl = BSP_RegRd(BSP_IPC_HS_CTRL(g_CoreNum, u32SignalNum));
|
||||
if (0 == u32HsCtrl) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void BSP_IPC_SpinUnLock(unsigned int u32SignalNum)
|
||||
{
|
||||
if (u32SignalNum >= INTSRC_NUM) {
|
||||
printk("BSP_IPC_SpinUnLock Parameter error, line:%d\n",
|
||||
__LINE__);
|
||||
return;
|
||||
}
|
||||
BSP_RegWr(BSP_IPC_HS_CTRL(g_CoreNum, u32SignalNum), 0);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(IPC_IntEnable);
|
||||
EXPORT_SYMBOL(IPC_IntDisable);
|
||||
EXPORT_SYMBOL(IPC_IntConnect);
|
||||
EXPORT_SYMBOL(IPC_IntSend);
|
||||
@@ -0,0 +1,188 @@
|
||||
|
||||
#ifndef __DRV_COMM_H__
|
||||
#define __DRV_COMM_H__
|
||||
|
||||
/*************************GLOBAL BEGIN*****************************/
|
||||
#ifndef _WIN32_COMPILE
|
||||
typedef signed long long BSP_S64;
|
||||
#else
|
||||
typedef double BSP_S64;
|
||||
#endif
|
||||
typedef signed int BSP_S32;
|
||||
typedef signed short BSP_S16;
|
||||
typedef signed char BSP_S8;
|
||||
typedef char BSP_CHAR;
|
||||
typedef char BSP_CHAR_TL;
|
||||
|
||||
#ifndef _WIN32_COMPILE
|
||||
typedef unsigned long long BSP_U64;
|
||||
#else
|
||||
typedef double BSP_U64;
|
||||
#endif
|
||||
typedef unsigned int BSP_U32;
|
||||
typedef unsigned short BSP_U16;
|
||||
typedef unsigned char BSP_U8;
|
||||
|
||||
typedef int BSP_BOOL;
|
||||
typedef void BSP_VOID;
|
||||
typedef int BSP_STATUS;
|
||||
|
||||
#ifndef _WIN32_COMPILE
|
||||
typedef signed long long *BSP_PS64;
|
||||
#else
|
||||
typedef double *BSP_PS64;
|
||||
#endif
|
||||
typedef signed int *BSP_PS32;
|
||||
typedef signed short *BSP_PS16;
|
||||
typedef signed char *BSP_PS8;
|
||||
|
||||
#ifndef _WIN32_COMPILE
|
||||
typedef unsigned long long *BSP_PU64;
|
||||
#else
|
||||
typedef double *BSP_PU64;
|
||||
#endif
|
||||
typedef unsigned int *BSP_PU32;
|
||||
typedef unsigned short *BSP_PU16;
|
||||
typedef unsigned char *BSP_PU8;
|
||||
|
||||
#ifndef UINT8
|
||||
typedef unsigned char UINT8;
|
||||
#endif
|
||||
#ifndef UINT32
|
||||
typedef unsigned int UINT32;
|
||||
#endif
|
||||
typedef int *BSP_PBOOL;
|
||||
typedef void *BSP_PVOID;
|
||||
typedef int *BSP_PSTATUS;
|
||||
|
||||
typedef void VOID;
|
||||
typedef BSP_S32 STATUS;
|
||||
typedef BSP_S32 UDI_HANDLE;
|
||||
|
||||
#ifndef BSP_CONST
|
||||
#define BSP_CONST const
|
||||
#endif
|
||||
|
||||
#ifndef OK
|
||||
#define OK (0)
|
||||
#endif
|
||||
|
||||
#ifndef ERROR
|
||||
#define ERROR (-1)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_OK
|
||||
#define BSP_OK (0)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_ERROR
|
||||
#define BSP_ERROR (-1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_TRUE
|
||||
#define BSP_TRUE (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_FALSE
|
||||
#define BSP_FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_NULL
|
||||
#define BSP_NULL (void *)0
|
||||
#endif
|
||||
|
||||
typedef BSP_S32(*FUNCPTR_1) (int);
|
||||
typedef int (*PWRCTRLFUNCPTRVOID) (void);
|
||||
typedef unsigned int (*PWRCTRLFUNCPTR) (unsigned int arg); /* ptr to function returning int */
|
||||
|
||||
#ifndef INLINE
|
||||
#ifdef __KERNEL__
|
||||
#define INLINE inline
|
||||
#else
|
||||
#define INLINE __inline__
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_CORE_MODEM) || defined(PRODUCT_CFG_CORE_TYPE_MODEM)
|
||||
#ifndef _VOIDFUNCPTR_DEFINED
|
||||
typedef BSP_VOID(*VOIDFUNCPTR) ();
|
||||
#endif
|
||||
#else
|
||||
typedef BSP_VOID(*VOIDFUNCPTR) (BSP_U32);
|
||||
#define SEM_FULL (1)
|
||||
#define SEM_EMPTY (0)
|
||||
#define LOCAL static
|
||||
#define IVEC_TO_INUM(intVec) ((int)(intVec))
|
||||
#endif
|
||||
|
||||
#define BSP_ERR_MODULE_OFFSET (0x1000)
|
||||
#define BSP_DEF_ERR(mod, errid) \
|
||||
((((BSP_U32) mod + BSP_ERR_MODULE_OFFSET) << 16) | (errid))
|
||||
|
||||
#define BSP_REG(base, reg) (*(volatile BSP_U32 *)((BSP_U32)base + (reg)))
|
||||
|
||||
#if defined(BSP_CORE_MODEM) || defined(PRODUCT_CFG_CORE_TYPE_MODEM) || defined(__VXWORKS__)
|
||||
#define BSP_REG_READ(base, reg, result) \
|
||||
((result) = BSP_REG(base, reg))
|
||||
|
||||
#define BSP_REG_WRITE(base, reg, data) \
|
||||
(BSP_REG(base, reg) = (data))
|
||||
|
||||
#else
|
||||
#define BSP_REG_READ(base, reg, resule) \
|
||||
(resule = readl(base + reg))
|
||||
|
||||
#define BSP_REG_WRITE(base, reg, data) \
|
||||
(writel(data, (base + reg)))
|
||||
#endif
|
||||
|
||||
#define BSP_REG_SETBITS(base, reg, pos, bits, val) (BSP_REG(base, reg) = (BSP_REG(base, reg) & (~((((u32)1 << (bits)) - 1) << (pos)))) \
|
||||
| ((u32)((val) & (((u32)1 << (bits)) - 1)) << (pos)))
|
||||
#define BSP_REG_GETBITS(base, reg, pos, bits) ((BSP_REG(base, reg) >> (pos)) & (((u32)1 << (bits)) - 1))
|
||||
|
||||
#define DRV_OK (0)
|
||||
#define DRV_ERROR (-1)
|
||||
#define DRV_INTERFACE_RSLT_OK (0)
|
||||
|
||||
typedef int (*pFUNCPTR) (void);
|
||||
|
||||
typedef unsigned long (*pFUNCPTR2) (unsigned long ulPara1,
|
||||
unsigned long ulPara2);
|
||||
|
||||
typedef unsigned int tagUDI_DEVICE_ID_UINT32;
|
||||
|
||||
typedef struct {
|
||||
BSP_U32 ulblockCount;
|
||||
BSP_U32 ulpageSize;
|
||||
BSP_U32 ulpgCntPerBlk;
|
||||
} DLOAD_FLASH_STRU;
|
||||
typedef BSP_VOID(*UpLinkRxFunc) (BSP_U8 *buf, BSP_U32 len);
|
||||
|
||||
typedef BSP_VOID(*FreePktEncap) (BSP_VOID *PktEncap);
|
||||
|
||||
typedef enum tagGMAC_OWNER_E {
|
||||
GMAC_OWNER_VXWORKS = 0,
|
||||
GMAC_OWNER_PS,
|
||||
GMAC_OWNER_MSP,
|
||||
GMAC_OWNER_MAX
|
||||
} GMAC_OWNER_E;
|
||||
|
||||
typedef enum tagWDT_TIMEOUT_E {
|
||||
WDT_TIMEOUT_1 = 0, /*0xFFFF000/WDT_CLK_FREQ, about 3657ms *//*WDT_CLK_FREQ = ARM_FREQ/6 = 70M */
|
||||
WDT_TIMEOUT_2, /*0x1FFFE000/WDT_CLK_FREQ, about 7314ms */
|
||||
WDT_TIMEOUT_3, /*0x3FFFC000/WDT_CLK_FREQ, about 14628ms */
|
||||
WDT_TIMEOUT_4, /*0x7FFF8000/WDT_CLK_FREQ, about 29257ms */
|
||||
WDT_TIMEOUT_BUTT
|
||||
} WDT_TIMEOUT_E;
|
||||
|
||||
/*************************GLOBAL END****************************/
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user