zwx305167
cae64574fd
Add dts and defconfig support HDMI&LCD display function for hikey970. Signed-off-by: zwx305167 <zwx305167@notesmail.huawei.com>
136 lines
3.1 KiB
Devicetree
Executable File
136 lines
3.1 KiB
Devicetree
Executable File
/{
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dpe: dpe@E8600000 {
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compatible = "hisilicon,kirin970-dpe";
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status = "ok"
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dss_version_tag = <0x40>;
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// DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG
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reg = <0 0xE8600000 0 0xC0000>,
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<0 0xFFF35000 0 0x1000>,
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<0 0xFFF0A000 0 0x1000>,
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<0 0xE8A09000 0 0x1000>,
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<0 0xE86C0000 0 0x10000>,
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<0 0xFFF31000 0 0x1000>,
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<0 0xE87FF000 0 0x1000>;
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// dss-pdp
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interrupts = <0 245 4>;
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/*regulator_dsssubsys-supply = <&dsssubsys>;
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regulator_mmbuf-supply = <&mmbuf>;*/
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clocks = <&media1_crg KIRIN970_ACLK_GATE_DSS>,
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<&media1_crg KIRIN970_PCLK_GATE_DSS>,
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<&media1_crg KIRIN970_CLK_GATE_EDC0>,
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<&media1_crg KIRIN970_CLK_GATE_LDI0>,
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<&media1_crg KIRIN970_CLK_GATE_DSS_AXI_MM>,
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<&media1_crg KIRIN970_PCLK_GATE_MMBUF>,
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<&crg_ctrl KIRIN970_PCLK_GATE_PCTRL>;
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clock-names = "aclk_dss",
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"pclk_dss",
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"clk_edc0",
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"clk_ldi0",
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"clk_dss_axi_mm",
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"pclk_mmbuf",
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"pclk_pctrl";
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dma-coherent;
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port {
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dpe_out: endpoint {
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remote-endpoint = <&dsi_in>;
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};
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};
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iommu_info {
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start-addr = <0x8000>;
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size = <0xbfff8000>;
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};
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};
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dsi: dsi@E8601000 {
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compatible = "hisilicon,kirin970-dsi";
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status = "ok"
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reg = <0 0xE8601000 0 0x7F000>,
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<0 0xFFF35000 0 0x1000>,
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<0 0xE8A09000 0 0x1000>;
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clocks = <&crg_ctrl KIRIN970_CLK_GATE_TXDPHY0_REF>,
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<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY1_REF>,
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<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY0_CFG>,
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<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY1_CFG>,
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<&crg_ctrl KIRIN970_PCLK_GATE_DSI0>,
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<&crg_ctrl KIRIN970_PCLK_GATE_DSI1>;
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clock-names = "clk_txdphy0_ref",
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"clk_txdphy1_ref",
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"clk_txdphy0_cfg",
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"clk_txdphy1_cfg",
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"pclk_dsi0",
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"pclk_dsi1";
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#address-cells = <1>;
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#size-cells = <0>;
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mux-gpio = <&gpio25 7 0>;//HDMI_SEL(GPIO_207)
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi_in: endpoint {
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remote-endpoint = <&dpe_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dsi_out0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&adv7533_in>;
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};
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dsi_out1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&panel0_in>;
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};
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};
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};
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panel@1 {
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compatible = "hisilicon,mipi-hikey";
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#address-cells = <2>;
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#size-cells = <2>;
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status = "ok"
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reg = <1>;
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panel-width-mm = <94>;
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panel-height-mm = <151>;
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vdd-supply = <&ldo3>;
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pwr-en-gpio = <&gpio21 3 0>;//GPIO_171
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bl-en-gpio = <&gpio6 4 0>;//GPIO_052
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pwm-gpio = <&gpio23 1 0>;//GPIO_185
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port {
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panel0_in: endpoint {
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remote-endpoint = <&dsi_out1>;
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};
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};
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};
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};
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panel_pwm {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "hisilicon,hisipwm";
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reg = <0 0xE8A04000 0 0x1000>,
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<0 0xFFF35000 0 0x1000>;
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clocks = <&crg_ctrl KIRIN970_CLK_GATE_PWM>;
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clock-names = "clk_pwm";
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pinctrl-names = "default","idle";
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pinctrl-0 = <&gpio185_pmx_func &gpio185_cfg_func>;
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pinctrl-1 = <&gpio185_pmx_idle &gpio185_cfg_idle>;
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status = "ok"
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};
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};
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