dts: arm64: add drm for hikey970.

Add dts and defconfig support HDMI&LCD display function for hikey970.

Signed-off-by: zwx305167 <zwx305167@notesmail.huawei.com>

arch/arm64/boot/dts/hisilicon/Makefile

@@ -1,5 +1,6 @@
 dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
 dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
+dtb-$(CONFIG_ARCH_HISI) += kirin970-hikey970.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
 

arch/arm64/boot/dts/hisilicon/kirin970-drm.dtsi

@@ -0,0 +1,135 @@
+/{
+		dpe: dpe@E8600000 {
+			compatible = "hisilicon,kirin970-dpe";
+			status = "ok"
+			dss_version_tag = <0x40>;
+			// DSS, PERI_CRG, SCTRL, PCTRL, NOC_DSS_Service_Target, PMCTRL, MEDIA_CRG
+			reg = <0 0xE8600000 0 0xC0000>,
+				<0 0xFFF35000 0 0x1000>,
+				<0 0xFFF0A000 0 0x1000>,
+				<0 0xE8A09000 0 0x1000>,
+				<0 0xE86C0000 0 0x10000>,
+				<0 0xFFF31000 0 0x1000>,
+				<0 0xE87FF000 0 0x1000>;
+			// dss-pdp
+			interrupts = <0 245 4>;
+
+			/*regulator_dsssubsys-supply = <&dsssubsys>;
+			regulator_mmbuf-supply = <&mmbuf>;*/
+			clocks = <&media1_crg KIRIN970_ACLK_GATE_DSS>,
+				<&media1_crg KIRIN970_PCLK_GATE_DSS>,
+				<&media1_crg KIRIN970_CLK_GATE_EDC0>,
+				<&media1_crg KIRIN970_CLK_GATE_LDI0>,
+				<&media1_crg KIRIN970_CLK_GATE_DSS_AXI_MM>,
+				<&media1_crg KIRIN970_PCLK_GATE_MMBUF>,
+				<&crg_ctrl KIRIN970_PCLK_GATE_PCTRL>;
+
+			clock-names = "aclk_dss",
+				"pclk_dss",
+				"clk_edc0",
+				"clk_ldi0",
+				"clk_dss_axi_mm",
+				"pclk_mmbuf",
+				"pclk_pctrl";
+
+			dma-coherent;
+
+			port {
+				dpe_out: endpoint {
+					remote-endpoint = <&dsi_in>;
+				};
+			};
+
+			iommu_info {
+				start-addr = <0x8000>;
+				size = <0xbfff8000>;
+			};
+		};
+
+		dsi: dsi@E8601000 {
+			compatible = "hisilicon,kirin970-dsi";
+			status = "ok"
+			reg = <0 0xE8601000 0 0x7F000>,
+				<0 0xFFF35000 0 0x1000>,
+				<0 0xE8A09000 0 0x1000>;
+
+			clocks = <&crg_ctrl KIRIN970_CLK_GATE_TXDPHY0_REF>,
+				<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY1_REF>,
+				<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY0_CFG>,
+				<&crg_ctrl KIRIN970_CLK_GATE_TXDPHY1_CFG>,
+				<&crg_ctrl KIRIN970_PCLK_GATE_DSI0>,
+				<&crg_ctrl KIRIN970_PCLK_GATE_DSI1>;
+			clock-names = "clk_txdphy0_ref",
+						"clk_txdphy1_ref",
+						"clk_txdphy0_cfg",
+						"clk_txdphy1_cfg",
+						"pclk_dsi0",
+						"pclk_dsi1";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mux-gpio = <&gpio25 7 0>;//HDMI_SEL(GPIO_207)
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi_in: endpoint {
+						remote-endpoint = <&dpe_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					dsi_out0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&adv7533_in>;
+					};
+
+					dsi_out1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&panel0_in>;
+					};
+				};
+			};
+
+			panel@1 {
+				compatible = "hisilicon,mipi-hikey";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				status = "ok"
+				reg = <1>;
+				panel-width-mm = <94>;
+				panel-height-mm = <151>;
+				vdd-supply = <&ldo3>;
+				pwr-en-gpio = <&gpio21 3 0>;//GPIO_171
+				bl-en-gpio = <&gpio6 4 0>;//GPIO_052
+				pwm-gpio = <&gpio23 1 0>;//GPIO_185
+
+				port {
+					panel0_in: endpoint {
+						remote-endpoint = <&dsi_out1>;
+					};
+				};
+			};
+		};
+
+		panel_pwm {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "hisilicon,hisipwm";
+			reg = <0 0xE8A04000 0 0x1000>,
+				<0 0xFFF35000 0 0x1000>;
+			clocks = <&crg_ctrl KIRIN970_CLK_GATE_PWM>;
+			clock-names = "clk_pwm";
+			pinctrl-names = "default","idle";
+			pinctrl-0 = <&gpio185_pmx_func &gpio185_cfg_func>;
+			pinctrl-1 = <&gpio185_pmx_idle &gpio185_cfg_idle>;
+			status = "ok"
+		};
+};

arch/arm64/boot/dts/hisilicon/kirin970-hikey970.dts

@@ -14,9 +14,9 @@
 #include "kirin970_spmi.dtsi"
 #include "hisi_6421v600_pmic_spmi.dtsi"
 #include "kirin970-gpu.dtsi"
-
 #include "kirin970-ion.dtsi"
 #include "kirin970-coresight.dtsi"
+#include "kirin970-drm.dtsi"
 / {
 	model = "HiKey970";
 	compatible = "Hisilicon,kirin970-hikey970", "Hisilicon,kirin970";
@@ -163,8 +163,6 @@
 		interrupts = <0 290 4>, <0 291 4>, <0 292 4>;
 		clocks = <&media2_crg KIRIN970_CLK_GATE_VDECFREQ>;
 		clock-names = "clk_gate_vdecfreq";
-		/*clocks = <&clk_gate_vdec>;*/
-		/*clock-names = "clk_vdec";*/
 		dec_clk_rate = <450000000>, <300000000>, <185000000>;
 		vdec_fpga = <0x1>;
 		status = "ok"
@@ -180,8 +178,6 @@
 		interrupts = <0 296 4>, <0 297 4>, <0 298 4>;
 		clocks = <&media2_crg KIRIN970_CLK_GATE_VENCFREQ>;
 		clock-names = "clk_gate_vencfreq";
-		/*clocks = <&clk_gate_venc &venc_volt_hold>;*/
-		/*clock-names = "clk_venc", "venc_volt_hold";*/
 		enc_clk_rate = <554000000>, <450000000>, <238000000>;
 		venc_fpga = <0x1>;
 		status = "ok"

arch/arm64/boot/dts/hisilicon/kirin970.dtsi

@@ -1342,8 +1342,8 @@
 			resets = <&crg_rst 0x78 27>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
-			status = "disabled";
-			/*
+			status = "ok"
+
 			adv7533: adv7533@39 {
 				status = "ok"
 				compatible = "adi,adv7533";
@@ -1364,7 +1364,6 @@
 					};
 				};
 			};
-			*/
 		};
 
 		hisi_pd: pd_dpm {
@@ -1468,7 +1467,7 @@
 			interrupt-names = "asp_dma_irq";
 			status = "ok"
 		};
-		/*
+
 		sound {
 			compatible = "simple-audio-card";
 			simple-audio-card,name = "hikey-hdmi";
@@ -1485,6 +1484,5 @@
 				sound-dai = <&adv7533>;
 			};
 		};
-		*/
 	};
 };

arch/arm64/configs/hikey970_defconfig

@@ -450,11 +450,11 @@ CONFIG_DRM_NOUVEAU=m
 CONFIG_DRM_TEGRA=m
 CONFIG_DRM_PANEL_SIMPLE=m
 CONFIG_DRM_I2C_ADV7511=m
-# CONFIG_DRM_I2C_ADV7533 is not set
+CONFIG_DRM_I2C_ADV7533=m
 CONFIG_DRM_HISI_KIRIN=m
-# CONFIG_DRM_KIRIN_960 is not set
-# CONFIG_HISI_FB_970 is not set
-# CONFIG_DRM_PANEL_HIKEY960_NTE300NTS is not set
+CONFIG_DRM_KIRIN_960=y
+CONFIG_HISI_FB_970=y
+CONFIG_DRM_PANEL_HIKEY960_NTE300NTS=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_BACKLIGHT_GENERIC=m